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2361 lines (2239 loc) · 229 KB
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/* LGPL - Copyright 2017-2018 - wargio */
#include "vle.h"
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#define PFMT64x "lx"
enum e_encoding_type {
E_NONE = 0,
E_X = 1,
E_XL = 2,
E_D = 3,
E_D8 = 4,
E_I16A = 5,
E_SCI8 = 6,
E_SCI8I = 7,
E_I16L = 8,
E_I16LS = 9,
E_BD24 = 10,
E_BD15 = 11,
E_IA16 = 12,
E_LI20 = 13,
E_M = 14,
E_XCR = 15,
E_XLSP = 16,
E_XRA = 17,
E_IA16U = 18,
E_SCI8CR= 19,
E_SCI8FLIP = 20,
E_BD15c = 21,
E_D8_N = 22,
E_BD15b = 23,
F_CFH = 24,
F_X_IMM = 25,
F_X_SH = 26
};
#define E_MASK_X 0x03FFF800
#define E_MASK_XL 0x03FFF801
#define E_MASK_D 0x03FFFFFF
#define E_MASK_D8 0x03FF00FF
#define E_MASK_I16A 0x03FF07FF
#define E_MASK_SCI8 0x03FF07FF
#define E_MASK_I16L 0x03FF07FF
#define E_MASK_BD24 0x01FFFFFE
#define E_MASK_BD15 0x000CFFFE
#define E_MASK_IA16 0x03FF07FF
#define E_MASK_LI20 0x03FF7FFF
#define E_MASK_M 0x03FFFFFE
#define F_MASK_CFH 0x03E0F800
enum f_encoding_type {
F_NONE = 0,
F_X = 1,
F_XO = 2,
F_EVX = 3,
F_CMP = 4,
F_DCBF = 5,
F_DCBL = 6,
F_DCI = 7,
F_EXT = 8,
F_A = 9,
F_XFX = 10,
F_XER = 11,
F_MFPR = 12,
F_MTPR = 13,
F_XRA = 14,
F_X_2 = 15,
F_AP = 16
};
#define F_MASK_X 0x03FFF800
#define F_MASK_XO 0x03FFF800
#define F_MASK_EVX 0x03FFF800
#define F_MASK_CMP 0x039FF800
#define F_MASK_DCBF 0x00FFF800
#define F_MASK_DCBL 0x01FFF800
#define F_MASK_DCI 0x00FFF800
#define F_MASK_EXT 0x03FF0000
#define F_MASK_A 0x01FFFFC0
#define F_MASK_XFX 0x03FFF800
#define F_MASK_XER 0x03FFF800
#define F_MASK_MFPR 0x03FFF800
#define F_MASK_MTPR 0x03FFF800
typedef struct {
uint16_t mask;
uint16_t shr;
uint16_t shl;
uint16_t add;
uint8_t idx;
enum field_type type;
} field_t;
typedef struct {
const char* name;
uint32_t op;
uint32_t mask;
enum e_encoding_type type;
enum op_type op_type;
enum op_condition cond;
enum field_type types[5];
} e_vle_t;
typedef struct {
const char* name;
uint16_t op;
uint16_t mask;
uint16_t n;
enum op_type op_type;
enum op_condition cond;
field_t fields[5];
} se_vle_t;
typedef struct {
const char* name;
uint32_t op;
uint32_t mask;
enum f_encoding_type type;
enum op_type op_type;
enum op_condition cond;
enum field_type types[5];
} ppc_t;
const ppc_t ppc_ops[] = {
// { "name" , op , mask , type , op_type , COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_REG, TYPE_REG}}
// 0 1 1 1 1 1 rD rA rB OE 1 0 0 0 0 1 0 1 0 Rc
// 0 1 1 1 1 1 rD rA rB OE 0 0 0 1 0 1 0 0 0 Rc
{ "add" , 0x7C000214, 0x7C000214 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "add." , 0x7C000214, 0x7C000215 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addo" , 0x7C000214, 0x7C000614 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addo." , 0x7C000214, 0x7C000615 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addc" , 0x7C000014, 0x7C000014 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addc." , 0x7C000014, 0x7C000011 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addco" , 0x7C000014, 0x7C000414 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addco." , 0x7C000014, 0x7C000415 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "adde" , 0x7C000114, 0x7C000114 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "adde." , 0x7C000114, 0x7C000111 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addeo" , 0x7C000114, 0x7C000514 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addeo." , 0x7C000114, 0x7C000515 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addme" , 0x7C0001D4, 0x7C0001D4 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addme." , 0x7C0001D4, 0x7C0001D1 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addmeo" , 0x7C0001D4, 0x7C0005D4 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addmeo." , 0x7C0001D4, 0x7C0005D5 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addze" , 0x7C000194, 0x7C000194 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addze." , 0x7C000194, 0x7C000191 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addzeo" , 0x7C000194, 0x7C000594 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "addzeo." , 0x7C000194, 0x7C000595 | F_MASK_XO , F_XO, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subf" , 0x7C000050, 0x7C000050 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subf." , 0x7C000050, 0x7C000051 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfo" , 0x7C000050, 0x7C000450 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfo." , 0x7C000050, 0x7C000451 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfc" , 0x7C000010, 0x7C000010 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfc." , 0x7C000010, 0x7C000011 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfco" , 0x7C000010, 0x7C000410 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfco." , 0x7C000010, 0x7C000411 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
/* 1e40: 7c e0 39 10 subfe r7,r0,r7 */
{ "subfe" , 0x7C000110, 0x7C000110 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfe." , 0x7C000110, 0x7C000111 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfeo" , 0x7C000510, 0x7C000510 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfeo." , 0x7C000510, 0x7C000511 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
/* { "subfic." , 0x7C000050, 0x7C000511 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}}, */
{ "subfze" , 0x7C000190, 0x7C000190 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfze." , 0x7C000190, 0x7C000191 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfzeo" , 0x7C000590, 0x7C000590 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "subfzeo." , 0x7C000590, 0x7C000591 | F_MASK_XO , F_XO, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
/* # 2718: 7c 00 01 46 wrteei 0 */
{ "wrtee" , 0x7C000106, 0x7C000106 | F_MASK_X , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
// This is a really awkward instruction to represent in this structure. the
// parameter is just bit 16
{ "wrteei" , 0x7C000146, 0x7C000146 | F_MASK_X , F_X, OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "and" , 0x7C000038, 0x7C000038 | F_MASK_X , F_XRA, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "and." , 0x7C000038, 0x7C000039 | F_MASK_X , F_XRA, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "andc" , 0x7C000078, 0x7C000078 | F_MASK_X , F_XRA, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "andc." , 0x7C000078, 0x7C000079 | F_MASK_X , F_XRA, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "or" , 0x7C000378, 0x7C000378 | F_MASK_X , F_XRA, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "or." , 0x7C000378, 0x7C000379 | F_MASK_X , F_XRA, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "orc" , 0x7C000338, 0x7C000338 | F_MASK_X , F_XRA, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "orc." , 0x7C000338, 0x7C000339 | F_MASK_X , F_XRA, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "xor" , 0x7C000278, 0x7C000278 | F_MASK_X , F_XRA, OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "xor." , 0x7C000278, 0x7C000279 | F_MASK_X , F_XRA, OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "nor" , 0x7C0000f8, 0x7C0000f8 | F_MASK_X , F_XRA, OP_TYPE_NOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "nor." , 0x7C0000f8, 0x7C0000f9 | F_MASK_X , F_XRA, OP_TYPE_NOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "brinc" , 0x1000020F, 0x1000020F | F_MASK_EVX , F_EVX, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "cmp" , 0x7C000000, 0x7C000000 | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "cmpl" , 0x7C000040, 0x7C000040 | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "cntlzd" , 0x7C000074, 0x7C000074 | F_MASK_X , F_X_2, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "cntlzd." , 0x7C000074, 0x7C000075 | F_MASK_X , F_X_2, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "cntlzw" , 0x7C000034, 0x7C000034 | F_MASK_X , F_X_2, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "cntlzw." , 0x7C000034, 0x7C000035 | F_MASK_X , F_X_2, OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "dcba" , 0x7C0005EC, 0x7C0005EC | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbf" , 0x7C0000AC, 0x7C0000AC | F_MASK_DCBF, F_DCBF, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbfep" , 0x7C0000FE, 0x7C0000FE | F_MASK_DCBF, F_DCBF, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbi" , 0x7C0003AC, 0x7C0003AC | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcblc" , 0x7C00030C, 0x7C00030C | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbst" , 0x7C00006C, 0x7C00006C | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbt" , 0x7C00022C, 0x7C00022C | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbtep" , 0x7C00027E, 0x7C00027E | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbtls" , 0x7C00014C, 0x7C00014C | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbtst" , 0x7C0001EC, 0x7C0001EC | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbtstep" , 0x7C0001FE, 0x7C0001FE | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbtstls" , 0x7C00010C, 0x7C00010C | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbz" , 0x7C0007EC, 0x7C0007EC | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcbzep" , 0x7C0007FE, 0x7C0007FE | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dci" , 0x7C00038C, 0x7C00038C | F_MASK_DCI , F_DCI, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "dcread" , 0x7C00028C, 0x7C00028C | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "dcread" , 0x7C0003CC, 0x7C0003CC | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "mulhw" , 0x7C000096, 0x7C000096 | F_MASK_XO , F_XO, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "mulhw." , 0x7C000096, 0x7C000097 | F_MASK_XO , F_XO, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "mulhwu" , 0x7C000016, 0x7C000016 | F_MASK_XO , F_XO, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "mulhwu." , 0x7C000016, 0x7C000017 | F_MASK_XO , F_XO, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "mullw" , 0x7C0001D6, 0x7C0001D6 | F_MASK_XO , F_XO, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "mullw." , 0x7C0001D6, 0x7C0001D7 | F_MASK_XO , F_XO, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divw" , 0x7C0003D6, 0x7C0003D6 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divw." , 0x7C0003D6, 0x7C0003D7 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divwo" , 0x7C0003D6, 0x7C0007D6 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divwo." , 0x7C0003D6, 0x7C0007D7 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divwu" , 0x7C000396, 0x7C000396 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divwu." , 0x7C000396, 0x7C000397 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divwuo" , 0x7C000396, 0x7C000796 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "divwuo." , 0x7C000396, 0x7C000797 | F_MASK_XO , F_XO, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "extsb" , 0x7C000774, 0x7C000774 | F_MASK_EXT , F_EXT, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "extsb." , 0x7C000774, 0x7C000775 | F_MASK_EXT , F_EXT, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "extsw" , 0x7C000734, 0x7C000734 | F_MASK_EXT , F_EXT, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "extsw." , 0x7C000734, 0x7C000735 | F_MASK_EXT , F_EXT, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "icbi" , 0x7C0007AC, 0x7C0007AC | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "icbiep" , 0x7C0007BE, 0x7C0007BE | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "icblc" , 0x7C0001CC, 0x7C0001CC | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "icbt" , 0x7C00002C, 0x7C00002C | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "icbtls" , 0x7C0003CC, 0x7C0003CC | F_MASK_DCBL, F_DCBL, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "ici" , 0x7C00078C, 0x7C00078C | F_MASK_DCI , F_DCI, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "icread" , 0x7C0007CC, 0x7C0007CC | F_MASK_X , F_X, OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
//apply only X instead of A for lt, gt, eq
{ "isellt" , 0x7C00001E, 0x7C00001E | F_MASK_X , F_AP, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "iselgt" , 0x7C00001E, 0x7C00005E | F_MASK_X , F_AP, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "iseleq" , 0x7C00001E, 0x7C00009E | F_MASK_X , F_AP, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "isel" , 0x7C00001E, 0x7C00001E | F_MASK_A , F_A, OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE}},
{ "lbepx" , 0x7C0000BE, 0x7C0000BE | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lbzux" , 0x7C0000AE, 0x7C0000AE | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lhaux" , 0x7C0002EE, 0x7C0002EE | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lhax" , 0x7C0002AE, 0x7C0002AE | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lhbrx" , 0x7C00062C, 0x7C00062C | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lhepx" , 0x7C00023E, 0x7C00023E | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lhzux" , 0x7C00026E, 0x7C00026E | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lhzx" , 0x7C00022E, 0x7C00022E | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lswi" , 0x7C0004AA, 0x7C0004AA | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "lswx" , 0x7C00042A, 0x7C00042A | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "lwarx" , 0x7C000028, 0x7C000028 | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lwarx." , 0x7C000029, 0x7C000029 | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lwbrx" , 0x7C00042C, 0x7C00042C | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lwepx" , 0x7C00003E, 0x7C00003E | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lwzux" , 0x7C00006E, 0x7C00006E | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lwzx" , 0x7C00002E, 0x7C00002E | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lbzx" , 0x7C0000AE, 0x7C0000AE | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "lbzux" , 0x7C0000EE, 0x7C0000EE | F_MASK_X , F_X, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "stbx" , 0x7C0001AE, 0x7C0001AE | F_MASK_X , F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "stbux" , 0x7C0001EE, 0x7C0001EE | F_MASK_X , F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "sthx" , 0x7C00032E, 0x7C00032E | F_MASK_X , F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "sthux" , 0x7C00036E, 0x7C00036E | F_MASK_X , F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "stwux" , 0x7C00016E, 0x7C00016E | F_MASK_X , F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "stwx" , 0x7C00012E, 0x7C00012E | F_MASK_X , F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
/* # 2584: 7c a7 e0 30 slw r7,r5,r28 */
{ "slw" , 0x7C000030, 0x7C000030 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "slw." , 0x7C000030, 0x7C000031 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "srw" , 0x7C000430, 0x7C000430 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "srw." , 0x7C000430, 0x7C000431 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "sraw" , 0x7C000630, 0x7C000630 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "sraw." , 0x7C000630, 0x7C000631 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "srawi" , 0x7C000670, 0x7C000670 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "srawi." , 0x7C000670, 0x7C000671 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
/* 1a1b6: 7c 6b 1e 70 srawi r11,r3,3 */
{ "mbar" , 0x7C0006AC, 0x7C0006AC | F_MASK_XFX , F_XFX, OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mcrxr" , 0x7C000400, 0x7C000400 | F_MASK_XER , F_XER, OP_TYPE_MOV, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mfdcr" , 0x7C000286, 0x7C000286 | F_MASK_MFPR, F_MFPR, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mfdcrux" , 0x7C000246, 0x7C000246 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mfdcrx" , 0x7C000206, 0x7C000206 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mfmsr" , 0x7C0000A6, 0x7C0000A6 | F_MASK_XFX , F_XFX, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mfctr" , 0x7C0902A6, 0x7C1902A6 | F_MASK_MTPR, F_MTPR, OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mfspr" , 0x7C0002A6, 0x7C0002A6 | F_MASK_MFPR, F_MFPR, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mtctr" , 0x7C0903A6, 0x7C1903A6 | F_MASK_MTPR, F_MTPR, OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mtspr" , 0x7C0003A6, 0x7C0003A6 | F_MASK_MTPR, F_MTPR, OP_TYPE_MOV, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mtmsr" , 0x7C000124, 0x7C000124 | F_MASK_XFX , F_XFX, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "msync" , 0x7C0004AC, 0x7C0004AC | F_MASK_XFX , F_XFX, OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
/* 32d30: 7c e6 00 d0 neg r7,r6 */
{ "neg" , 0x7C0000D0, 0x7C0000D0 | F_MASK_X , F_X, OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "neg." , 0x7C0000D0, 0x7C0000D1 | F_MASK_X , F_X, OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "nego" , 0x7C0000D0, 0x7C0004D0 | F_MASK_X , F_X, OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "nego." , 0x7C0000D0, 0x7C0004D1 | F_MASK_X , F_X, OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "tlbre" , 0x7C000764, 0x7C000764 | F_MASK_XFX , F_NONE, OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "tlbwe" , 0x7C0007A4, 0x7C0007A4 | F_MASK_XFX , F_NONE, OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
// TODO: ERM, these won't actually go through the E_XL codepatH?
// they'll actually get picked up as F_XO. thankfully, that seems to be correct still?
{ "mfcr" , 0x7C000026, 0x7C000026 | E_MASK_XL , F_XO , OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "mtcrf" , 0x7C000120, 0x7C000120 | E_MASK_XL , F_XO , OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}}, //crf rossz
// Floating point
{ "efsabs" , 0x100002C4, 0x100002C4 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsadd" , 0x100002C0, 0x100002C0 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efscfh" , 0x100402D1, 0x100402D1 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efscfsf" , 0x100002D3, 0x100002D3 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efscfsi" , 0x100002D1, 0x100002D1 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efscfuf" , 0x100002D2, 0x100002D2 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efscfui" , 0x100002D0, 0x100002D0 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efscmpgt" , 0x100002CC, 0x100002CC | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efscmpeq" , 0x100002CE, 0x100002CE | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efscmplt" , 0x100002CD, 0x100002CD | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efscth" , 0x100402D5, 0x100402D5 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsctsf" , 0x100002D7, 0x100002D7 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsctsi" , 0x100002D5, 0x100002D5 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsctsiz" , 0x100002DA, 0x100002DA | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsctuf" , 0x100002D6, 0x100002D6 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsctui" , 0x100002D4, 0x100002D4 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsctuiz" , 0x100002D8, 0x100002D8 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsdiv" , 0x100002C9, 0x100002C9 | F_MASK_X , F_X, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsmadd" , 0x100002C2, 0x100002C2 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsmax" , 0x100002B0, 0x100002B0 | F_MASK_X , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsmin" , 0x100002B1, 0x100002B1 | F_MASK_X , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsmsub" , 0x100002C3, 0x100002C3 | F_MASK_X , F_X, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsmul" , 0x100002C8, 0x100002C8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsnabs" , 0x100002C5, 0x100002C5 | F_MASK_EXT , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsneg" , 0x100002C6, 0x100002C6 | F_MASK_EXT , F_X, OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efsnmadd" , 0x100002CA, 0x100002CA | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efsnmsub" , 0x100002CB, 0x100002CB | F_MASK_X , F_X, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efssqrt" , 0x100002C7, 0x100002C7 | F_MASK_EXT , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "efssub" , 0x100002C1, 0x100002C1 | F_MASK_X , F_X, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efststeq" , 0x100002DE, 0x100002DE | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efststgt" , 0x100002DC, 0x100002DC | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "efststlt" , 0x100002DD, 0x100002DD | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// vector floats instructions
{ "evfsabs" , 0x10000284, 0x10000284 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsadd" , 0x10000280, 0x10000280 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfscfh" , 0x10040291, 0x10040291 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfscfsf" , 0x10000293, 0x10000293 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfscfsi" , 0x10000291, 0x10000291 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfscfuf" , 0x10000292, 0x10000292 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfscfui" , 0x10000290, 0x10000290 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfscmpeq" , 0x1000028E, 0x1000028E | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfscmpgt" , 0x1000028C, 0x1000028C | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfscmplt" , 0x1000028D, 0x1000028D | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfscth" , 0x10040295, 0x10040295 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsctsf" , 0x10000297, 0x10000297 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsctsi" , 0x10000295, 0x10000295 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsctsiz" , 0x1000029A, 0x1000029A | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsctuf" , 0x10000296, 0x10000296 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsctui" , 0x10000294, 0x10000294 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsctuiz" , 0x10000298, 0x10000298 | F_MASK_CFH , F_CFH, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsdiv" , 0x10000289, 0x10000289 | F_MASK_X , F_X, OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmadd" , 0x10000282, 0x10000282 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmax" , 0x100002A0, 0x100002A0 | F_MASK_X , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmin" , 0x100002A1, 0x100002A1 | F_MASK_X , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmsub" , 0x10000283, 0x10000283 | F_MASK_X , F_X, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmul" , 0x10000288, 0x10000288 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsnabs" , 0x10000285, 0x10000285 | F_MASK_EXT , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsneg" , 0x10000286, 0x10000286 | F_MASK_EXT , F_X, OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfsnmadd" , 0x1000028A, 0x1000028A | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsnmsub" , 0x1000028B, 0x1000028B | F_MASK_X , F_X, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfssqrt" , 0x10000287, 0x10000287 | F_MASK_EXT , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evfssub" , 0x10000281, 0x10000281 | F_MASK_X , F_X, OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfststeq" , 0x1000029E, 0x1000029E | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfststgt" , 0x1000029C, 0x1000029C | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfststlt" , 0x1000029D, 0x1000029D | F_MASK_CMP , F_CMP, OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// TODO to verify
{ "evfsaddsub" , 0x100002A2, 0x100002A2 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsaddsubx" , 0x100002AA, 0x100002AA | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsaddx" , 0x100002A8, 0x100002A8 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsdiff" , 0x100002A5, 0x100002A5 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsdiffsum" , 0x100002A7, 0x100002A7 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmule" , 0x100002AE, 0x100002AE | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmulo" , 0x100002AF, 0x100002AF | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsmulx" , 0x100002AC, 0x100002AC | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsubadd" , 0x100002A3, 0x100002A3 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfsubaddx" , 0x100002AB, 0x100002AB | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfssubx" , 0x100002A9, 0x100002A9 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfssum" , 0x100002A4, 0x100002A4 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evfssumdiff" , 0x100002A6, 0x100002A6 | F_MASK_X , F_X, OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// TODO from: https://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/external/gpl3/binutils/dist/opcodes/ppc-opc.c
{ "evdotpwcssi" , 0x10000080, 0x10000080 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcsmi" , 0x10000081, 0x10000081 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfr" , 0x10000082, 0x10000082 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssf" , 0x10000083, 0x10000083 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmf" , 0x10000088, 0x10000088 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmf" , 0x10000089, 0x10000089 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfr" , 0x1000008A, 0x1000008A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfr" , 0x1000008B, 0x1000008B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmf" , 0x1000008C, 0x1000008C | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmf" , 0x1000008D, 0x1000008D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfr" , 0x1000008E, 0x1000008E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfr" , 0x1000008F, 0x1000008F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssiaaw3" , 0x10000090, 0x10000090 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcsmiaaw3" , 0x10000091, 0x10000091 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfraaw3" , 0x10000092, 0x10000092 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfaaw3" , 0x10000093, 0x10000093 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfaa3" , 0x10000098, 0x10000098 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfaa3" , 0x10000099, 0x10000099 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfraa3" , 0x1000009A, 0x1000009A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfraa3" , 0x1000009B, 0x1000009B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfaa3" , 0x1000009C, 0x1000009C | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfaa3" , 0x1000009D, 0x1000009D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfraa3" , 0x1000009E, 0x1000009E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfraa3" , 0x1000009F, 0x1000009F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssia" , 0x100000A0, 0x100000A0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcsmia" , 0x100000A1, 0x100000A1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfra" , 0x100000A2, 0x100000A2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfa" , 0x100000A3, 0x100000A3 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfa" , 0x100000A8, 0x100000A8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfa" , 0x100000A9, 0x100000A9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfra" , 0x100000AA, 0x100000AA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfra" , 0x100000AB, 0x100000AB | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfa" , 0x100000AC, 0x100000AC | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfa" , 0x100000AD, 0x100000AD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfra" , 0x100000AE, 0x100000AE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfra" , 0x100000AF, 0x100000AF | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssiaaw" , 0x100000B0, 0x100000B0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcsmiaaw" , 0x100000B1, 0x100000B1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfraaw" , 0x100000B2, 0x100000B2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwcssfaaw" , 0x100000B3, 0x100000B3 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfaa" , 0x100000B8, 0x100000B8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfaa" , 0x100000B9, 0x100000B9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgasmfraa" , 0x100000BA, 0x100000BA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgasmfraa" , 0x100000BB, 0x100000BB | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfaa" , 0x100000BC, 0x100000BC | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfaa" , 0x100000BD, 0x100000BD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwgssmfraa" , 0x100000BE, 0x100000BE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwxgssmfraa" , 0x100000BF, 0x100000BF | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssi" , 0x10000100, 0x10000100 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssi" , 0x10000101, 0x10000101 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssf" , 0x10000102, 0x10000102 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssf" , 0x10000103, 0x10000103 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcsmi" , 0x10000108, 0x10000108 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcsmi" , 0x10000109, 0x10000109 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfr" , 0x1000010A, 0x1000010A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssfr" , 0x1000010B, 0x1000010B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssiaaw3" , 0x10000110, 0x10000110 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssiaaw3" , 0x10000111, 0x10000111 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfaaw3" , 0x10000112, 0x10000112 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssfaaw3" , 0x10000113, 0x10000113 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcsmiaaw3" , 0x10000118, 0x10000118 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcsmiaaw3" , 0x10000119, 0x10000119 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfraaw3" , 0x1000011A, 0x1000011A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssfraaw3" , 0x1000011B, 0x1000011B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssia" , 0x10000120, 0x10000120 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssia" , 0x10000121, 0x10000121 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfa" , 0x10000122, 0x10000122 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssfa" , 0x10000123, 0x10000123 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcsmia" , 0x10000128, 0x10000128 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcsmia" , 0x10000129, 0x10000129 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfra" , 0x1000012A, 0x1000012A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssfra" , 0x1000012B, 0x1000012B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssiaaw" , 0x10000130, 0x10000130 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssiaaw" , 0x10000131, 0x10000131 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfaaw" , 0x10000132, 0x10000132 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcsmiaaw" , 0x10000138, 0x10000138 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcsmiaaw" , 0x10000139, 0x10000139 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphihcssfraaw" , 0x1000013A, 0x1000013A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotplohcssfraaw" , 0x1000013B, 0x1000013B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphausi" , 0x10000140, 0x10000140 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassi" , 0x10000141, 0x10000141 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasusi" , 0x10000142, 0x10000142 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassf" , 0x10000143, 0x10000143 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssf" , 0x10000147, 0x10000147 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphaumi" , 0x10000148, 0x10000148 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasmi" , 0x10000149, 0x10000149 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasumi" , 0x1000014A, 0x1000014A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfr" , 0x1000014B, 0x1000014B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphssmi" , 0x1000014C, 0x1000014C | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// TODO are these correct? ^ ˇ
{ "evdotphsssi" , 0x1000014D, 0x1000014D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfr" , 0x1000014F, 0x1000014F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphausiaaw3" , 0x10000150, 0x10000150 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassiaaw3" , 0x10000151, 0x10000151 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasusiaaw3" , 0x10000152, 0x10000152 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfaaw3" , 0x10000153, 0x10000153 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssiaaw3" , 0x10000155, 0x10000155 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfaaw3" , 0x10000157, 0x10000157 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphaumiaaw3" , 0x10000158, 0x10000158 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasmiaaw3" , 0x10000159, 0x10000159 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasumiaaw3" , 0x1000015A, 0x1000015A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfraaw3" , 0x1000015B, 0x1000015B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphssmiaaw3" , 0x1000015D, 0x1000015D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfraaw3" , 0x1000015F, 0x1000015F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphausia" , 0x10000160, 0x10000160 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassia" , 0x10000161, 0x10000161 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasusia" , 0x10000162, 0x10000162 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfa" , 0x10000163, 0x10000163 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfa" , 0x10000167, 0x10000167 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphaumia" , 0x10000168, 0x10000168 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasmia" , 0x10000169, 0x10000169 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasumia" , 0x1000016A, 0x1000016A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfra" , 0x1000016B, 0x1000016B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphssmia" , 0x1000016C, 0x1000016C | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// TODO are these correct? ^ ˇ
{ "evdotphsssia" , 0x1000016D, 0x1000016D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfra" , 0x1000016F, 0x1000016F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphausiaaw" , 0x10000170, 0x10000170 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassiaaw" , 0x10000171, 0x10000171 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasusiaaw" , 0x10000172, 0x10000172 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfaaw" , 0x10000173, 0x10000173 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssiaaw" , 0x10000175, 0x10000175 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfaaw" , 0x10000177, 0x10000177 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphaumiaaw" , 0x10000178, 0x10000178 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasmiaaw" , 0x10000179, 0x10000179 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphasumiaaw" , 0x1000017A, 0x1000017A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphassfraaw" , 0x1000017B, 0x1000017B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphssmiaaw" , 0x1000017D, 0x1000017D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotphsssfraaw" , 0x1000017F, 0x1000017F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgaumi" , 0x10000180, 0x10000180 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmi" , 0x10000181, 0x10000181 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasumi" , 0x10000182, 0x10000182 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmf" , 0x10000183, 0x10000183 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmi" , 0x10000184, 0x10000184 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmf" , 0x10000185, 0x10000185 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmi" , 0x10000186, 0x10000186 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmf" , 0x10000187, 0x10000187 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbaumi" , 0x10000188, 0x10000188 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasmi" , 0x10000189, 0x10000189 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasumi" , 0x1000018A, 0x1000018A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmi" , 0x1000018E, 0x1000018E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmf" , 0x1000018F, 0x1000018F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgaumiaa3" , 0x10000190, 0x10000190 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmiaa3" , 0x10000191, 0x10000191 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasumiaa3" , 0x10000192, 0x10000192 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmfaa3" , 0x10000193, 0x10000193 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmiaa3" , 0x10000194, 0x10000194 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmfaa3" , 0x10000195, 0x10000195 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmiaa3" , 0x10000196, 0x10000196 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmfaa3" , 0x10000197, 0x10000197 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbaumiaaw3" , 0x10000198, 0x10000198 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasmiaaw3" , 0x10000199, 0x10000199 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasumiaaw3" , 0x1000019A, 0x1000019A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmiaa3" , 0x1000019E, 0x1000019E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmfaa3" , 0x1000019F, 0x1000019F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgaumia" , 0x100001A0, 0x100001A0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmia" , 0x100001A1, 0x100001A1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasumia" , 0x100001A2, 0x100001A2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmfa" , 0x100001A3, 0x100001A3 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmia" , 0x100001A4, 0x100001A4 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmfa" , 0x100001A5, 0x100001A5 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmia" , 0x100001A6, 0x100001A6 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmfa" , 0x100001A7, 0x100001A7 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbaumia" , 0x100001A8, 0x100001A8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasmia" , 0x100001A9, 0x100001A9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasumia" , 0x100001AA, 0x100001AA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmia" , 0x100001AE, 0x100001AE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmfa" , 0x100001AF, 0x100001AF | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgaumiaa" , 0x100001B0, 0x100001B0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmiaa" , 0x100001B1, 0x100001B1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasumiaa" , 0x100001B2, 0x100001B2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgasmfaa" , 0x100001B3, 0x100001B3 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmiaa" , 0x100001B4, 0x100001B4 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hgssmfaa" , 0x100001B5, 0x100001B5 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmiaa" , 0x100001B6, 0x100001B6 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgasmfaa" , 0x100001B7, 0x100001B7 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbaumiaaw" , 0x100001B8, 0x100001B8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasmiaaw" , 0x100001B9, 0x100001B9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpbasumiaaw" , 0x100001BA, 0x100001BA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmiaa" , 0x100001BE, 0x100001BE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotp4hxgssmfaa" , 0x100001BF, 0x100001BF | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwausi" , 0x100001C0, 0x100001C0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwassi" , 0x100001C1, 0x100001C1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasusi" , 0x100001C2, 0x100001C2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwaumi" , 0x100001C8, 0x100001C8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasmi" , 0x100001C9, 0x100001C9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasumi" , 0x100001CA, 0x100001CA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwssmi" , 0x100001CD, 0x100001CD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwsssi" , 0x100001CE, 0x100001CE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwausiaa3" , 0x100001D0, 0x100001D0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwassiaa3" , 0x100001D1, 0x100001D1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasusiaa3" , 0x100001D2, 0x100001D2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwsssiaa3" , 0x100001D5, 0x100001D5 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwaumiaa3" , 0x100001D8, 0x100001D8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasmiaa3" , 0x100001D9, 0x100001D9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasumiaa3" , 0x100001DA, 0x100001DA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwssmiaa3" , 0x100001DD, 0x100001DD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwausia" , 0x100001E0, 0x100001E0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwassia" , 0x100001E1, 0x100001E1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasusia" , 0x100001E2, 0x100001E2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwaumia" , 0x100001E8, 0x100001E8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasmia" , 0x100001E9, 0x100001E9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasumia" , 0x100001EA, 0x100001EA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwssmia" , 0x100001EC, 0x100001EC | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwsssia" , 0x100001ED, 0x100001ED | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwausiaa" , 0x100001F0, 0x100001F0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwassiaa" , 0x100001F1, 0x100001F1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasusiaa" , 0x100001F2, 0x100001F2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwsssiaa" , 0x100001F5, 0x100001F5 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwaumiaa" , 0x100001F8, 0x100001F8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasmiaa" , 0x100001F9, 0x100001F9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwasumiaa" , 0x100001FA, 0x100001FA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdotpwssmiaa" , 0x100001FD, 0x100001FD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddib" , 0x10000203, 0x10000203 | F_MASK_X , F_X, OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evaddih" , 0x10000201, 0x10000201 | F_MASK_X , F_X, OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsubifh" , 0x10000205, 0x10000205 | F_MASK_X , F_X_IMM, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsubifb" , 0x10000202, 0x10000202 | F_MASK_X , F_X_IMM, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evabsb" , 0x10000000 | (2 << 11) | 520, 0x10000000 | (2 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evabsh" , 0x10000000 | (4 << 11) + 520, 0x10000000 | (4 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evabsd" , 0x10000000 | (6 << 11) + 520, 0x10000000 | (6 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evabss" , 0x10000000 | (8 << 11) + 520, 0x10000000 | (8 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evabsbs" , 0x10000000 | (10 << 11) + 520, 0x10000000 | (10 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evabshs" , 0x10000000 | (12 << 11) + 520, 0x10000000 | (12 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evabsds" , 0x10000000 | (14 << 11) + 520, 0x10000000 | (14 << 11) + 520 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegwo" , 0x10000000 | (1 << 11) + 521, 0x10000000 | (1 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegb" , 0x10000000 | (2 << 11) + 521, 0x10000000 | (2 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegbo" , 0x10000000 | (3 << 11) + 521, 0x10000000 | (3 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegh" , 0x10000000 | (4 << 11) + 521, 0x10000000 | (4 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegho" , 0x10000000 | (5 << 11) + 521, 0x10000000 | (5 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegd" , 0x10000000 | (6 << 11) + 521, 0x10000000 | (6 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegs" , 0x10000000 | (8 << 11) + 521, 0x10000000 | (8 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegwos" , 0x10000000 | (9 << 11) + 521, 0x10000000 | (9 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegbs" , 0x10000000 | (10 << 11) + 521, 0x10000000 | (10 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegbos" , 0x10000000 | (11 << 11) + 521, 0x10000000 | (11 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evneghs" , 0x10000000 | (12 << 11) + 521, 0x10000000 | (12 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evneghos" , 0x10000000 | (13 << 11) + 521, 0x10000000 | (13 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evnegds" , 0x10000000 | (14 << 11) + 521, 0x10000000 | (14 << 11) + 521 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evextzb" , 0x10000000 | (1 << 11) + 522, 0x10000000 | (1 << 11) + 522 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evextsbh" , 0x10000000 | (4 << 11) + 522, 0x10000000 | (4 << 11) + 522 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evextsw" , 0x10000000 | (6 << 11) + 523, 0x10000000 | (6 << 11) + 523 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndwh" , 0x10000000 | (0 << 11) + 524, 0x10000000 | (0 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndhb" , 0x10000000 | (4 << 11) + 524, 0x10000000 | (4 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrnddw" , 0x10000000 | (6 << 11) + 524, 0x10000000 | (6 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndwhus" , 0x10000000 | (8 << 11) + 524, 0x10000000 | (8 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndwhss" , 0x10000000 | (9 << 11) + 524, 0x10000000 | (9 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndhbus" , 0x10000000 | (12 << 11) + 524, 0x10000000 | (12 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndhbss" , 0x10000000 | (13 << 11) + 524, 0x10000000 | (13 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrnddwus" , 0x10000000 | (14 << 11) + 524, 0x10000000 | (14 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrnddwss" , 0x10000000 | (15 << 11) + 524, 0x10000000 | (15 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndwnh" , 0x10000000 | (16 << 11) + 524, 0x10000000 | (16 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndhnb" , 0x10000000 | (20 << 11) + 524, 0x10000000 | (20 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrnddnw" , 0x10000000 | (22 << 11) + 524, 0x10000000 | (22 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndwnhus" , 0x10000000 | (24 << 11) + 524, 0x10000000 | (24 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndwnhss" , 0x10000000 | (25 << 11) + 524, 0x10000000 | (25 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndhnbus" , 0x10000000 | (28 << 11) + 524, 0x10000000 | (28 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrndhnbss" , 0x10000000 | (29 << 11) + 524, 0x10000000 | (29 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrnddnwus" , 0x10000000 | (30 << 11) + 524, 0x10000000 | (30 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evrnddnwss" , 0x10000000 | (31 << 11) + 524, 0x10000000 | (31 << 11) + 524 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evcntlzh" , 0x10000000 | (4 << 11) + 525, 0x10000000 | (4 << 11) + 525 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evcntlsh" , 0x10000000 | (4 << 11) + 526, 0x10000000 | (4 << 11) + 526 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evpopcntb" , 0x10000000 | (26 << 11) + 526, 0x10000000 | (26 << 11) + 526 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "circinc" , 0x10000210, 0x10000210 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evunpkhibui" , 0x10000000 | (0 << 11) + 540, 0x10000000 | (0 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpkhibsi" , 0x10000000 | (1 << 11) + 540, 0x10000000 | (1 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpkhihui" , 0x10000000 | (2 << 11) + 540, 0x10000000 | (2 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpkhihsi" , 0x10000000 | (3 << 11) + 540, 0x10000000 | (3 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklobui" , 0x10000000 | (4 << 11) + 540, 0x10000000 | (4 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklobsi" , 0x10000000 | (5 << 11) + 540, 0x10000000 | (5 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklohui" , 0x10000000 | (6 << 11) + 540, 0x10000000 | (6 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklohsi" , 0x10000000 | (7 << 11) + 540, 0x10000000 | (7 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklohf" , 0x10000000 | (8 << 11) + 540, 0x10000000 | (8 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpkhihf" , 0x10000000 | (9 << 11) + 540, 0x10000000 | (9 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklowgsf" , 0x10000000 | (12 << 11) + 540, 0x10000000 | (12 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpkhiwgsf" , 0x10000000 | (13 << 11) + 540, 0x10000000 | (13 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatsduw" , 0x10000000 | (16 << 11) + 540, 0x10000000 | (16 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatsdsw" , 0x10000000 | (17 << 11) + 540, 0x10000000 | (17 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatshub" , 0x10000000 | (18 << 11) + 540, 0x10000000 | (18 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatshsb" , 0x10000000 | (19 << 11) + 540, 0x10000000 | (19 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatuwuh" , 0x10000000 | (20 << 11) + 540, 0x10000000 | (20 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatswsh" , 0x10000000 | (21 << 11) + 540, 0x10000000 | (21 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatswuh" , 0x10000000 | (22 << 11) + 540, 0x10000000 | (22 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatuhub" , 0x10000000 | (23 << 11) + 540, 0x10000000 | (23 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatuduw" , 0x10000000 | (24 << 11) + 540, 0x10000000 | (24 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatuwsw" , 0x10000000 | (25 << 11) + 540, 0x10000000 | (25 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatshuh" , 0x10000000 | (26 << 11) + 540, 0x10000000 | (26 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatuhsh" , 0x10000000 | (27 << 11) + 540, 0x10000000 | (27 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatswuw" , 0x10000000 | (28 << 11) + 540, 0x10000000 | (28 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatswgsdf" , 0x10000000 | (29 << 11) + 540, 0x10000000 | (29 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatsbub" , 0x10000000 | (30 << 11) + 540, 0x10000000 | (30 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsatubsb" , 0x10000000 | (31 << 11) + 540, 0x10000000 | (31 << 11) + 540 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evmaxhpuw" , 0x10000000 | (0 << 11) + 541, 0x10000000 | (0 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evmaxhpsw" , 0x10000000 | (1 << 11) + 541, 0x10000000 | (1 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evmaxbpuh" , 0x10000000 | (4 << 11) + 541, 0x10000000 | (4 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evmaxbpsh" , 0x10000000 | (5 << 11) + 541, 0x10000000 | (5 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evmaxwpud" , 0x10000000 | (6 << 11) + 541, 0x10000000 | (6 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evmaxwpsd" , 0x10000000 | (7 << 11) + 541, 0x10000000 | (7 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminhpuw" , 0x10000000 | (8 << 11) + 541, 0x10000000 | (8 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminhpsw" , 0x10000000 | (9 << 11) + 541, 0x10000000 | (9 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminbpuh" , 0x10000000 | (12 << 11) + 541, 0x10000000 | (12 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminbpsh" , 0x10000000 | (13 << 11) + 541, 0x10000000 | (13 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminwpud" , 0x10000000 | (14 << 11) + 541, 0x10000000 | (14 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminwpsd" , 0x10000000 | (15 << 11) + 541, 0x10000000 | (15 << 11) + 541 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evminwpsd" , 0x1000021f, 0x1000021f | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsl" , 0x10000225, 0x10000225 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsli" , 0x10000227, 0x10000227 | F_MASK_X , F_X, OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsplatie" , 0x10000000 | (1 << 11) + 553, 0x10000000 | (1 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatib" , 0x10000000 | (2 << 11) + 553, 0x10000000 | (2 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatibe" , 0x10000000 | (3 << 11) + 553, 0x10000000 | (3 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatih" , 0x10000000 | (4 << 11) + 553, 0x10000000 | (4 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatihe" , 0x10000000 | (5 << 11) + 553, 0x10000000 | (5 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatid" , 0x10000000 | (6 << 11) + 553, 0x10000000 | (6 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatia" , 0x10000000 | (16 << 11) + 553, 0x10000000 | (16 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatiea" , 0x10000000 | (17 << 11) + 553, 0x10000000 | (17 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatiba" , 0x10000000 | (18 << 11) + 553, 0x10000000 | (18 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatibea" , 0x10000000 | (19 << 11) + 553, 0x10000000 | (19 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatiha" , 0x10000000 | (20 << 11) + 553, 0x10000000 | (20 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatihea" , 0x10000000 | (21 << 11) + 553, 0x10000000 | (21 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatida" , 0x10000000 | (22 << 11) + 553, 0x10000000 | (22 << 11) + 553 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfio" , 0x10000000 | (1 << 11) + 555, 0x10000000 | (1 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfib" , 0x10000000 | (2 << 11) + 555, 0x10000000 | (2 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfibo" , 0x10000000 | (3 << 11) + 555, 0x10000000 | (3 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfih" , 0x10000000 | (4 << 11) + 555, 0x10000000 | (4 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfiho" , 0x10000000 | (5 << 11) + 555, 0x10000000 | (5 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfid" , 0x10000000 | (6 << 11) + 555, 0x10000000 | (6 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfia" , 0x10000000 | (16 << 11) + 555, 0x10000000 | (16 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfioa" , 0x10000000 | (17 << 11) + 555, 0x10000000 | (17 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfiba" , 0x10000000 | (18 << 11) + 555, 0x10000000 | (18 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfiboa" , 0x10000000 | (19 << 11) + 555, 0x10000000 | (19 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfiha" , 0x10000000 | (20 << 11) + 555, 0x10000000 | (20 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfihoa" , 0x10000000 | (21 << 11) + 555, 0x10000000 | (21 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsplatfida" , 0x10000000 | (22 << 11) + 555, 0x10000000 | (22 << 11) + 555 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
// TODO continue here : https://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/external/gpl3/binutils/dist/opcodes/ppc-opc.c
{ "evstddu" , 0x10000361, 0x10000361 | F_MASK_X , F_X_SH, OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
{ "evunpkhihsi" , 0x10001A1C, 0x10001A1C | F_MASK_EXT , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evunpklohsi" , 0x10003A1C, 0x10003A1C | F_MASK_EXT , F_X, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evswapbhilo" , 0x10000000 | 568, 0x10000000 | 568 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswapblohi" , 0x10000000 | 569, 0x10000000 | 569 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswaphhilo" , 0x10000000 | 570, 0x10000000 | 570 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswaphlohi" , 0x10000000 | 571, 0x10000000 | 571 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswaphe" , 0x10000000 | 572, 0x10000000 | 572 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswaphhi" , 0x10000000 | 573, 0x10000000 | 573 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswaphlo" , 0x10000000 | 574, 0x10000000 | 574 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evswapho" , 0x10000000 | 575, 0x10000000 | 575 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evselbitm0" , 0x10000000 | 592, 0x10000000 | 592 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evselbitm1" , 0x10000000 | 593, 0x10000000 | 593 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evselbit" , 0x10000000 | 594, 0x10000000 | 594 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evperm" , 0x10000000 | 596, 0x10000000 | 596 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evperm2" , 0x10000000 | 597, 0x10000000 | 597 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evperm3" , 0x10000000 | 598, 0x10000000 | 598 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evxtrd" , 0x10000000 | 600, 0x10000000 | 600 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsrbu" , 0x10000000 | 608, 0x10000000 | 608 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsrbs" , 0x10000000 | 609, 0x10000000 | 609 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsrbiu" , 0x10000000 | 610, 0x10000000 | 610 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsrbis" , 0x10000000 | 611, 0x10000000 | 611 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evslb" , 0x10000000 | 612, 0x10000000 | 612 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evrlb" , 0x10000000 | 613, 0x10000000 | 613 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evslbi" , 0x10000000 | 614, 0x10000000 | 614 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evrlbi" , 0x10000000 | 615, 0x10000000 | 615 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsrhu" , 0x10000000 | 616, 0x10000000 | 616 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsrhs" , 0x10000000 | 617, 0x10000000 | 617 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsrhiu" , 0x10000000 | 618, 0x10000000 | 618 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsrhis" , 0x10000000 | 619, 0x10000000 | 619 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evslh" , 0x10000000 | 620, 0x10000000 | 620 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evrlh" , 0x10000000 | 621, 0x10000000 | 621 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evslhi" , 0x10000000 | 622, 0x10000000 | 622 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evrlhi" , 0x10000000 | 623, 0x10000000 | 623 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsru" , 0x10000000 | 624, 0x10000000 | 624 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsrs" , 0x10000000 | 625, 0x10000000 | 625 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsriu" , 0x10000000 | 626, 0x10000000 | 626 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evsris" , 0x10000000 | 627, 0x10000000 | 627 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
{ "evlvsl" , 0x10000000 | 628, 0x10000000 | 628 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evlvsr" , 0x10000000 | 629, 0x10000000 | 629 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// TODO continue here : https://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/external/gpl3/binutils/dist/opcodes/ppc-opc.c
{ "evmhusi" , 0x10000000 | 1024, 0x10000000 | 1024 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhssi" , 0x10000000 | 1025, 0x10000000 | 1025 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhsusi" , 0x10000000 | 1026, 0x10000000 | 1026 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhssf" , 0x10000000 | 1028, 0x10000000 | 1028 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhumi" , 0x10000000 | 1029, 0x10000000 | 1029 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhssfr" , 0x10000000 | 1030, 0x10000000 | 1030 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesumi" , 0x10000000 | 1034, 0x10000000 | 1034 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhosumi" , 0x10000000 | 1038, 0x10000000 | 1038 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbeumi" , 0x10000000 | 1048, 0x10000000 | 1048 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesmi" , 0x10000000 | 1049, 0x10000000 | 1049 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesumi" , 0x10000000 | 1050, 0x10000000 | 1050 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmboumi" , 0x10000000 | 1052, 0x10000000 | 1052 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosmi" , 0x10000000 | 1053, 0x10000000 | 1053 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosumi" , 0x10000000 | 1054, 0x10000000 | 1054 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesumia" , 0x10000000 | 1066, 0x10000000 | 1066 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhosumia" , 0x10000000 | 1070, 0x10000000 | 1070 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbeumia" , 0x10000000 | 1080, 0x10000000 | 1080 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesmia" , 0x10000000 | 1081, 0x10000000 | 1081 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesumia" , 0x10000000 | 1082, 0x10000000 | 1082 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmboumia" , 0x10000000 | 1084, 0x10000000 | 1084 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosmia" , 0x10000000 | 1085, 0x10000000 | 1085 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosumia" , 0x10000000 | 1086, 0x10000000 | 1086 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwusiw" , 0x10000000 | 1088, 0x10000000 | 1088 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwssiw" , 0x10000000 | 1089, 0x10000000 | 1089 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwhssfr" , 0x10000000 | 1094, 0x10000000 | 1094 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwehgsmfr" , 0x10000000 | 1110, 0x10000000 | 1110 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwehgsmf" , 0x10000000 | 1111, 0x10000000 | 1111 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwohgsmfr" , 0x10000000 | 1118, 0x10000000 | 1118 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwohgsmf" , 0x10000000 | 1119, 0x10000000 | 1119 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwhssfra" , 0x10000000 | 1126, 0x10000000 | 1126 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwehgsmfra" , 0x10000000 | 1142, 0x10000000 | 1142 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwehgsmfa" , 0x10000000 | 1143, 0x10000000 | 1143 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwohgsmfra" , 0x10000000 | 1150, 0x10000000 | 1150 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwohgsmfa" , 0x10000000 | 1151, 0x10000000 | 1151 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddusiaa" , 0x10000000 | (0 << 11) | 1152, 0x10000000 | (0 << 11) | 1152 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evaddssiaa" , 0x10000000 | (0 << 11) | 1153, 0x10000000 | (0 << 11) | 1153 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsubfusiaa" , 0x10000000 | (0 << 11) | 1154, 0x10000000 | (0 << 11) | 1154 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsubfssiaa" , 0x10000000 | (0 << 11) | 1155, 0x10000000 | (0 << 11) | 1155 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evaddsmiaa" , 0x10000000 | (0 << 11) | 1156, 0x10000000 | (0 << 11) | 1156 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsubfsmiaa" , 0x10000000 | (0 << 11) | 1158, 0x10000000 | (0 << 11) | 1158 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evaddh" , 0x10000000 | 1160, 0x10000000 | 1160 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhss" , 0x10000000 | 1161, 0x10000000 | 1161 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfh" , 0x10000000 | 1162, 0x10000000 | 1162 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhss" , 0x10000000 | 1163, 0x10000000 | 1163 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhx" , 0x10000000 | 1164, 0x10000000 | 1164 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhxss" , 0x10000000 | 1165, 0x10000000 | 1165 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhx" , 0x10000000 | 1166, 0x10000000 | 1166 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhxss" , 0x10000000 | 1167, 0x10000000 | 1167 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddd" , 0x10000000 | 1168, 0x10000000 | 1168 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evadddss" , 0x10000000 | 1169, 0x10000000 | 1169 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfd" , 0x10000000 | 1170, 0x10000000 | 1170 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfdss" , 0x10000000 | 1171, 0x10000000 | 1171 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddb" , 0x10000000 | 1172, 0x10000000 | 1172 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddbss" , 0x10000000 | 1173, 0x10000000 | 1173 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfb" , 0x10000000 | 1174, 0x10000000 | 1174 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfbss" , 0x10000000 | 1175, 0x10000000 | 1175 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfh" , 0x10000000 | 1176, 0x10000000 | 1176 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfh" , 0x10000000 | 1177, 0x10000000 | 1177 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddh" , 0x10000000 | 1178, 0x10000000 | 1178 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddhss" , 0x10000000 | 1179, 0x10000000 | 1179 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfhx" , 0x10000000 | 1180, 0x10000000 | 1180 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfhxss" , 0x10000000 | 1181, 0x10000000 | 1181 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddhx" , 0x10000000 | 1182, 0x10000000 | 1182 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddhxss" , 0x10000000 | 1183, 0x10000000 | 1183 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evadddus" , 0x10000000 | 1184, 0x10000000 | 1184 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddbus" , 0x10000000 | 1185, 0x10000000 | 1185 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfdus" , 0x10000000 | 1186, 0x10000000 | 1186 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfbus" , 0x10000000 | 1187, 0x10000000 | 1187 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwus" , 0x10000000 | 1188, 0x10000000 | 1188 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwxus" , 0x10000000 | 1189, 0x10000000 | 1189 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwus" , 0x10000000 | 1190, 0x10000000 | 1190 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwxus" , 0x10000000 | 1191, 0x10000000 | 1191 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evadd2subf2h" , 0x10000000 | 1192, 0x10000000 | 1192 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evadd2subf2hss" , 0x10000000 | 1193, 0x10000000 | 1193 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubf2add2h" , 0x10000000 | 1194, 0x10000000 | 1194 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubf2add2hss" , 0x10000000 | 1195, 0x10000000 | 1195 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhus" , 0x10000000 | 1196, 0x10000000 | 1196 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhxus" , 0x10000000 | 1197, 0x10000000 | 1197 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhus" , 0x10000000 | 1198, 0x10000000 | 1198 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhxus" , 0x10000000 | 1199, 0x10000000 | 1199 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwss" , 0x10000000 | 1201, 0x10000000 | 1201 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwss" , 0x10000000 | 1203, 0x10000000 | 1203 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwx" , 0x10000000 | 1204, 0x10000000 | 1204 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwxss" , 0x10000000 | 1205, 0x10000000 | 1205 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwx" , 0x10000000 | 1206, 0x10000000 | 1206 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwxss" , 0x10000000 | 1207, 0x10000000 | 1207 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfw" , 0x10000000 | 1208, 0x10000000 | 1208 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfwss" , 0x10000000 | 1209, 0x10000000 | 1209 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddw" , 0x10000000 | 1210, 0x10000000 | 1210 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddwss" , 0x10000000 | 1211, 0x10000000 | 1211 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfwx" , 0x10000000 | 1212, 0x10000000 | 1212 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddsubfwxss" , 0x10000000 | 1213, 0x10000000 | 1213 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddwx" , 0x10000000 | 1214, 0x10000000 | 1214 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfaddwxss" , 0x10000000 | 1215, 0x10000000 | 1215 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsumwu" , 0x10000000 | (0 << 11) | 1221, 0x10000000 | (0 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsumws" , 0x10000000 | (1 << 11) | 1221, 0x10000000 | (1 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum4bu" , 0x10000000 | (2 << 11) | 1221, 0x10000000 | (2 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum4bs" , 0x10000000 | (3 << 11) | 1221, 0x10000000 | (3 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hu" , 0x10000000 | (4 << 11) | 1221, 0x10000000 | (4 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hs" , 0x10000000 | (5 << 11) | 1221, 0x10000000 | (5 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evdiff2his" , 0x10000000 | (6 << 11) | 1221, 0x10000000 | (6 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2his" , 0x10000000 | (7 << 11) | 1221, 0x10000000 | (7 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsumwua" , 0x10000000 | (16 << 11) | 1221, 0x10000000 | (16 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsumwsa" , 0x10000000 | (17 << 11) | 1221, 0x10000000 | (17 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum4bua" , 0x10000000 | (18 << 11) | 1221, 0x10000000 | (18 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum4bsa" , 0x10000000 | (19 << 11) | 1221, 0x10000000 | (19 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hua" , 0x10000000 | (20 << 11) | 1221, 0x10000000 | (20 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hsa" , 0x10000000 | (21 << 11) | 1221, 0x10000000 | (21 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evdiff2hisa" , 0x10000000 | (22 << 11) | 1221, 0x10000000 | (22 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hisa" , 0x10000000 | (23 << 11) | 1221, 0x10000000 | (23 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsumwuaa" , 0x10000000 | (24 << 11) | 1221, 0x10000000 | (24 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsumwsaa" , 0x10000000 | (25 << 11) | 1221, 0x10000000 | (25 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum4buaaw" , 0x10000000 | (26 << 11) | 1221, 0x10000000 | (26 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum4bsaaw" , 0x10000000 | (27 << 11) | 1221, 0x10000000 | (27 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2huaaw" , 0x10000000 | (28 << 11) | 1221, 0x10000000 | (28 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hsaaw" , 0x10000000 | (29 << 11) | 1221, 0x10000000 | (29 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evdiff2hisaaw" , 0x10000000 | (30 << 11) | 1221, 0x10000000 | (30 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evsum2hisaaw" , 0x10000000 | (31 << 11) | 1221, 0x10000000 | (31 << 11) | 1221 | F_MASK_EXT , F_EXT, OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
{ "evdivwsf" , 0x100004CC, 0x100004CC | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdivwuf" , 0x100004CD, 0x100004CD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdivs" , 0x100004CE, 0x100004CE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evdivu" , 0x100004CF, 0x100004CF | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwegsi" , 0x100004D0, 0x100004D0 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwegsf" , 0x100004D1, 0x100004D1 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwegsi" , 0x100004D2, 0x100004D2 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwegsf" , 0x100004D3, 0x100004D3 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwogsi" , 0x100004D4, 0x100004D4 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddwogsf" , 0x100004D5, 0x100004D5 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwogsi" , 0x100004D6, 0x100004D6 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfwogsf" , 0x100004D7, 0x100004D7 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhhiuw" , 0x100004D8, 0x100004D8 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhhisw" , 0x100004D9, 0x100004D9 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhhiuw" , 0x100004DA, 0x100004DA | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhhisw" , 0x100004DB, 0x100004DB | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhlouw" , 0x100004DC, 0x100004DC | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evaddhlosw" , 0x100004DD, 0x100004DD | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhlouw" , 0x100004DE, 0x100004DE | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evsubfhlosw" , 0x100004DF, 0x100004DF | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesusiaaw" , 0x10000502, 0x10000502 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesusiaaw" , 0x10000506, 0x10000506 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesumiaaw" , 0x1000050A, 0x1000050A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhosumiaaw" , 0x1000050E, 0x1000050E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbeusiaah" , 0x10000510, 0x10000510 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbessiaah" , 0x10000511, 0x10000511 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesusiaah" , 0x10000512, 0x10000512 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbousiaah" , 0x10000514, 0x10000514 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbossiaah" , 0x10000515, 0x10000515 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosusiaah" , 0x10000516, 0x10000516 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbeumiaah" , 0x10000518, 0x10000518 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesmiaah" , 0x10000519, 0x10000519 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbesumiaah" , 0x1000051A, 0x1000051A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmboumiaah" , 0x1000051C, 0x1000051C | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosmiaah" , 0x1000051D, 0x1000051D | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbosumiaah" , 0x1000051E, 0x1000051E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwlusiaaw3" , 0x10000542, 0x10000542 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwlssiaaw3" , 0x10000543, 0x10000543 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwhssfraaw3" , 0x10000544, 0x10000544 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwhssfaaw3" , 0x10000545, 0x10000545 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwhssfraaw" , 0x10000546, 0x10000546 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwhssfaaw" , 0x10000547, 0x10000547 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwlumiaaw3" , 0x1000054A, 0x1000054A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwlsmiaaw3" , 0x1000054B, 0x1000054B | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwusiaa" , 0x10000550, 0x10000550 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwssiaa" , 0x10000551, 0x10000551 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwehgsmfraa" , 0x10000556, 0x10000556 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwehgsmfaa" , 0x10000557, 0x10000557 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwohgsmfraa" , 0x1000055E, 0x1000055E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmwohgsmfaa" , 0x1000055F, 0x1000055F | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesusianw" , 0x10000582, 0x10000582 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhosusianw" , 0x10000586, 0x10000586 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhesumianw" , 0x1000058A, 0x1000058A | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmhosumianw" , 0x1000058E, 0x1000058E | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
{ "evmbeusianh" , 0x10000590, 0x10000590 | F_MASK_X , F_X, OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},