vle.c

/* LGPL - Copyright 2017-2018 - wargio */
#include "vle.h"
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>

#define PFMT64x "lx"

enum e_encoding_type {
  E_NONE  = 0,
  E_X     = 1,
  E_XL    = 2,
  E_D     = 3,
  E_D8    = 4,
  E_I16A  = 5,
  E_SCI8  = 6,
  E_SCI8I = 7,
  E_I16L  = 8,
  E_I16LS = 9,
  E_BD24  = 10,
  E_BD15  = 11,
  E_IA16  = 12,
  E_LI20  = 13,
  E_M     = 14,
  E_XCR   = 15,
  E_XLSP  = 16,
  E_XRA   = 17,
  E_IA16U = 18,
  E_SCI8CR= 19,
  E_SCI8FLIP = 20,
  E_BD15c = 21,
  E_D8_N = 22,
  E_BD15b = 23,
  F_CFH = 24,
  F_X_IMM = 25,
  F_X_SH = 26
};

#define E_MASK_X    0x03FFF800
#define E_MASK_XL   0x03FFF801
#define E_MASK_D    0x03FFFFFF
#define E_MASK_D8   0x03FF00FF
#define E_MASK_I16A 0x03FF07FF
#define E_MASK_SCI8 0x03FF07FF
#define E_MASK_I16L 0x03FF07FF
#define E_MASK_BD24 0x01FFFFFE
#define E_MASK_BD15 0x000CFFFE
#define E_MASK_IA16 0x03FF07FF
#define E_MASK_LI20 0x03FF7FFF
#define E_MASK_M    0x03FFFFFE
#define F_MASK_CFH   0x03E0F800

enum f_encoding_type {
  F_NONE = 0,
  F_X    = 1,
  F_XO   = 2,
  F_EVX  = 3,
  F_CMP  = 4,
  F_DCBF = 5,
  F_DCBL = 6,
  F_DCI  = 7,
  F_EXT  = 8,
  F_A    = 9,
  F_XFX  = 10,
  F_XER  = 11,
  F_MFPR = 12,
  F_MTPR = 13,
  F_XRA  = 14,
  F_X_2  = 15,
  F_AP   = 16
};

#define F_MASK_X     0x03FFF800
#define F_MASK_XO    0x03FFF800
#define F_MASK_EVX   0x03FFF800
#define F_MASK_CMP   0x039FF800
#define F_MASK_DCBF  0x00FFF800
#define F_MASK_DCBL  0x01FFF800
#define F_MASK_DCI   0x00FFF800
#define F_MASK_EXT   0x03FF0000
#define F_MASK_A     0x01FFFFC0
#define F_MASK_XFX   0x03FFF800
#define F_MASK_XER   0x03FFF800
#define F_MASK_MFPR  0x03FFF800
#define F_MASK_MTPR  0x03FFF800

typedef struct {
  uint16_t mask;
  uint16_t shr;
  uint16_t shl;
  uint16_t add;
  uint8_t idx;
  enum field_type type;
} field_t;

typedef struct {
  const char* name;
  uint32_t op;
  uint32_t mask;
  enum e_encoding_type type;
  enum op_type op_type;
  enum op_condition cond;
  enum field_type types[5];
} e_vle_t;

typedef struct {
  const char* name;
  uint16_t op;
  uint16_t mask;
  uint16_t n;
  enum op_type op_type;
  enum op_condition cond;
  field_t fields[5];
} se_vle_t;

typedef struct {
  const char* name;
  uint32_t op;
  uint32_t mask;
  enum f_encoding_type type;
  enum op_type op_type;
  enum op_condition cond;
  enum field_type types[5];
} ppc_t;

const ppc_t ppc_ops[] = {
//  { "name"       , op        , mask                    , type   ,   op_type           , COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_REG, TYPE_REG}}
// 0 1 1 1 1 1 rD rA rB OE 1 0                0 0 0 1                0 1 0 Rc
// 0 1 1 1 1 1 rD rA rB OE 0 0                0 1 0 1                0 0 0 Rc

  { "add"        , 0x7C000214, 0x7C000214 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "add."       , 0x7C000214, 0x7C000215 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addo"       , 0x7C000214, 0x7C000614 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addo."      , 0x7C000214, 0x7C000615 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addc"       , 0x7C000014, 0x7C000014 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addc."      , 0x7C000014, 0x7C000011 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addco"      , 0x7C000014, 0x7C000414 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addco."     , 0x7C000014, 0x7C000415 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "adde"       , 0x7C000114, 0x7C000114 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "adde."      , 0x7C000114, 0x7C000111 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addeo"      , 0x7C000114, 0x7C000514 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addeo."     , 0x7C000114, 0x7C000515 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addme"      , 0x7C0001D4, 0x7C0001D4 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addme."     , 0x7C0001D4, 0x7C0001D1 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addmeo"     , 0x7C0001D4, 0x7C0005D4 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addmeo."    , 0x7C0001D4, 0x7C0005D5 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addze"      , 0x7C000194, 0x7C000194 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addze."     , 0x7C000194, 0x7C000191 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addzeo"     , 0x7C000194, 0x7C000594 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "addzeo."    , 0x7C000194, 0x7C000595 | F_MASK_XO  ,    F_XO,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "subf"       , 0x7C000050, 0x7C000050 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subf."      , 0x7C000050, 0x7C000051 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfo"      , 0x7C000050, 0x7C000450 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfo."     , 0x7C000050, 0x7C000451 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfc"      , 0x7C000010, 0x7C000010 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfc."     , 0x7C000010, 0x7C000011 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfco"     , 0x7C000010, 0x7C000410 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfco."    , 0x7C000010, 0x7C000411 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

    /* 1e40:	7c e0 39 10 	subfe   r7,r0,r7 */
  { "subfe"      , 0x7C000110, 0x7C000110 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfe."     , 0x7C000110, 0x7C000111 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfeo"     , 0x7C000510, 0x7C000510 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfeo."    , 0x7C000510, 0x7C000511 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  /* { "subfic."    , 0x7C000050, 0x7C000511 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}}, */
  { "subfze"     , 0x7C000190, 0x7C000190 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfze."    , 0x7C000190, 0x7C000191 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfzeo"    , 0x7C000590, 0x7C000590 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "subfzeo."   , 0x7C000590, 0x7C000591 | F_MASK_XO  ,    F_XO,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  /* # 2718:	7c 00 01 46 	wrteei  0 */
  { "wrtee"      , 0x7C000106, 0x7C000106 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  // This is a really awkward instruction to represent in this structure. the
  // parameter is just bit 16
  { "wrteei"     , 0x7C000146, 0x7C000146 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_IMM, TYPE_NONE, TYPE_NONE}},


  { "and"        , 0x7C000038, 0x7C000038 | F_MASK_X   ,   F_XRA,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "and."       , 0x7C000038, 0x7C000039 | F_MASK_X   ,   F_XRA,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "andc"       , 0x7C000078, 0x7C000078 | F_MASK_X   ,   F_XRA,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "andc."      , 0x7C000078, 0x7C000079 | F_MASK_X   ,   F_XRA,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "or"         , 0x7C000378, 0x7C000378 | F_MASK_X   ,   F_XRA,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "or."        , 0x7C000378, 0x7C000379 | F_MASK_X   ,   F_XRA,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "orc"        , 0x7C000338, 0x7C000338 | F_MASK_X   ,   F_XRA,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "orc."       , 0x7C000338, 0x7C000339 | F_MASK_X   ,   F_XRA,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "xor"        , 0x7C000278, 0x7C000278 | F_MASK_X   ,   F_XRA,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "xor."       , 0x7C000278, 0x7C000279 | F_MASK_X   ,   F_XRA,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "nor"        , 0x7C0000f8, 0x7C0000f8 | F_MASK_X   ,   F_XRA,   OP_TYPE_NOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "nor."       , 0x7C0000f8, 0x7C0000f9 | F_MASK_X   ,   F_XRA,   OP_TYPE_NOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "brinc"      , 0x1000020F, 0x1000020F | F_MASK_EVX ,   F_EVX,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "cmp"        , 0x7C000000, 0x7C000000 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "cmpl"       , 0x7C000040, 0x7C000040 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "cntlzd"     , 0x7C000074, 0x7C000074 | F_MASK_X   ,   F_X_2,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "cntlzd."    , 0x7C000074, 0x7C000075 | F_MASK_X   ,   F_X_2,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "cntlzw"     , 0x7C000034, 0x7C000034 | F_MASK_X   ,   F_X_2,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "cntlzw."    , 0x7C000034, 0x7C000035 | F_MASK_X   ,   F_X_2,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "dcba"       , 0x7C0005EC, 0x7C0005EC | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbf"       , 0x7C0000AC, 0x7C0000AC | F_MASK_DCBF,  F_DCBF,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbfep"     , 0x7C0000FE, 0x7C0000FE | F_MASK_DCBF,  F_DCBF,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbi"       , 0x7C0003AC, 0x7C0003AC | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcblc"      , 0x7C00030C, 0x7C00030C | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbst"      , 0x7C00006C, 0x7C00006C | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbt"       , 0x7C00022C, 0x7C00022C | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbtep"     , 0x7C00027E, 0x7C00027E | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbtls"     , 0x7C00014C, 0x7C00014C | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbtst"     , 0x7C0001EC, 0x7C0001EC | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbtstep"   , 0x7C0001FE, 0x7C0001FE | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbtstls"   , 0x7C00010C, 0x7C00010C | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbz"       , 0x7C0007EC, 0x7C0007EC | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcbzep"     , 0x7C0007FE, 0x7C0007FE | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dci"        , 0x7C00038C, 0x7C00038C | F_MASK_DCI ,   F_DCI,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "dcread"     , 0x7C00028C, 0x7C00028C | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "dcread"     , 0x7C0003CC, 0x7C0003CC | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "mulhw"      , 0x7C000096, 0x7C000096 | F_MASK_XO  ,    F_XO,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "mulhw."     , 0x7C000096, 0x7C000097 | F_MASK_XO  ,    F_XO,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "mulhwu"     , 0x7C000016, 0x7C000016 | F_MASK_XO  ,    F_XO,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "mulhwu."    , 0x7C000016, 0x7C000017 | F_MASK_XO  ,    F_XO,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "mullw"      , 0x7C0001D6, 0x7C0001D6 | F_MASK_XO  ,    F_XO,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "mullw."     , 0x7C0001D6, 0x7C0001D7 | F_MASK_XO  ,    F_XO,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divw"       , 0x7C0003D6, 0x7C0003D6 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divw."      , 0x7C0003D6, 0x7C0003D7 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divwo"      , 0x7C0003D6, 0x7C0007D6 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divwo."     , 0x7C0003D6, 0x7C0007D7 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divwu"      , 0x7C000396, 0x7C000396 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divwu."     , 0x7C000396, 0x7C000397 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divwuo"     , 0x7C000396, 0x7C000796 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "divwuo."    , 0x7C000396, 0x7C000797 | F_MASK_XO  ,    F_XO,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "extsb"      , 0x7C000774, 0x7C000774 | F_MASK_EXT ,   F_EXT,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "extsb."     , 0x7C000774, 0x7C000775 | F_MASK_EXT ,   F_EXT,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "extsw"      , 0x7C000734, 0x7C000734 | F_MASK_EXT ,   F_EXT,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "extsw."     , 0x7C000734, 0x7C000735 | F_MASK_EXT ,   F_EXT,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "icbi"       , 0x7C0007AC, 0x7C0007AC | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "icbiep"     , 0x7C0007BE, 0x7C0007BE | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "icblc"      , 0x7C0001CC, 0x7C0001CC | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "icbt"       , 0x7C00002C, 0x7C00002C | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "icbtls"     , 0x7C0003CC, 0x7C0003CC | F_MASK_DCBL,  F_DCBL,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "ici"        , 0x7C00078C, 0x7C00078C | F_MASK_DCI ,   F_DCI,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "icread"     , 0x7C0007CC, 0x7C0007CC | F_MASK_X   ,     F_X,    OP_TYPE_IO, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  //apply only X instead of A for lt, gt, eq
  { "isellt"     , 0x7C00001E, 0x7C00001E | F_MASK_X   ,     F_AP,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "iselgt"     , 0x7C00001E, 0x7C00005E | F_MASK_X   ,     F_AP,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "iseleq"     , 0x7C00001E, 0x7C00009E | F_MASK_X   ,     F_AP,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "isel"       , 0x7C00001E, 0x7C00001E | F_MASK_A   ,     F_A,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE}},
  
  { "lbepx"      , 0x7C0000BE, 0x7C0000BE | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lbzux"      , 0x7C0000AE, 0x7C0000AE | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lhaux"      , 0x7C0002EE, 0x7C0002EE | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lhax"       , 0x7C0002AE, 0x7C0002AE | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lhbrx"      , 0x7C00062C, 0x7C00062C | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lhepx"      , 0x7C00023E, 0x7C00023E | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lhzux"      , 0x7C00026E, 0x7C00026E | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lhzx"       , 0x7C00022E, 0x7C00022E | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lswi"       , 0x7C0004AA, 0x7C0004AA | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "lswx"       , 0x7C00042A, 0x7C00042A | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "lwarx"      , 0x7C000028, 0x7C000028 | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lwarx."     , 0x7C000029, 0x7C000029 | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lwbrx"      , 0x7C00042C, 0x7C00042C | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lwepx"      , 0x7C00003E, 0x7C00003E | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lwzux"      , 0x7C00006E, 0x7C00006E | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lwzx"       , 0x7C00002E, 0x7C00002E | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "lbzx"       , 0x7C0000AE, 0x7C0000AE | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "lbzux"      , 0x7C0000EE, 0x7C0000EE | F_MASK_X   ,     F_X,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "stbx"       , 0x7C0001AE, 0x7C0001AE | F_MASK_X   ,     F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "stbux"      , 0x7C0001EE, 0x7C0001EE | F_MASK_X   ,     F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "sthx"       , 0x7C00032E, 0x7C00032E | F_MASK_X   ,     F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "sthux"      , 0x7C00036E, 0x7C00036E | F_MASK_X   ,     F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "stwux"      , 0x7C00016E, 0x7C00016E | F_MASK_X   ,     F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "stwx"       , 0x7C00012E, 0x7C00012E | F_MASK_X   ,     F_X, OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

        /* # 2584:	7c a7 e0 30 	slw     r7,r5,r28 */
  { "slw"        , 0x7C000030, 0x7C000030 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "slw."       , 0x7C000030, 0x7C000031 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "srw"        , 0x7C000430, 0x7C000430 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "srw."       , 0x7C000430, 0x7C000431 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

  { "sraw"       , 0x7C000630, 0x7C000630 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "sraw."      , 0x7C000630, 0x7C000631 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "srawi"      , 0x7C000670, 0x7C000670 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "srawi."     , 0x7C000670, 0x7C000671 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

   /* 1a1b6:	7c 6b 1e 70 	srawi   r11,r3,3 */

  { "mbar"       , 0x7C0006AC, 0x7C0006AC | F_MASK_XFX ,   F_XFX,    OP_TYPE_IO, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mcrxr"      , 0x7C000400, 0x7C000400 | F_MASK_XER ,   F_XER,   OP_TYPE_MOV, COND_AL, {TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mfdcr"      , 0x7C000286, 0x7C000286 | F_MASK_MFPR,  F_MFPR,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mfdcrux"    , 0x7C000246, 0x7C000246 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mfdcrx"     , 0x7C000206, 0x7C000206 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mfmsr"      , 0x7C0000A6, 0x7C0000A6 | F_MASK_XFX ,   F_XFX,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mfctr"      , 0x7C0902A6, 0x7C1902A6 | F_MASK_MTPR,  F_MTPR,   OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mfspr"      , 0x7C0002A6, 0x7C0002A6 | F_MASK_MFPR,  F_MFPR,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mtctr"      , 0x7C0903A6, 0x7C1903A6 | F_MASK_MTPR,  F_MTPR,   OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mtspr"      , 0x7C0003A6, 0x7C0003A6 | F_MASK_MTPR,  F_MTPR,   OP_TYPE_MOV, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

  { "mtmsr"      , 0x7C000124, 0x7C000124 | F_MASK_XFX ,   F_XFX,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "msync"      , 0x7C0004AC, 0x7C0004AC | F_MASK_XFX ,   F_XFX,   OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},


   /* 32d30:	7c e6 00 d0 	neg     r7,r6 */

  { "neg"        , 0x7C0000D0, 0x7C0000D0 | F_MASK_X   ,     F_X,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "neg."       , 0x7C0000D0, 0x7C0000D1 | F_MASK_X   ,     F_X,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "nego"       , 0x7C0000D0, 0x7C0004D0 | F_MASK_X   ,     F_X,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "nego."      , 0x7C0000D0, 0x7C0004D1 | F_MASK_X   ,     F_X,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

  { "tlbre"      , 0x7C000764, 0x7C000764 | F_MASK_XFX ,  F_NONE,   OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "tlbwe"      , 0x7C0007A4, 0x7C0007A4 | F_MASK_XFX ,  F_NONE,   OP_TYPE_MOV, COND_AL, {TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  // TODO: ERM, these won't actually go through the E_XL codepatH?
  // they'll actually get picked up as F_XO. thankfully, that seems to be correct still?
  { "mfcr"       , 0x7C000026, 0x7C000026 | E_MASK_XL  ,   F_XO ,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "mtcrf"      , 0x7C000120, 0x7C000120 | E_MASK_XL  ,   F_XO ,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}}, //crf rossz
// Floating point
	{ "efsabs"     , 0x100002C4, 0x100002C4 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsadd"     , 0x100002C0, 0x100002C0 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efscfh"     , 0x100402D1, 0x100402D1 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efscfsf"    , 0x100002D3, 0x100002D3 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efscfsi"    , 0x100002D1, 0x100002D1 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efscfuf"    , 0x100002D2, 0x100002D2 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efscfui"    , 0x100002D0, 0x100002D0 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efscmpgt"   , 0x100002CC, 0x100002CC | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efscmpeq"   , 0x100002CE, 0x100002CE | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efscmplt"   , 0x100002CD, 0x100002CD | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efscth"     , 0x100402D5, 0x100402D5 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsctsf"    , 0x100002D7, 0x100002D7 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsctsi"    , 0x100002D5, 0x100002D5 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsctsiz"   , 0x100002DA, 0x100002DA | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsctuf"    , 0x100002D6, 0x100002D6 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsctui"    , 0x100002D4, 0x100002D4 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsctuiz"   , 0x100002D8, 0x100002D8 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsdiv"     , 0x100002C9, 0x100002C9 | F_MASK_X   ,     F_X,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsmadd"    , 0x100002C2, 0x100002C2 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsmax"     , 0x100002B0, 0x100002B0 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsmin"     , 0x100002B1, 0x100002B1 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsmsub"    , 0x100002C3, 0x100002C3 | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsmul"     , 0x100002C8, 0x100002C8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsnabs"    , 0x100002C5, 0x100002C5 | F_MASK_EXT ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsneg"     , 0x100002C6, 0x100002C6 | F_MASK_EXT ,     F_X,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efsnmadd"   , 0x100002CA, 0x100002CA | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efsnmsub"   , 0x100002CB, 0x100002CB | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efssqrt"    , 0x100002C7, 0x100002C7 | F_MASK_EXT ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "efssub"     , 0x100002C1, 0x100002C1 | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efststeq"   , 0x100002DE, 0x100002DE | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efststgt"   , 0x100002DC, 0x100002DC | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "efststlt"   , 0x100002DD, 0x100002DD | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// vector floats instructions
	{ "evfsabs"     , 0x10000284, 0x10000284 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsadd"     , 0x10000280, 0x10000280 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfscfh"     , 0x10040291, 0x10040291 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfscfsf"    , 0x10000293, 0x10000293 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfscfsi"    , 0x10000291, 0x10000291 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfscfuf"    , 0x10000292, 0x10000292 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfscfui"    , 0x10000290, 0x10000290 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfscmpeq"   , 0x1000028E, 0x1000028E | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfscmpgt"   , 0x1000028C, 0x1000028C | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfscmplt"   , 0x1000028D, 0x1000028D | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfscth"     , 0x10040295, 0x10040295 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsctsf"    , 0x10000297, 0x10000297 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsctsi"    , 0x10000295, 0x10000295 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsctsiz"   , 0x1000029A, 0x1000029A | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsctuf"    , 0x10000296, 0x10000296 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsctui"    , 0x10000294, 0x10000294 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsctuiz"   , 0x10000298, 0x10000298 | F_MASK_CFH ,   F_CFH,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsdiv"     , 0x10000289, 0x10000289 | F_MASK_X   ,     F_X,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmadd"    , 0x10000282, 0x10000282 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmax"     , 0x100002A0, 0x100002A0 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmin"     , 0x100002A1, 0x100002A1 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmsub"    , 0x10000283, 0x10000283 | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmul"     , 0x10000288, 0x10000288 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsnabs"    , 0x10000285, 0x10000285 | F_MASK_EXT ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsneg"     , 0x10000286, 0x10000286 | F_MASK_EXT ,     F_X,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfsnmadd"   , 0x1000028A, 0x1000028A | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsnmsub"   , 0x1000028B, 0x1000028B | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfssqrt"    , 0x10000287, 0x10000287 | F_MASK_EXT ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evfssub"     , 0x10000281, 0x10000281 | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfststeq"   , 0x1000029E, 0x1000029E | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfststgt"   , 0x1000029C, 0x1000029C | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfststlt"   , 0x1000029D, 0x1000029D | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},


// TODO to verify
	{ "evfsaddsub"     , 0x100002A2, 0x100002A2 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsaddsubx"     , 0x100002AA, 0x100002AA | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsaddx"     , 0x100002A8, 0x100002A8 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsdiff"     , 0x100002A5, 0x100002A5 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsdiffsum"     , 0x100002A7, 0x100002A7 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmule"     , 0x100002AE, 0x100002AE | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmulo"     , 0x100002AF, 0x100002AF | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsmulx"     , 0x100002AC, 0x100002AC | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsubadd"     , 0x100002A3, 0x100002A3 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfsubaddx"     , 0x100002AB, 0x100002AB | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfssubx"     , 0x100002A9, 0x100002A9 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfssum"     , 0x100002A4, 0x100002A4 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evfssumdiff"     , 0x100002A6, 0x100002A6 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
// TODO from: https://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/external/gpl3/binutils/dist/opcodes/ppc-opc.c
	{ "evdotpwcssi"     , 0x10000080, 0x10000080 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcsmi"     , 0x10000081, 0x10000081 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfr"     , 0x10000082, 0x10000082 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssf"     , 0x10000083, 0x10000083 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmf"     , 0x10000088, 0x10000088 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmf"     , 0x10000089, 0x10000089 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfr"     , 0x1000008A, 0x1000008A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfr"     , 0x1000008B, 0x1000008B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmf"     , 0x1000008C, 0x1000008C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmf"     , 0x1000008D, 0x1000008D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfr"     , 0x1000008E, 0x1000008E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfr"     , 0x1000008F, 0x1000008F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssiaaw3"     , 0x10000090, 0x10000090 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcsmiaaw3"     , 0x10000091, 0x10000091 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfraaw3"     , 0x10000092, 0x10000092 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfaaw3"     , 0x10000093, 0x10000093 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfaa3"     , 0x10000098, 0x10000098 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfaa3"     , 0x10000099, 0x10000099 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfraa3"     , 0x1000009A, 0x1000009A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfraa3"     , 0x1000009B, 0x1000009B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfaa3"     , 0x1000009C, 0x1000009C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfaa3"     , 0x1000009D, 0x1000009D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfraa3"     , 0x1000009E, 0x1000009E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfraa3"     , 0x1000009F, 0x1000009F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssia"     , 0x100000A0, 0x100000A0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcsmia"     , 0x100000A1, 0x100000A1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfra"     , 0x100000A2, 0x100000A2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfa"     , 0x100000A3, 0x100000A3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfa"     , 0x100000A8, 0x100000A8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfa"     , 0x100000A9, 0x100000A9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfra"     , 0x100000AA, 0x100000AA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfra"     , 0x100000AB, 0x100000AB | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfa"     , 0x100000AC, 0x100000AC | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfa"     , 0x100000AD, 0x100000AD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfra"     , 0x100000AE, 0x100000AE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfra"     , 0x100000AF, 0x100000AF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssiaaw"     , 0x100000B0, 0x100000B0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcsmiaaw"     , 0x100000B1, 0x100000B1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfraaw"     , 0x100000B2, 0x100000B2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwcssfaaw"     , 0x100000B3, 0x100000B3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfaa"     , 0x100000B8, 0x100000B8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfaa"     , 0x100000B9, 0x100000B9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgasmfraa"     , 0x100000BA, 0x100000BA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgasmfraa"     , 0x100000BB, 0x100000BB | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfaa"     , 0x100000BC, 0x100000BC | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfaa"     , 0x100000BD, 0x100000BD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwgssmfraa"     , 0x100000BE, 0x100000BE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwxgssmfraa"     , 0x100000BF, 0x100000BF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotphihcssi"     , 0x10000100, 0x10000100 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssi"     , 0x10000101, 0x10000101 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssf"     , 0x10000102, 0x10000102 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssf"     , 0x10000103, 0x10000103 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcsmi"     , 0x10000108, 0x10000108 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcsmi"     , 0x10000109, 0x10000109 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfr"     , 0x1000010A, 0x1000010A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssfr"     , 0x1000010B, 0x1000010B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssiaaw3"     , 0x10000110, 0x10000110 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssiaaw3"     , 0x10000111, 0x10000111 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfaaw3"     , 0x10000112, 0x10000112 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssfaaw3"     , 0x10000113, 0x10000113 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcsmiaaw3"     , 0x10000118, 0x10000118 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcsmiaaw3"     , 0x10000119, 0x10000119 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfraaw3"     , 0x1000011A, 0x1000011A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssfraaw3"     , 0x1000011B, 0x1000011B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssia"     , 0x10000120, 0x10000120 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssia"     , 0x10000121, 0x10000121 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfa"     , 0x10000122, 0x10000122 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssfa"     , 0x10000123, 0x10000123 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcsmia"     , 0x10000128, 0x10000128 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcsmia"     , 0x10000129, 0x10000129 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfra"     , 0x1000012A, 0x1000012A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssfra"     , 0x1000012B, 0x1000012B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssiaaw"     , 0x10000130, 0x10000130 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssiaaw"     , 0x10000131, 0x10000131 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfaaw"     , 0x10000132, 0x10000132 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotphihcsmiaaw"     , 0x10000138, 0x10000138 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcsmiaaw"     , 0x10000139, 0x10000139 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphihcssfraaw"     , 0x1000013A, 0x1000013A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotplohcssfraaw"     , 0x1000013B, 0x1000013B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotphausi"     , 0x10000140, 0x10000140 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassi"     , 0x10000141, 0x10000141 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasusi"     , 0x10000142, 0x10000142 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassf"     , 0x10000143, 0x10000143 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotphsssf"     , 0x10000147, 0x10000147 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphaumi"     , 0x10000148, 0x10000148 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasmi"     , 0x10000149, 0x10000149 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasumi"     , 0x1000014A, 0x1000014A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfr"     , 0x1000014B, 0x1000014B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphssmi"     , 0x1000014C, 0x1000014C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	// TODO are these correct? ^ ˇ
	{ "evdotphsssi"     , 0x1000014D, 0x1000014D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphsssfr"     , 0x1000014F, 0x1000014F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
    
	{ "evdotphausiaaw3"     , 0x10000150, 0x10000150 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassiaaw3"     , 0x10000151, 0x10000151 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasusiaaw3"     , 0x10000152, 0x10000152 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfaaw3"     , 0x10000153, 0x10000153 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotphsssiaaw3"     , 0x10000155, 0x10000155 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphsssfaaw3"     , 0x10000157, 0x10000157 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphaumiaaw3"     , 0x10000158, 0x10000158 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasmiaaw3"     , 0x10000159, 0x10000159 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasumiaaw3"     , 0x1000015A, 0x1000015A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfraaw3"     , 0x1000015B, 0x1000015B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotphssmiaaw3"     , 0x1000015D, 0x1000015D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},


	{ "evdotphsssfraaw3"     , 0x1000015F, 0x1000015F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphausia"     , 0x10000160, 0x10000160 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassia"     , 0x10000161, 0x10000161 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasusia"     , 0x10000162, 0x10000162 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfa"     , 0x10000163, 0x10000163 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotphsssfa"     , 0x10000167, 0x10000167 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphaumia"     , 0x10000168, 0x10000168 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasmia"     , 0x10000169, 0x10000169 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasumia"     , 0x1000016A, 0x1000016A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfra"     , 0x1000016B, 0x1000016B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotphssmia"     , 0x1000016C, 0x1000016C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	// TODO are these correct? ^ ˇ
	{ "evdotphsssia"     , 0x1000016D, 0x1000016D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphsssfra"     , 0x1000016F, 0x1000016F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphausiaaw"     , 0x10000170, 0x10000170 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassiaaw"     , 0x10000171, 0x10000171 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasusiaaw"     , 0x10000172, 0x10000172 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfaaw"     , 0x10000173, 0x10000173 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphsssiaaw"     , 0x10000175, 0x10000175 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphsssfaaw"     , 0x10000177, 0x10000177 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphaumiaaw"     , 0x10000178, 0x10000178 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasmiaaw"     , 0x10000179, 0x10000179 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphasumiaaw"     , 0x1000017A, 0x1000017A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphassfraaw"     , 0x1000017B, 0x1000017B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotphssmiaaw"     , 0x1000017D, 0x1000017D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotphsssfraaw"     , 0x1000017F, 0x1000017F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgaumi"     , 0x10000180, 0x10000180 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmi"     , 0x10000181, 0x10000181 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasumi"     , 0x10000182, 0x10000182 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmf"     , 0x10000183, 0x10000183 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmi"     , 0x10000184, 0x10000184 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmf"     , 0x10000185, 0x10000185 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmi"     , 0x10000186, 0x10000186 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmf"     , 0x10000187, 0x10000187 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbaumi"     , 0x10000188, 0x10000188 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasmi"     , 0x10000189, 0x10000189 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasumi"     , 0x1000018A, 0x1000018A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgssmi"     , 0x1000018E, 0x1000018E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgssmf"     , 0x1000018F, 0x1000018F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgaumiaa3"     , 0x10000190, 0x10000190 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmiaa3"     , 0x10000191, 0x10000191 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasumiaa3"     , 0x10000192, 0x10000192 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmfaa3"     , 0x10000193, 0x10000193 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmiaa3"     , 0x10000194, 0x10000194 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmfaa3"     , 0x10000195, 0x10000195 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmiaa3"     , 0x10000196, 0x10000196 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmfaa3"     , 0x10000197, 0x10000197 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbaumiaaw3"     , 0x10000198, 0x10000198 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasmiaaw3"     , 0x10000199, 0x10000199 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasumiaaw3"     , 0x1000019A, 0x1000019A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotp4hxgssmiaa3"     , 0x1000019E, 0x1000019E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgssmfaa3"     , 0x1000019F, 0x1000019F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgaumia"     , 0x100001A0, 0x100001A0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmia"     , 0x100001A1, 0x100001A1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasumia"     , 0x100001A2, 0x100001A2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmfa"     , 0x100001A3, 0x100001A3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmia"     , 0x100001A4, 0x100001A4 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmfa"     , 0x100001A5, 0x100001A5 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmia"     , 0x100001A6, 0x100001A6 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmfa"     , 0x100001A7, 0x100001A7 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbaumia"     , 0x100001A8, 0x100001A8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasmia"     , 0x100001A9, 0x100001A9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasumia"     , 0x100001AA, 0x100001AA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotp4hxgssmia"     , 0x100001AE, 0x100001AE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgssmfa"     , 0x100001AF, 0x100001AF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgaumiaa"     , 0x100001B0, 0x100001B0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmiaa"     , 0x100001B1, 0x100001B1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasumiaa"     , 0x100001B2, 0x100001B2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgasmfaa"     , 0x100001B3, 0x100001B3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmiaa"     , 0x100001B4, 0x100001B4 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hgssmfaa"     , 0x100001B5, 0x100001B5 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmiaa"     , 0x100001B6, 0x100001B6 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgasmfaa"     , 0x100001B7, 0x100001B7 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbaumiaaw"     , 0x100001B8, 0x100001B8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasmiaaw"     , 0x100001B9, 0x100001B9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpbasumiaaw"     , 0x100001BA, 0x100001BA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotp4hxgssmiaa"     , 0x100001BE, 0x100001BE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotp4hxgssmfaa"     , 0x100001BF, 0x100001BF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwausi"     , 0x100001C0, 0x100001C0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwassi"     , 0x100001C1, 0x100001C1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasusi"     , 0x100001C2, 0x100001C2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotpwaumi"     , 0x100001C8, 0x100001C8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasmi"     , 0x100001C9, 0x100001C9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasumi"     , 0x100001CA, 0x100001CA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwssmi"     , 0x100001CD, 0x100001CD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwsssi"     , 0x100001CE, 0x100001CE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwausiaa3"     , 0x100001D0, 0x100001D0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwassiaa3"     , 0x100001D1, 0x100001D1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasusiaa3"     , 0x100001D2, 0x100001D2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwsssiaa3"     , 0x100001D5, 0x100001D5 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwaumiaa3"     , 0x100001D8, 0x100001D8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasmiaa3"     , 0x100001D9, 0x100001D9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasumiaa3"     , 0x100001DA, 0x100001DA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotpwssmiaa3"     , 0x100001DD, 0x100001DD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotpwausia"     , 0x100001E0, 0x100001E0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwassia"     , 0x100001E1, 0x100001E1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasusia"     , 0x100001E2, 0x100001E2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
	{ "evdotpwaumia"     , 0x100001E8, 0x100001E8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasmia"     , 0x100001E9, 0x100001E9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasumia"     , 0x100001EA, 0x100001EA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotpwssmia"     , 0x100001EC, 0x100001EC | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwsssia"     , 0x100001ED, 0x100001ED | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotpwausiaa"     , 0x100001F0, 0x100001F0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwassiaa"     , 0x100001F1, 0x100001F1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasusiaa"     , 0x100001F2, 0x100001F2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotpwsssiaa"     , 0x100001F5, 0x100001F5 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evdotpwaumiaa"     , 0x100001F8, 0x100001F8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasmiaa"     , 0x100001F9, 0x100001F9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwasumiaa"     , 0x100001FA, 0x100001FA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdotpwssmiaa"     , 0x100001FD, 0x100001FD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evaddib"     , 0x10000203, 0x10000203 | F_MASK_X   ,     F_X,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evaddih"     , 0x10000201, 0x10000201 | F_MASK_X   ,     F_X,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},

	{ "evsubifh"     , 0x10000205, 0x10000205 | F_MASK_X ,   F_X_IMM,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsubifb"     , 0x10000202, 0x10000202 | F_MASK_X ,   F_X_IMM,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},

	
	{ "evabsb"     , 0x10000000 | (2 << 11) | 520, 0x10000000 | (2 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evabsh"     , 0x10000000 | (4 << 11) + 520, 0x10000000 | (4 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evabsd"     , 0x10000000 | (6 << 11) + 520, 0x10000000 | (6 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evabss"     , 0x10000000 | (8 << 11) + 520, 0x10000000 | (8 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evabsbs"     , 0x10000000 | (10 << 11) + 520, 0x10000000 | (10 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evabshs"     , 0x10000000 | (12 << 11) + 520, 0x10000000 | (12 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evabsds"     , 0x10000000 | (14 << 11) + 520, 0x10000000 | (14 << 11) + 520 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegwo"     , 0x10000000 | (1 << 11) + 521, 0x10000000 | (1 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegb"     , 0x10000000 | (2 << 11) + 521, 0x10000000 | (2 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegbo"     , 0x10000000 | (3 << 11) + 521, 0x10000000 | (3 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegh"     , 0x10000000 | (4 << 11) + 521, 0x10000000 | (4 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegho"     , 0x10000000 | (5 << 11) + 521, 0x10000000 | (5 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegd"     , 0x10000000 | (6 << 11) + 521, 0x10000000 | (6 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegs"     , 0x10000000 | (8 << 11) + 521, 0x10000000 | (8 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegwos"     , 0x10000000 | (9 << 11) + 521, 0x10000000 | (9 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegbs"     , 0x10000000 | (10 << 11) + 521, 0x10000000 | (10 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegbos"     , 0x10000000 | (11 << 11) + 521, 0x10000000 | (11 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evneghs"     , 0x10000000 | (12 << 11) + 521, 0x10000000 | (12 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evneghos"     , 0x10000000 | (13 << 11) + 521, 0x10000000 | (13 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnegds"     , 0x10000000 | (14 << 11) + 521, 0x10000000 | (14 << 11) + 521 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	
	{ "evextzb"     , 0x10000000 | (1 << 11) + 522, 0x10000000 | (1 << 11) + 522 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evextsbh"     , 0x10000000 | (4 << 11) + 522, 0x10000000 | (4 << 11) + 522 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evextsw"     , 0x10000000 | (6 << 11) + 523, 0x10000000 | (6 << 11) + 523 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

	{ "evrndwh"     , 0x10000000 | (0 << 11) + 524, 0x10000000 | (0 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndhb"     , 0x10000000 | (4 << 11) + 524, 0x10000000 | (4 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrnddw"     , 0x10000000 | (6 << 11) + 524, 0x10000000 | (6 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndwhus"     , 0x10000000 | (8 << 11) + 524, 0x10000000 | (8 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndwhss"     , 0x10000000 | (9 << 11) + 524, 0x10000000 | (9 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndhbus"     , 0x10000000 | (12 << 11) + 524, 0x10000000 | (12 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndhbss"     , 0x10000000 | (13 << 11) + 524, 0x10000000 | (13 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrnddwus"     , 0x10000000 | (14 << 11) + 524, 0x10000000 | (14 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrnddwss"     , 0x10000000 | (15 << 11) + 524, 0x10000000 | (15 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndwnh"     , 0x10000000 | (16 << 11) + 524, 0x10000000 | (16 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndhnb"     , 0x10000000 | (20 << 11) + 524, 0x10000000 | (20 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrnddnw"     , 0x10000000 | (22 << 11) + 524, 0x10000000 | (22 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndwnhus"     , 0x10000000 | (24 << 11) + 524, 0x10000000 | (24 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndwnhss"     , 0x10000000 | (25 << 11) + 524, 0x10000000 | (25 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndhnbus"     , 0x10000000 | (28 << 11) + 524, 0x10000000 | (28 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrndhnbss"     , 0x10000000 | (29 << 11) + 524, 0x10000000 | (29 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrnddnwus"     , 0x10000000 | (30 << 11) + 524, 0x10000000 | (30 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evrnddnwss"     , 0x10000000 | (31 << 11) + 524, 0x10000000 | (31 << 11) + 524 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	
	{ "evcntlzh"     , 0x10000000 | (4 << 11) + 525, 0x10000000 | (4 << 11) + 525 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evcntlsh"     , 0x10000000 | (4 << 11) + 526, 0x10000000 | (4 << 11) + 526 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evpopcntb"     , 0x10000000 | (26 << 11) + 526, 0x10000000 | (26 << 11) + 526 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

	{ "circinc"     , 0x10000210, 0x10000210 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evunpkhibui"     , 0x10000000 | (0 << 11) + 540, 0x10000000 | (0 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpkhibsi"     , 0x10000000 | (1 << 11) + 540, 0x10000000 | (1 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpkhihui"     , 0x10000000 | (2 << 11) + 540, 0x10000000 | (2 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpkhihsi"     , 0x10000000 | (3 << 11) + 540, 0x10000000 | (3 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklobui"     , 0x10000000 | (4 << 11) + 540, 0x10000000 | (4 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklobsi"     , 0x10000000 | (5 << 11) + 540, 0x10000000 | (5 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklohui"     , 0x10000000 | (6 << 11) + 540, 0x10000000 | (6 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklohsi"     , 0x10000000 | (7 << 11) + 540, 0x10000000 | (7 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklohf"     , 0x10000000 | (8 << 11) + 540, 0x10000000 | (8 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpkhihf"     , 0x10000000 | (9 << 11) + 540, 0x10000000 | (9 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklowgsf"     , 0x10000000 | (12 << 11) + 540, 0x10000000 | (12 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpkhiwgsf"     , 0x10000000 | (13 << 11) + 540, 0x10000000 | (13 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatsduw"     , 0x10000000 | (16 << 11) + 540, 0x10000000 | (16 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatsdsw"     , 0x10000000 | (17 << 11) + 540, 0x10000000 | (17 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatshub"     , 0x10000000 | (18 << 11) + 540, 0x10000000 | (18 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatshsb"     , 0x10000000 | (19 << 11) + 540, 0x10000000 | (19 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatuwuh"     , 0x10000000 | (20 << 11) + 540, 0x10000000 | (20 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatswsh"     , 0x10000000 | (21 << 11) + 540, 0x10000000 | (21 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatswuh"     , 0x10000000 | (22 << 11) + 540, 0x10000000 | (22 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatuhub"     , 0x10000000 | (23 << 11) + 540, 0x10000000 | (23 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatuduw"     , 0x10000000 | (24 << 11) + 540, 0x10000000 | (24 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatuwsw"     , 0x10000000 | (25 << 11) + 540, 0x10000000 | (25 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatshuh"     , 0x10000000 | (26 << 11) + 540, 0x10000000 | (26 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatuhsh"     , 0x10000000 | (27 << 11) + 540, 0x10000000 | (27 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatswuw"     , 0x10000000 | (28 << 11) + 540, 0x10000000 | (28 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatswgsdf"     , 0x10000000 | (29 << 11) + 540, 0x10000000 | (29 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatsbub"     , 0x10000000 | (30 << 11) + 540, 0x10000000 | (30 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsatubsb"     , 0x10000000 | (31 << 11) + 540, 0x10000000 | (31 << 11) + 540 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	
	{ "evmaxhpuw"     , 0x10000000 | (0 << 11) + 541, 0x10000000 | (0 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmaxhpsw"     , 0x10000000 | (1 << 11) + 541, 0x10000000 | (1 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmaxbpuh"     , 0x10000000 | (4 << 11) + 541, 0x10000000 | (4 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmaxbpsh"     , 0x10000000 | (5 << 11) + 541, 0x10000000 | (5 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmaxwpud"     , 0x10000000 | (6 << 11) + 541, 0x10000000 | (6 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmaxwpsd"     , 0x10000000 | (7 << 11) + 541, 0x10000000 | (7 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evminhpuw"     , 0x10000000 | (8 << 11) + 541, 0x10000000 | (8 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evminhpsw"     , 0x10000000 | (9 << 11) + 541, 0x10000000 | (9 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evminbpuh"     , 0x10000000 | (12 << 11) + 541, 0x10000000 | (12 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evminbpsh"     , 0x10000000 | (13 << 11) + 541, 0x10000000 | (13 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evminwpud"     , 0x10000000 | (14 << 11) + 541, 0x10000000 | (14 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evminwpsd"     , 0x10000000 | (15 << 11) + 541, 0x10000000 | (15 << 11) + 541 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

	{ "evminwpsd"     , 0x1000021f, 0x1000021f | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsl"     , 0x10000225, 0x10000225 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsli"     , 0x10000227, 0x10000227 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	
	{ "evsplatie"     , 0x10000000 | (1 << 11) + 553, 0x10000000 | (1 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatib"     , 0x10000000 | (2 << 11) + 553, 0x10000000 | (2 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatibe"     , 0x10000000 | (3 << 11) + 553, 0x10000000 | (3 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatih"     , 0x10000000 | (4 << 11) + 553, 0x10000000 | (4 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatihe"     , 0x10000000 | (5 << 11) + 553, 0x10000000 | (5 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatid"     , 0x10000000 | (6 << 11) + 553, 0x10000000 | (6 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatia"     , 0x10000000 | (16 << 11) + 553, 0x10000000 | (16 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatiea"     , 0x10000000 | (17 << 11) + 553, 0x10000000 | (17 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatiba"     , 0x10000000 | (18 << 11) + 553, 0x10000000 | (18 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatibea"     , 0x10000000 | (19 << 11) + 553, 0x10000000 | (19 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatiha"     , 0x10000000 | (20 << 11) + 553, 0x10000000 | (20 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatihea"     , 0x10000000 | (21 << 11) + 553, 0x10000000 | (21 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatida"     , 0x10000000 | (22 << 11) + 553, 0x10000000 | (22 << 11) + 553 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

	{ "evsplatfio"     , 0x10000000 | (1 << 11) + 555, 0x10000000 | (1 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfib"     , 0x10000000 | (2 << 11) + 555, 0x10000000 | (2 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfibo"     , 0x10000000 | (3 << 11) + 555, 0x10000000 | (3 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfih"     , 0x10000000 | (4 << 11) + 555, 0x10000000 | (4 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfiho"     , 0x10000000 | (5 << 11) + 555, 0x10000000 | (5 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfid"     , 0x10000000 | (6 << 11) + 555, 0x10000000 | (6 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfia"     , 0x10000000 | (16 << 11) + 555, 0x10000000 | (16 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfioa"     , 0x10000000 | (17 << 11) + 555, 0x10000000 | (17 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfiba"     , 0x10000000 | (18 << 11) + 555, 0x10000000 | (18 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfiboa"     , 0x10000000 | (19 << 11) + 555, 0x10000000 | (19 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfiha"     , 0x10000000 | (20 << 11) + 555, 0x10000000 | (20 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfihoa"     , 0x10000000 | (21 << 11) + 555, 0x10000000 | (21 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfida"     , 0x10000000 | (22 << 11) + 555, 0x10000000 | (22 << 11) + 555 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	

	// TODO continue here : https://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/external/gpl3/binutils/dist/opcodes/ppc-opc.c
	
	
	{ "evstddu"     , 0x10000361, 0x10000361 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},



	{ "evunpkhihsi"    , 0x10001A1C, 0x10001A1C | F_MASK_EXT ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evunpklohsi"    , 0x10003A1C, 0x10003A1C | F_MASK_EXT ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

	{ "evswapbhilo"     , 0x10000000 | 568, 0x10000000 | 568 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswapblohi"     , 0x10000000 | 569, 0x10000000 | 569 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswaphhilo"     , 0x10000000 | 570, 0x10000000 | 570 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswaphlohi"     , 0x10000000 | 571, 0x10000000 | 571 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswaphe"     , 0x10000000 | 572, 0x10000000 | 572 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswaphhi"     , 0x10000000 | 573, 0x10000000 | 573 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswaphlo"     , 0x10000000 | 574, 0x10000000 | 574 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evswapho"     , 0x10000000 | 575, 0x10000000 | 575 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evselbitm0"     , 0x10000000 | 592, 0x10000000 | 592 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evselbitm1"     , 0x10000000 | 593, 0x10000000 | 593 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evselbit"     , 0x10000000 | 594, 0x10000000 | 594 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evperm"     , 0x10000000 | 596, 0x10000000 | 596 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evperm2"     , 0x10000000 | 597, 0x10000000 | 597 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evperm3"     , 0x10000000 | 598, 0x10000000 | 598 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evxtrd"     , 0x10000000 | 600, 0x10000000 | 600 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrbu"     , 0x10000000 | 608, 0x10000000 | 608 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrbs"     , 0x10000000 | 609, 0x10000000 | 609 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrbiu"     , 0x10000000 | 610, 0x10000000 | 610 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsrbis"     , 0x10000000 | 611, 0x10000000 | 611 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evslb"     , 0x10000000 | 612, 0x10000000 | 612 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evrlb"     , 0x10000000 | 613, 0x10000000 | 613 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evslbi"     , 0x10000000 | 614, 0x10000000 | 614 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evrlbi"     , 0x10000000 | 615, 0x10000000 | 615 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsrhu"     , 0x10000000 | 616, 0x10000000 | 616 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrhs"     , 0x10000000 | 617, 0x10000000 | 617 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrhiu"     , 0x10000000 | 618, 0x10000000 | 618 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsrhis"     , 0x10000000 | 619, 0x10000000 | 619 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evslh"     , 0x10000000 | 620, 0x10000000 | 620 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evrlh"     , 0x10000000 | 621, 0x10000000 | 621 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evslhi"     , 0x10000000 | 622, 0x10000000 | 622 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evrlhi"     , 0x10000000 | 623, 0x10000000 | 623 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsru"     , 0x10000000 | 624, 0x10000000 | 624 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrs"     , 0x10000000 | 625, 0x10000000 | 625 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsriu"     , 0x10000000 | 626, 0x10000000 | 626 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsris"     , 0x10000000 | 627, 0x10000000 | 627 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evlvsl"     , 0x10000000 | 628, 0x10000000 | 628 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlvsr"     , 0x10000000 | 629, 0x10000000 | 629 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	
// TODO continue here : https://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/external/gpl3/binutils/dist/opcodes/ppc-opc.c

	{ "evmhusi"     , 0x10000000 | 1024, 0x10000000 | 1024 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhssi"     , 0x10000000 | 1025, 0x10000000 | 1025 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhsusi"     , 0x10000000 | 1026, 0x10000000 | 1026 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhssf"     , 0x10000000 | 1028, 0x10000000 | 1028 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhumi"     , 0x10000000 | 1029, 0x10000000 | 1029 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhssfr"     , 0x10000000 | 1030, 0x10000000 | 1030 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesumi"     , 0x10000000 | 1034, 0x10000000 | 1034 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosumi"     , 0x10000000 | 1038, 0x10000000 | 1038 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbeumi"     , 0x10000000 | 1048, 0x10000000 | 1048 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesmi"     , 0x10000000 | 1049, 0x10000000 | 1049 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesumi"     , 0x10000000 | 1050, 0x10000000 | 1050 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmboumi"     , 0x10000000 | 1052, 0x10000000 | 1052 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosmi"     , 0x10000000 | 1053, 0x10000000 | 1053 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosumi"     , 0x10000000 | 1054, 0x10000000 | 1054 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesumia"     , 0x10000000 | 1066, 0x10000000 | 1066 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosumia"     , 0x10000000 | 1070, 0x10000000 | 1070 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbeumia"     , 0x10000000 | 1080, 0x10000000 | 1080 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesmia"     , 0x10000000 | 1081, 0x10000000 | 1081 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesumia"     , 0x10000000 | 1082, 0x10000000 | 1082 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmboumia"     , 0x10000000 | 1084, 0x10000000 | 1084 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosmia"     , 0x10000000 | 1085, 0x10000000 | 1085 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosumia"     , 0x10000000 | 1086, 0x10000000 | 1086 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwusiw"     , 0x10000000 | 1088, 0x10000000 | 1088 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssiw"     , 0x10000000 | 1089, 0x10000000 | 1089 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfr"     , 0x10000000 | 1094, 0x10000000 | 1094 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfr"     , 0x10000000 | 1110, 0x10000000 | 1110 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmf"     , 0x10000000 | 1111, 0x10000000 | 1111 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfr"     , 0x10000000 | 1118, 0x10000000 | 1118 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmf"     , 0x10000000 | 1119, 0x10000000 | 1119 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfra"     , 0x10000000 | 1126, 0x10000000 | 1126 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfra"     , 0x10000000 | 1142, 0x10000000 | 1142 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfa"     , 0x10000000 | 1143, 0x10000000 | 1143 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfra"     , 0x10000000 | 1150, 0x10000000 | 1150 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfa"     , 0x10000000 | 1151, 0x10000000 | 1151 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evaddusiaa"     , 0x10000000 | (0 << 11) | 1152, 0x10000000 | (0 << 11) | 1152 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evaddssiaa"     , 0x10000000 | (0 << 11) | 1153, 0x10000000 | (0 << 11) | 1153 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfusiaa"     , 0x10000000 | (0 << 11) | 1154, 0x10000000 | (0 << 11) | 1154 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfssiaa"     , 0x10000000 | (0 << 11) | 1155, 0x10000000 | (0 << 11) | 1155 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evaddsmiaa"     , 0x10000000 | (0 << 11) | 1156, 0x10000000 | (0 << 11) | 1156 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfsmiaa"     , 0x10000000 | (0 << 11) | 1158, 0x10000000 | (0 << 11) | 1158 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

	{ "evaddh"     , 0x10000000 | 1160, 0x10000000 | 1160 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhss"     , 0x10000000 | 1161, 0x10000000 | 1161 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfh"     , 0x10000000 | 1162, 0x10000000 | 1162 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhss"     , 0x10000000 | 1163, 0x10000000 | 1163 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhx"     , 0x10000000 | 1164, 0x10000000 | 1164 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhxss"     , 0x10000000 | 1165, 0x10000000 | 1165 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhx"     , 0x10000000 | 1166, 0x10000000 | 1166 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhxss"     , 0x10000000 | 1167, 0x10000000 | 1167 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddd"     , 0x10000000 | 1168, 0x10000000 | 1168 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evadddss"     , 0x10000000 | 1169, 0x10000000 | 1169 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfd"     , 0x10000000 | 1170, 0x10000000 | 1170 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfdss"     , 0x10000000 | 1171, 0x10000000 | 1171 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddb"     , 0x10000000 | 1172, 0x10000000 | 1172 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddbss"     , 0x10000000 | 1173, 0x10000000 | 1173 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfb"     , 0x10000000 | 1174, 0x10000000 | 1174 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfbss"     , 0x10000000 | 1175, 0x10000000 | 1175 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfh"     , 0x10000000 | 1176, 0x10000000 | 1176 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfh"     , 0x10000000 | 1177, 0x10000000 | 1177 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddh"     , 0x10000000 | 1178, 0x10000000 | 1178 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddhss"     , 0x10000000 | 1179, 0x10000000 | 1179 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfhx"     , 0x10000000 | 1180, 0x10000000 | 1180 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfhxss"     , 0x10000000 | 1181, 0x10000000 | 1181 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddhx"     , 0x10000000 | 1182, 0x10000000 | 1182 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddhxss"     , 0x10000000 | 1183, 0x10000000 | 1183 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evadddus"     , 0x10000000 | 1184, 0x10000000 | 1184 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddbus"     , 0x10000000 | 1185, 0x10000000 | 1185 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfdus"     , 0x10000000 | 1186, 0x10000000 | 1186 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfbus"     , 0x10000000 | 1187, 0x10000000 | 1187 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwus"     , 0x10000000 | 1188, 0x10000000 | 1188 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwxus"     , 0x10000000 | 1189, 0x10000000 | 1189 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwus"     , 0x10000000 | 1190, 0x10000000 | 1190 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwxus"     , 0x10000000 | 1191, 0x10000000 | 1191 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evadd2subf2h"     , 0x10000000 | 1192, 0x10000000 | 1192 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evadd2subf2hss"     , 0x10000000 | 1193, 0x10000000 | 1193 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubf2add2h"     , 0x10000000 | 1194, 0x10000000 | 1194 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubf2add2hss"     , 0x10000000 | 1195, 0x10000000 | 1195 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhus"     , 0x10000000 | 1196, 0x10000000 | 1196 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhxus"     , 0x10000000 | 1197, 0x10000000 | 1197 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhus"     , 0x10000000 | 1198, 0x10000000 | 1198 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhxus"     , 0x10000000 | 1199, 0x10000000 | 1199 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwss"     , 0x10000000 | 1201, 0x10000000 | 1201 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwss"     , 0x10000000 | 1203, 0x10000000 | 1203 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwx"     , 0x10000000 | 1204, 0x10000000 | 1204 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwxss"     , 0x10000000 | 1205, 0x10000000 | 1205 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwx"     , 0x10000000 | 1206, 0x10000000 | 1206 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwxss"     , 0x10000000 | 1207, 0x10000000 | 1207 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfw"     , 0x10000000 | 1208, 0x10000000 | 1208 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfwss"     , 0x10000000 | 1209, 0x10000000 | 1209 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddw"     , 0x10000000 | 1210, 0x10000000 | 1210 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddwss"     , 0x10000000 | 1211, 0x10000000 | 1211 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfwx"     , 0x10000000 | 1212, 0x10000000 | 1212 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsubfwxss"     , 0x10000000 | 1213, 0x10000000 | 1213 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddwx"     , 0x10000000 | 1214, 0x10000000 | 1214 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfaddwxss"     , 0x10000000 | 1215, 0x10000000 | 1215 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

	{ "evsumwu"     , 0x10000000 | (0 << 11) | 1221, 0x10000000 | (0 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsumws"     , 0x10000000 | (1 << 11) | 1221, 0x10000000 | (1 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum4bu"     , 0x10000000 | (2 << 11) | 1221, 0x10000000 | (2 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum4bs"     , 0x10000000 | (3 << 11) | 1221, 0x10000000 | (3 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hu"     , 0x10000000 | (4 << 11) | 1221, 0x10000000 | (4 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hs"     , 0x10000000 | (5 << 11) | 1221, 0x10000000 | (5 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evdiff2his"     , 0x10000000 | (6 << 11) | 1221, 0x10000000 | (6 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2his"     , 0x10000000 | (7 << 11) | 1221, 0x10000000 | (7 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	
	{ "evsumwua"     , 0x10000000 | (16 << 11) | 1221, 0x10000000 | (16 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsumwsa"     , 0x10000000 | (17 << 11) | 1221, 0x10000000 | (17 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum4bua"     , 0x10000000 | (18 << 11) | 1221, 0x10000000 | (18 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum4bsa"     , 0x10000000 | (19 << 11) | 1221, 0x10000000 | (19 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hua"     , 0x10000000 | (20 << 11) | 1221, 0x10000000 | (20 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hsa"     , 0x10000000 | (21 << 11) | 1221, 0x10000000 | (21 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evdiff2hisa"     , 0x10000000 | (22 << 11) | 1221, 0x10000000 | (22 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hisa"     , 0x10000000 | (23 << 11) | 1221, 0x10000000 | (23 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsumwuaa"     , 0x10000000 | (24 << 11) | 1221, 0x10000000 | (24 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsumwsaa"     , 0x10000000 | (25 << 11) | 1221, 0x10000000 | (25 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum4buaaw"     , 0x10000000 | (26 << 11) | 1221, 0x10000000 | (26 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum4bsaaw"     , 0x10000000 | (27 << 11) | 1221, 0x10000000 | (27 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2huaaw"     , 0x10000000 | (28 << 11) | 1221, 0x10000000 | (28 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hsaaw"     , 0x10000000 | (29 << 11) | 1221, 0x10000000 | (29 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evdiff2hisaaw"     , 0x10000000 | (30 << 11) | 1221, 0x10000000 | (30 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsum2hisaaw"     , 0x10000000 | (31 << 11) | 1221, 0x10000000 | (31 << 11) | 1221 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},


	{ "evdivwsf"     , 0x100004CC, 0x100004CC | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdivwuf"     , 0x100004CD, 0x100004CD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdivs"     , 0x100004CE, 0x100004CE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdivu"     , 0x100004CF, 0x100004CF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwegsi"     , 0x100004D0, 0x100004D0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwegsf"     , 0x100004D1, 0x100004D1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwegsi"     , 0x100004D2, 0x100004D2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwegsf"     , 0x100004D3, 0x100004D3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwogsi"     , 0x100004D4, 0x100004D4 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddwogsf"     , 0x100004D5, 0x100004D5 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwogsi"     , 0x100004D6, 0x100004D6 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfwogsf"     , 0x100004D7, 0x100004D7 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhhiuw"     , 0x100004D8, 0x100004D8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhhisw"     , 0x100004D9, 0x100004D9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhhiuw"     , 0x100004DA, 0x100004DA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhhisw"     , 0x100004DB, 0x100004DB | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhlouw"     , 0x100004DC, 0x100004DC | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddhlosw"     , 0x100004DD, 0x100004DD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhlouw"     , 0x100004DE, 0x100004DE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfhlosw"     , 0x100004DF, 0x100004DF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesusiaaw"     , 0x10000502, 0x10000502 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesusiaaw"     , 0x10000506, 0x10000506 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesumiaaw"     , 0x1000050A, 0x1000050A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosumiaaw"     , 0x1000050E, 0x1000050E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbeusiaah"     , 0x10000510, 0x10000510 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbessiaah"     , 0x10000511, 0x10000511 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesusiaah"     , 0x10000512, 0x10000512 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbousiaah"     , 0x10000514, 0x10000514 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbossiaah"     , 0x10000515, 0x10000515 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosusiaah"     , 0x10000516, 0x10000516 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbeumiaah"     , 0x10000518, 0x10000518 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesmiaah"     , 0x10000519, 0x10000519 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesumiaah"     , 0x1000051A, 0x1000051A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmboumiaah"     , 0x1000051C, 0x1000051C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosmiaah"     , 0x1000051D, 0x1000051D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosumiaah"     , 0x1000051E, 0x1000051E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlusiaaw3"     , 0x10000542, 0x10000542 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlssiaaw3"     , 0x10000543, 0x10000543 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfraaw3"     , 0x10000544, 0x10000544 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfaaw3"     , 0x10000545, 0x10000545 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfraaw"     , 0x10000546, 0x10000546 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfaaw"     , 0x10000547, 0x10000547 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlumiaaw3"     , 0x1000054A, 0x1000054A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlsmiaaw3"     , 0x1000054B, 0x1000054B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwusiaa"     , 0x10000550, 0x10000550 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssiaa"     , 0x10000551, 0x10000551 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfraa"     , 0x10000556, 0x10000556 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfaa"     , 0x10000557, 0x10000557 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfraa"     , 0x1000055E, 0x1000055E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfaa"     , 0x1000055F, 0x1000055F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesusianw"     , 0x10000582, 0x10000582 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosusianw"     , 0x10000586, 0x10000586 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesumianw"     , 0x1000058A, 0x1000058A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosumianw"     , 0x1000058E, 0x1000058E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbeusianh"     , 0x10000590, 0x10000590 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbessianh"     , 0x10000591, 0x10000591 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesusianh"     , 0x10000592, 0x10000592 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbousianh"     , 0x10000594, 0x10000594 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbossianh"     , 0x10000595, 0x10000595 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosusianh"     , 0x10000596, 0x10000596 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbeumianh"     , 0x10000598, 0x10000598 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesmianh"     , 0x10000599, 0x10000599 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbesumianh"     , 0x1000059A, 0x1000059A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmboumianh"     , 0x1000059C, 0x1000059C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosmianh"     , 0x1000059D, 0x1000059D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmbosumianh"     , 0x1000059E, 0x1000059E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlusianw3"     , 0x100005C2, 0x100005C2 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlssianw3"     , 0x100005C3, 0x100005C3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfranw3"     , 0x100005C4, 0x100005C4 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfanw3"     , 0x100005C5, 0x100005C5 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfranw"     , 0x100005C6, 0x100005C6 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfanw"     , 0x100005C7, 0x100005C7 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlumianw3"     , 0x100005CA, 0x100005CA | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlsmianw3"     , 0x100005CB, 0x100005CB | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwusian"     , 0x100005D0, 0x100005D0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssian"     , 0x100005D1, 0x100005D1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfran"     , 0x100005D6, 0x100005D6 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwehgsmfan"     , 0x100005D7, 0x100005D7 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfran"     , 0x100005DE, 0x100005DE | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfan"     , 0x100005DF, 0x100005DF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwohgsmfan"     , 0x100005DF, 0x100005DF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evseteqb"     , 0x10000600, 0x10000600 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evseteqb."     , 0x10000601, 0x10000601 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evseteqh"     , 0x10000602, 0x10000602 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evseteqh."     , 0x10000603, 0x10000603 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evseteqw"     , 0x10000604, 0x10000604 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evseteqw."     , 0x10000605, 0x10000605 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgthu"     , 0x10000608, 0x10000608 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgthu."     , 0x10000609, 0x10000609 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgths"     , 0x1000060A, 0x1000060A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgths."     , 0x1000060B, 0x1000060B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtwu"     , 0x1000060C, 0x1000060C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtwu."     , 0x1000060D, 0x1000060D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtws"     , 0x1000060E, 0x1000060E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtws."     , 0x1000060F, 0x1000060F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtbu"     , 0x10000610, 0x10000610 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtbu."     , 0x10000611, 0x10000611 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtbs"     , 0x10000612, 0x10000612 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetgtbs."     , 0x10000613, 0x10000613 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltbu"     , 0x10000614, 0x10000614 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltbu."     , 0x10000615, 0x10000615 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltbs"     , 0x10000616, 0x10000616 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltbs."     , 0x10000617, 0x10000617 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetlthu"     , 0x10000618, 0x10000618 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetlthu."     , 0x10000619, 0x10000619 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetlths"     , 0x1000061A, 0x1000061A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetlths."     , 0x1000061B, 0x1000061B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltwu"     , 0x1000061C, 0x1000061C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltwu."     , 0x1000061D, 0x1000061D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltws"     , 0x1000061E, 0x1000061E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsetltws."     , 0x1000061F, 0x1000061F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsaduw"     , 0x10000620, 0x10000620 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsadsw"     , 0x10000621, 0x10000621 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad4ub"     , 0x10000622, 0x10000622 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad4sb"     , 0x10000623, 0x10000623 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad2uh"     , 0x10000624, 0x10000624 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad2sh"     , 0x10000625, 0x10000625 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsaduwa"     , 0x10000628, 0x10000628 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsadswa"     , 0x10000629, 0x10000629 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad4uba"     , 0x1000062A, 0x1000062A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad4sba"     , 0x1000062B, 0x1000062B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad2uha"     , 0x1000062C, 0x1000062C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad2sha"     , 0x1000062D, 0x1000062D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evabsdifuw"     , 0x10000630, 0x10000630 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evabsdifsw"     , 0x10000631, 0x10000631 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evabsdifub"     , 0x10000632, 0x10000632 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evabsdifsb"     , 0x10000633, 0x10000633 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evabsdifuh"     , 0x10000634, 0x10000634 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evabsdifsh"     , 0x10000635, 0x10000635 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsaduwaa"     , 0x10000638, 0x10000638 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsadswaa"     , 0x10000639, 0x10000639 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad4ubaaw"     , 0x1000063A, 0x1000063A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad4sbaaw"     , 0x1000063B, 0x1000063B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad2uhaaw"     , 0x1000063C, 0x1000063C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsad2shaaw"     , 0x1000063D, 0x1000063D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswshs"     , 0x10000643, 0x10000643 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkshsbs"     , 0x10000641, 0x10000641 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkshubs"     , 0x10000640, 0x10000640 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswuhs"     , 0x10000642, 0x10000642 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkuhubs"     , 0x10000644, 0x10000644 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkuwuhs"     , 0x10000645, 0x10000645 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswshilvs"     , 0x10000646, 0x10000646 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswgshefrs"     , 0x10000647, 0x10000647 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswshfrs"     , 0x10000648, 0x10000648 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswshilvfrs"     , 0x10000649, 0x10000649 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpksdswfrs"     , 0x1000064A, 0x1000064A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpksdshefrs"     , 0x1000064B, 0x1000064B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkuduws"     , 0x1000064C, 0x1000064C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpksdsws"     , 0x1000064D, 0x1000064D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evpkswgswfrs"     , 0x1000064E, 0x1000064E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilveh"     , 0x10000650, 0x10000650 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilveoh"     , 0x10000651, 0x10000651 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilvhih"     , 0x10000652, 0x10000652 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilvhiloh"     , 0x10000653, 0x10000653 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilvloh"     , 0x10000654, 0x10000654 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilvlohih"     , 0x10000655, 0x10000655 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilvoeh"     , 0x10000656, 0x10000656 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evilvoh"     , 0x10000657, 0x10000657 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlveb"     , 0x10000658, 0x10000658 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlveh"     , 0x10000659, 0x10000659 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlveob"     , 0x1000065A, 0x1000065A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlveoh"     , 0x1000065B, 0x1000065B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlvob"     , 0x1000065C, 0x1000065C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlvoh"     , 0x1000065D, 0x1000065D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlvoeb"     , 0x1000065E, 0x1000065E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdlvoeh"     , 0x1000065F, 0x1000065F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxbu"     , 0x10000660, 0x10000660 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxbs"     , 0x10000661, 0x10000661 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxhu"     , 0x10000662, 0x10000662 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxhs"     , 0x10000663, 0x10000663 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxwu"     , 0x10000664, 0x10000664 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxws"     , 0x10000665, 0x10000665 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxdu"     , 0x10000666, 0x10000666 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmaxds"     , 0x10000667, 0x10000667 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminbu"     , 0x10000668, 0x10000668 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminbs"     , 0x10000669, 0x10000669 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminhu"     , 0x1000066A, 0x1000066A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminhs"     , 0x1000066B, 0x1000066B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminwu"     , 0x1000066C, 0x1000066C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminws"     , 0x1000066D, 0x1000066D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmindu"     , 0x1000066E, 0x1000066E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evminds"     , 0x1000066F, 0x1000066F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgwu"     , 0x10000670, 0x10000670 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgws"     , 0x10000671, 0x10000671 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgbu"     , 0x10000672, 0x10000672 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgbs"     , 0x10000673, 0x10000673 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavghu"     , 0x10000674, 0x10000674 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavghs"     , 0x10000675, 0x10000675 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgdu"     , 0x10000676, 0x10000676 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgds"     , 0x10000677, 0x10000677 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgwur"     , 0x10000678, 0x10000678 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgwsr"     , 0x10000679, 0x10000679 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgbur"     , 0x1000067A, 0x1000067A | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgbsr"     , 0x1000067B, 0x1000067B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavghur"     , 0x1000067C, 0x1000067C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavghsr"     , 0x1000067D, 0x1000067D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgdur"     , 0x1000067E, 0x1000067E | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evavgdsr"     , 0x1000067F, 0x1000067F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},


// TODO vector
	{ "evabs"     , 0x10000208, 0x10000208 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evaddiw"     , 0x10000202, 0x10000202 | F_MASK_X ,   F_X_IMM,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evaddw"     , 0x10000200, 0x10000200 | F_MASK_X   ,     F_X,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evand"     , 0x10000211, 0x10000211 | F_MASK_X   ,     F_X,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evandc"     , 0x10000212, 0x10000212 | F_MASK_X   ,     F_X,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evcmpeq"   , 0x10000234, 0x10000234 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evcmpgts"   , 0x10000231, 0x10000231 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evcmpgtu"   , 0x10000230, 0x10000230 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evcmplts"   , 0x10000233, 0x10000233 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evcmpltu"   , 0x10000232, 0x10000232 | F_MASK_CMP ,   F_CMP,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evcntlsw"     , 0x1000020E, 0x1000020E | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evcntlzw"     , 0x1000020D, 0x1000020D | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evdivws"     , 0x100004C6, 0x100004C6 | F_MASK_X   ,     F_X,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evdivwu"     , 0x100004C7, 0x100004C7 | F_MASK_X   ,     F_X,   OP_TYPE_DIV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "eveqv"     , 0x10000219, 0x10000219 | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evextsb"     , 0x1000020A, 0x1000020A | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evextsh"     , 0x1000020B, 0x1000020B | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmergehi"     , 0x1000022C, 0x1000022C | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmergehilo"     , 0x1000022E, 0x1000022E | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmergelo"     , 0x1000022D, 0x1000022D | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmergelohi"     , 0x1000022F, 0x1000022F | F_MASK_X   ,     F_X,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evnand"     , 0x1000021E, 0x1000021E | F_MASK_X   ,     F_X,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evneg"     , 0x10000209, 0x10000209 | F_MASK_EXT ,   F_EXT,   OP_TYPE_NOT, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evnor"     , 0x10000218, 0x10000218 | F_MASK_X   ,     F_X,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evor"     , 0x10000217, 0x10000217 | F_MASK_X   ,     F_X,   OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evorc"     , 0x1000021B, 0x1000021B | F_MASK_X   ,     F_X,   OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evrlw"     , 0x10000228, 0x10000228 | F_MASK_X   ,     F_X,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evrlwi"     , 0x1000022A, 0x1000022A | F_MASK_X   ,     F_X,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	// TODO
	{ "evsrois"     , 0x10000277, 0x10000277 | F_MASK_X   ,     F_X,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evrndw"     , 0x1000020C, 0x1000020C | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	// TODO evsel
	{ "evslw"     , 0x10000224, 0x10000224 | F_MASK_X   ,     F_X,   OP_TYPE_SHL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evslwi"     , 0x10000226, 0x10000226 | F_MASK_X   ,     F_X,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsplatfi"     , 0x1000022B, 0x1000022B | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsplati"     , 0x10000229, 0x10000229 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsrwis"     , 0x10000223, 0x10000223 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsrwiu"     , 0x10000222, 0x10000222 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evsrws"     , 0x10000221, 0x10000221 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsrwsu"     , 0x10000220, 0x10000220 | F_MASK_X   ,     F_X,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubfw"     , 0x10000204, 0x10000204 | F_MASK_X   ,     F_X,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsubifw"     , 0x10000206, 0x10000206 | F_MASK_X ,   F_X_IMM,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "evxor"     , 0x10000216, 0x10000216 | F_MASK_X   ,     F_X,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsl"     , 0x10000225, 0x10000225 | F_MASK_X   ,     F_X,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evsru"     , 0x10000270, 0x10000270 | F_MASK_X   ,     F_X,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhegsmfaa"     , 0x1000052B, 0x1000052B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhegsmfan"     , 0x100005AB, 0x100005AB | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhegsmiaa"     , 0x10000529, 0x10000529 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhegsmian"     , 0x100005A9, 0x100005A9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhegumiaa"     , 0x10000528, 0x10000528 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhegumian"     , 0x100005A8, 0x100005A8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmf"     , 0x1000040B, 0x1000040B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmfa"     , 0x1000042B, 0x1000042B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmfaaw"     , 0x1000050B, 0x1000050B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmfanw"     , 0x1000058B, 0x1000058B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmi"     , 0x10000409, 0x10000409 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmia"     , 0x10000429, 0x10000429 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmiaaw"     , 0x10000509, 0x10000509 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhesmianw"     , 0x10000589, 0x10000589 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhessf"     , 0x10000403, 0x10000403 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhessfa"     , 0x10000423, 0x10000423 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhessfaaw"     , 0x10000503, 0x10000503 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhessfanw"     , 0x10000583, 0x10000583 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhessiaaw"     , 0x10000501, 0x10000501 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhessianw"     , 0x10000581, 0x10000581 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmheumi"     , 0x10000408, 0x10000408 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmheumia"     , 0x10000428, 0x10000428 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmheumiaaw"     , 0x10000508, 0x10000508 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmheumianw"     , 0x10000588, 0x10000588 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmheusiaaw"     , 0x10000500, 0x10000500 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmheusianw"     , 0x10000580, 0x10000580 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhogsmfaa"     , 0x1000052F, 0x1000052F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhogsmfan"     , 0x100005AF, 0x100005AF | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhogsmiaa"     , 0x1000052D, 0x1000052D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhogsmian"     , 0x100005AD, 0x100005AD | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhogumiaa"     , 0x1000052C, 0x1000052C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhogumian"     , 0x100005AC, 0x100005AC | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmf"     , 0x1000040F, 0x1000040F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmfa"     , 0x1000042F, 0x1000042F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmfaaw"     , 0x1000050F, 0x1000050F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmfanw"     , 0x1000058F, 0x1000058F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmi"     , 0x1000040D, 0x1000040D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmia"     , 0x1000042D, 0x1000042D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmiaaw"     , 0x1000050D, 0x1000050D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhosmianw"     , 0x1000058D, 0x1000058D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhossf"     , 0x10000407, 0x10000407 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhossfa"     , 0x10000427, 0x10000427 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhossfaaw"     , 0x10000507, 0x10000507 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhossfanw"     , 0x10000587, 0x10000587 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhossiaaw"     , 0x10000505, 0x10000505 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhossianw"     , 0x10000585, 0x10000585 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhoumi"     , 0x1000040C, 0x1000040C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhoumia"     , 0x1000042C, 0x1000042C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhoumiaaw"     , 0x1000050C, 0x1000050C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhoumianw"     , 0x1000058C, 0x1000058C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhousiaaw"     , 0x10000504, 0x10000504 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmhousianw"     , 0x10000584, 0x10000584 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhsmf"     , 0x1000044F, 0x1000044F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhsmfa"     , 0x1000046F, 0x1000046F | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhsmi"     , 0x1000044D, 0x1000044D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhsmia"     , 0x1000046D, 0x1000046D | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssf"     , 0x10000447, 0x10000447 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhssfa"     , 0x10000467, 0x10000467 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhumi"     , 0x1000044C, 0x1000044C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwhumia"     , 0x1000046C, 0x1000046C | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlsmiaaw"     , 0x10000549, 0x10000549 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlsmianw"     , 0x100005C9, 0x100005C9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlssiaaw"     , 0x10000541, 0x10000541 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlssianw"     , 0x100005C1, 0x100005C1 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlumi"     , 0x10000448, 0x10000448 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlumia"     , 0x10000468, 0x10000468 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlumiaaw"     , 0x10000548, 0x10000548 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlumianw"     , 0x100005C8, 0x100005C8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlusiaaw"     , 0x10000540, 0x10000540 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwlusianw"     , 0x100005C0, 0x100005C0 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmf"     , 0x1000045B, 0x1000045B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmfa"     , 0x1000047B, 0x1000047B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmfaa"     , 0x1000055B, 0x1000055B | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmfan"     , 0x100005DB, 0x100005DB | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmi"     , 0x10000459, 0x10000459 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmia"     , 0x10000479, 0x10000479 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmiaa"     , 0x10000559, 0x10000559 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwsmian"     , 0x100005D9, 0x100005D9 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssf"     , 0x10000453, 0x10000453 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssfa"     , 0x10000473, 0x10000473 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssfaa"     , 0x10000553, 0x10000553 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwssfan"     , 0x100005D3, 0x100005D3 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwumi"     , 0x10000458, 0x10000458 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwumia"     , 0x10000478, 0x10000478 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwumiaa"     , 0x10000558, 0x10000558 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evmwumian"     , 0x100005D8, 0x100005D8 | F_MASK_X   ,     F_X,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evaddsmiaaw"     , 0x100004C9, 0x100004C9 | F_MASK_EXT ,   F_EXT,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evaddssiaaw"     , 0x100004C1, 0x100004C1 | F_MASK_EXT ,   F_EXT,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evaddumiaaw"     , 0x100004C8, 0x100004C8 | F_MASK_EXT ,   F_EXT,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evaddusiaaw"     , 0x100004C0, 0x100004C0 | F_MASK_EXT ,   F_EXT,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfsmiaaw"     , 0x100004CB, 0x100004CB | F_MASK_EXT ,   F_EXT,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfssiaaw"     , 0x100004C3, 0x100004C3 | F_MASK_EXT ,   F_EXT,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfumiaaw"     , 0x100004CA, 0x100004CA | F_MASK_EXT ,   F_EXT,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evsubfusiaaw"     , 0x100004C2, 0x100004C2 | F_MASK_EXT ,   F_EXT,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evmra"     , 0x100004C4, 0x100004C4 | F_MASK_EXT ,   F_EXT,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "evldd"     , 0x10000301, 0x10000301 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlddu"     , 0x10000341, 0x10000341 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlddx"     , 0x10000300, 0x10000300 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evldw"     , 0x10000303, 0x10000303 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evldwx"     , 0x10000302, 0x10000302 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evldh"     , 0x10000305, 0x10000305 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evldhx"     , 0x10000304, 0x10000304 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlwhe"     , 0x10000311, 0x10000311 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlwhex"     , 0x10000310, 0x10000310 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlwhou"     , 0x10000315, 0x10000315 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlwhoux"     , 0x10000314, 0x10000314 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlwhos"     , 0x10000317, 0x10000317 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlwhosx"     , 0x10000316, 0x10000316 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlwwsplat"     , 0x10000319, 0x10000319 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlwwsplatx"     , 0x10000318, 0x10000318 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlwhsplat"     , 0x1000031D, 0x1000031D | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlwhsplatx"     , 0x1000031C, 0x1000031C | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlhhesplat"     , 0x10000309, 0x10000309 | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlhhesplatx"     , 0x10000308, 0x10000308 | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlhhesplat"     , 0x1000030D, 0x1000030D | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlhhousplatx"     , 0x1000030C, 0x1000030C | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evlhhossplat"     , 0x1000030F, 0x1000030F | F_MASK_X   ,     F_X_SH,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evlhhousplatx"     , 0x1000030E, 0x1000030E | F_MASK_X   ,     F_X,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstdd"     , 0x10000321, 0x10000321 | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstddx"     , 0x10000320, 0x10000320 | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstdw"     , 0x10000323, 0x10000323 | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstdwx"     , 0x10000322, 0x10000322 | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstdh"     , 0x10000325, 0x10000325 | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstdhx"     , 0x10000324, 0x10000324 | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstwwe"     , 0x10000339, 0x10000339 | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstwwex"     , 0x10000338, 0x10000338 | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstwwo"     , 0x1000033D, 0x1000033D | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstwwox"     , 0x1000033C, 0x1000033C | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstwhe"     , 0x10000331, 0x10000331 | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstwhex"     , 0x10000330, 0x10000330 | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "evstwho"     , 0x10000335, 0x10000335 | F_MASK_X   ,     F_X_SH,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "evstwhox"     , 0x10000334, 0x10000334 | F_MASK_X   ,     F_X,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},

};

const e_vle_t e_ops[] = {
//  { "name"       , op        , mask                    , type   ,   op_type           , COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_REG, TYPE_REG}}
	{ "e_add16i"    , 0x1C000000, 0x1F000000 | E_MASK_D   , E_D     ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_add2i."    , 0x70008800, 0x70008800 | E_MASK_I16A, E_I16A  ,   OP_TYPE_ADD, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_add2is"    , 0x70009000, 0x70009000 | E_MASK_I16A, E_I16A  ,   OP_TYPE_ADD, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_addi"      , 0x18008000, 0x18008000 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_addi."     , 0x18008800, 0x18008800 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_addic"     , 0x18009000, 0x18009000 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_addic."    , 0x18009800, 0x18009800 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_and2i."    , 0x7000C800, 0x7000C800 | E_MASK_I16L, E_I16L  ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_and2is."   , 0x7000E800, 0x7000E800 | E_MASK_I16L, E_I16LS ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_andi"      , 0x1800C000, 0x1800C000 | E_MASK_SCI8, E_SCI8I ,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_andi."     , 0x1800C800, 0x1800C800 | E_MASK_SCI8, E_SCI8I ,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	// has cr0-cr3   // TODO conditions
	{ "e_bge"       , 0x7A000000, 0x7A000000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_GE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_ble"       , 0x7A000000, 0x7A010000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_LE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bne"       , 0x7A000000, 0x7A020000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_NE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bns"       , 0x7A000000, 0x7A030000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_VC, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_blt"       , 0x7A000000, 0x7A100000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_LT, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bgt"       , 0x7A000000, 0x7A110000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_GT, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_beq"       , 0x7A000000, 0x7A120000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_EQ, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bso"       , 0x7A000000, 0x7A130000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_VS, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bc"        , 0x7A000000, 0x7A140000 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CJMP, COND_VS, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bgel"      , 0x7A000001, 0x7A000001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_GE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_blel"      , 0x7A000001, 0x7A010001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_LE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bnel"      , 0x7A000001, 0x7A020001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_NE, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bnsl"      , 0x7A000001, 0x7A030001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_VC, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bltl"      , 0x7A000001, 0x7A110001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_LT, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bgtl"      , 0x7A000001, 0x7A120001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_GT, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_beql"      , 0x7A000001, 0x7A130001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_EQ, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bsol"      , 0x7A000001, 0x7A140001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_VS, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bcl"       , 0x7A000001, 0x7A140001 | E_MASK_BD15, E_BD15  ,   OP_TYPE_CCALL, COND_VS, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	// has cr0-cr3    
	// TODO review
	{ "e_bdnz"      , 0x7A200000, 0x7A200000 | E_MASK_BD15, E_BD15c ,   OP_TYPE_CJMP, COND_NE, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bdnzl"     , 0x7A200001, 0x7A200001 | E_MASK_BD15, E_BD15c ,   OP_TYPE_CJMP, COND_NE, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bdz"       , 0x7A300000, 0x7A300000 | E_MASK_BD15, E_BD15c ,   OP_TYPE_CJMP, COND_EQ, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bdzl"      , 0x7A300001, 0x7A300001 | E_MASK_BD15, E_BD15c ,   OP_TYPE_CJMP, COND_EQ, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bl"        , 0x78000001, 0x78000001 | E_MASK_BD24, E_BD24  ,   OP_TYPE_CALL, COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_b"         , 0x78000000, 0x78000000 | E_MASK_BD24, E_BD24  ,   OP_TYPE_JMP, COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_bc"        , 0x7A000000, 0x7A200000 | E_MASK_BD15, E_BD15b ,   OP_TYPE_CJMP, COND_VS, {TYPE_IMM, TYPE_IMM, TYPE_JMP, TYPE_NONE, TYPE_NONE}},
	{ "e_bcl"       , 0x7A000001, 0x7A200001 | E_MASK_BD15, E_BD15b ,   OP_TYPE_CCALL, COND_VS, {TYPE_IMM, TYPE_IMM, TYPE_JMP, TYPE_NONE, TYPE_NONE}},
	{ "e_cmp16i"    , 0x70009800, 0x70009800 | E_MASK_IA16, E_IA16  ,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_cmph"      , 0x7C00001C, 0x7C00001D | E_MASK_X   , E_XCR   ,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "e_cmph16i"   , 0x7000B000, 0x7000B000 | E_MASK_IA16, E_IA16  ,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_cmphl"     , 0x7C00005C, 0x7C00005D | E_MASK_X   , E_XCR   ,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "e_cmphl16i"  , 0x7000B800, 0x7000B800 | E_MASK_IA16, E_IA16U ,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_cmpl16i"   , 0x7000A800, 0x7000A800 | E_MASK_IA16, E_IA16U ,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_cmpli"     , 0x1880A800, 0x1880A800 | E_MASK_SCI8, E_SCI8CR,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_cmpi"      , 0x1800A800, 0x1800A800 | E_MASK_SCI8, E_SCI8CR,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_crand"     , 0x7C000202, 0x7C000202 | E_MASK_XL  , E_XL    ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_crandc"    , 0x7C000102, 0x7C000102 | E_MASK_XL  , E_XL    ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_creqv"     , 0x7C000242, 0x7C000242 | E_MASK_XL  , E_XL    ,   OP_TYPE_XOR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_crnand"    , 0x7C0001C2, 0x7C0001C2 | E_MASK_XL  , E_XL    ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_crnor"     , 0x7C000042, 0x7C000042 | E_MASK_XL  , E_XL    ,   OP_TYPE_NOR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_cror"      , 0x7C000382, 0x7C000382 | E_MASK_XL  , E_XL    ,   OP_TYPE_OR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_crorc"     , 0x7C000342, 0x7C000342 | E_MASK_XL  , E_XL    ,   OP_TYPE_OR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_crxor"     , 0x7C000182, 0x7C000182 | E_MASK_XL  , E_XL    ,   OP_TYPE_XOR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
	{ "e_lbz"       , 0x30000000, 0x30000000 | E_MASK_D   , E_D     ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lbzu"      , 0x18000000, 0x18000000 | E_MASK_D8  , E_D8    ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lha"       , 0x38000000, 0x38000000 | E_MASK_D   , E_D     ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lhau"      , 0x18000300, 0x18000300 | E_MASK_D8  , E_D8    ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lhz"       , 0x58000000, 0x58000000 | E_MASK_D   , E_D     ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lhzu"      , 0x18000100, 0x18000100 | E_MASK_D8  , E_D8    ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_li"        , 0x70000000, 0x70000000 | E_MASK_LI20, E_LI20  ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lis"       , 0x7000E000, 0x7000E000 | E_MASK_I16L, E_I16LS ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmw"       , 0x18000800, 0x18000800 | E_MASK_D8  , E_D8    ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lwz"       , 0x50000000, 0x53000000 | E_MASK_D   , E_D     ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_lwzu"      , 0x18000200, 0x18000200 | E_MASK_D8  , E_D8    ,   OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_mcrf"      , 0x7C000020, 0x7C000020 | E_MASK_XL  , E_XLSP  ,   OP_TYPE_MOV, COND_AL, {TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_mull2i"    , 0x7000A000, 0x7000A000 | E_MASK_I16A, E_I16A  ,   OP_TYPE_MUL, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_mulli"     , 0x1800A000, 0x1800A000 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_or2i"      , 0x7000C000, 0x7000C000 | E_MASK_I16L, E_I16L  ,   OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_or2is"     , 0x7000D000, 0x7000D000 | E_MASK_I16L, E_I16LS ,   OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_ori"       , 0x1800D000, 0x1800D000 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_ori."      , 0x1800D800, 0x1800D800 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_rlw"       , 0x7C000230, 0x7C000230 | E_MASK_X   , E_XRA   ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "e_rlw."      , 0x7C000231, 0x7C000231 | E_MASK_X   , E_XRA   ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
	{ "e_rlwi"      , 0x7C000270, 0x7C000270 | E_MASK_X   , E_XRA   ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_rlwi."     , 0x7C000271, 0x7C000271 | E_MASK_X   , E_XRA   ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_rlwimi"    , 0x74000000, 0x74000000 | E_MASK_M   , E_M     ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_rlwinm"    , 0x74000001, 0x74000001 | E_MASK_M   , E_M     ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_slwi"      , 0x7C000070, 0x7C000070 | E_MASK_X   , E_XRA   ,   OP_TYPE_SHL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_slwi."     , 0x7C000071, 0x7C000071 | E_MASK_X   , E_XRA   ,   OP_TYPE_SHL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_srwi"      , 0x7C000470, 0x7C000470 | E_MASK_X   , E_XRA   ,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_srwi."     , 0x7C000471, 0x7C000471 | E_MASK_X   , E_XRA   ,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
	{ "e_stb"       , 0x34000000, 0x34000000 | E_MASK_D   , E_D     ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_stbu"      , 0x18000400, 0x18000400 | E_MASK_D8  , E_D8    ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_sth"       , 0x5C000000, 0x5C000000 | E_MASK_D   , E_D     ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_sthu"      , 0x18000500, 0x18000500 | E_MASK_D8  , E_D8    ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_stmw"      , 0x18000900, 0x18000900 | E_MASK_D8  , E_D8    ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_stw"       , 0x54000000, 0x56000000 | E_MASK_D   , E_D     ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_stwu"      , 0x18000600, 0x18000600 | E_MASK_D8  , E_D8    ,   OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
	{ "e_subfic"    , 0x1800B000, 0x1800B000 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_subfic."   , 0x1800B800, 0x1800B800 | E_MASK_SCI8, E_SCI8  ,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_xori"      , 0x1800E000, 0x1800E000 | E_MASK_SCI8, E_SCI8I ,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
	{ "e_xori."     , 0x1800E800, 0x1800E800 | E_MASK_SCI8, E_SCI8I ,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},




  { "e_add16i"   , 0x1C000000, 0x1F000000 | E_MASK_D   , E_D    ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_add2i."   , 0x70008800, 0x70008800 | E_MASK_I16A, E_I16A ,   OP_TYPE_ADD, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_add2is"   , 0x70009000, 0x70009000 | E_MASK_I16A, E_I16A ,   OP_TYPE_ADD, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_addi"     , 0x18008000, 0x18008000 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_addi."    , 0x18008800, 0x18008800 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_addic"    , 0x18009000, 0x18009000 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_addic."   , 0x18009800, 0x18009800 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_ADD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_and2i."   , 0x7000C800, 0x7000C800 | E_MASK_I16L, E_I16L ,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_and2is."  , 0x7000E800, 0x7000E800 | E_MASK_I16L, E_I16LS,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_andi"     , 0x1800C000, 0x1800C000 | E_MASK_SCI8, E_SCI8I,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_andi."    , 0x1800C800, 0x1800C800 | E_MASK_SCI8, E_SCI8I,   OP_TYPE_AND, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  // has cr0-cr3 
  { "e_bge"      , 0x7A000000, 0x7A000000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_GE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_ble"      , 0x7A000000, 0x7A010000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_LE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bne"      , 0x7A000000, 0x7A020000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_NE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bns"      , 0x7A000000, 0x7A030000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_VC, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_blt"      , 0x7A000000, 0x7A100000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_LT, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  /* 0x7a, 0x12, 0x01, 0x0a */
  { "e_bgt"      , 0x7A000000, 0x7A110000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_GT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_beq"      , 0x7A000000, 0x7A120000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_EQ, {TYPE_CR, TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bso"      , 0x7A000000, 0x7A130000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  // TODO this may not be correct
  { "e_bc"       , 0x7A000000, 0x7A140000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bgel"     , 0x7A000001, 0x7A000001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_GE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_blel"     , 0x7A000001, 0x7A010001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_LE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bnel"     , 0x7A000001, 0x7A020001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_NE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bnsl"     , 0x7A000001, 0x7A030001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_VC, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bltl"     , 0x7A000001, 0x7A110001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_LT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bgtl"     , 0x7A000001, 0x7A120001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_GT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_beql"     , 0x7A000001, 0x7A130001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_EQ, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bsol"     , 0x7A000001, 0x7A140001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bcl"      , 0x7A000001, 0x7A140001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  // has cr0-cr3  
  { "e_bgectr"   , 0x7A000000, 0x7A200000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_GE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_blectr"   , 0x7A000000, 0x7A210000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_LE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bnectr"   , 0x7A000000, 0x7A220000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_NE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bnsctr"   , 0x7A000000, 0x7A230000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_VC, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bltctr"   , 0x7A000000, 0x7A310000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_LT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bgtctr"   , 0x7A000000, 0x7A320000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_GT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_beqctr"   , 0x7A000000, 0x7A330000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_EQ, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bsoctr"   , 0x7A000000, 0x7A340000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bcctr"    , 0x7A000000, 0x7A340000 | E_MASK_BD15, E_BD15 ,  OP_TYPE_CJMP, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bgectrl"  , 0x7A000001, 0x7A200001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_GE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_blectrl"  , 0x7A000001, 0x7A210001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_LE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bnectrl"  , 0x7A000001, 0x7A220001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_NE, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bnsctrl"  , 0x7A000001, 0x7A230001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_VC, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bltctrl"  , 0x7A000001, 0x7A310001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_LT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bgtctrl"  , 0x7A000001, 0x7A320001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_GT, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_beqctrl"  , 0x7A000001, 0x7A330001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_EQ, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bsoctrl"  , 0x7A000001, 0x7A340001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_bcctrl"   , 0x7A000001, 0x7A340001 | E_MASK_BD15, E_BD15 , OP_TYPE_CCALL, COND_VS, {TYPE_CR, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_b"        , 0x78000000, 0x78000000 | E_MASK_BD24, E_BD24 ,   OP_TYPE_JMP, COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  // 78000313
  // The 24-bit BD24 field is concatenated on the right with 0b0, sign-extended, and then
  // added to the address of the branch instruction.
  { "e_bl"       , 0x78000001, 0x78000001 | E_MASK_BD24, E_BD24 ,  OP_TYPE_CALL, COND_AL, {TYPE_JMP, TYPE_NONE, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_cmp16i"   , 0x70009800, 0x70009800 | E_MASK_IA16, E_IA16 ,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_cmph16i"  , 0x7000B000, 0x7000B000 | E_MASK_IA16, E_IA16 ,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_cmph"     , 0x7C00001C, 0x7C00001D | E_MASK_X   , E_XCR  ,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_cmphl16i" , 0x7000B800, 0x7000B800 | E_MASK_IA16, E_IA16U,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_cmphl"    , 0x7C00005C, 0x7C00005D | E_MASK_X   , E_XCR  ,   OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_cmpli"    , 0x1880A800, 0x1880A800 | E_MASK_SCI8, E_SCI8CR,  OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_cmpi"     , 0x1800A800, 0x1800A800 | E_MASK_SCI8, E_SCI8CR,  OP_TYPE_CMP, COND_AL, {TYPE_CR, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_cmpl16i"  , 0x7000A800, 0x7000A800 | E_MASK_IA16, E_IA16U,   OP_TYPE_CMP, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_crand"    , 0x7C000202, 0x7C000202 | E_MASK_XL  , E_XL   ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_crandc"   , 0x7C000102, 0x7C000102 | E_MASK_XL  , E_XL   ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_creqv"    , 0x7C000242, 0x7C000242 | E_MASK_XL  , E_XL   ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_crnand"   , 0x7C0001C2, 0x7C0001C2 | E_MASK_XL  , E_XL   ,   OP_TYPE_AND, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_crnor"    , 0x7C000042, 0x7C000042 | E_MASK_XL  , E_XL   ,   OP_TYPE_NOR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_cror"     , 0x7C000382, 0x7C000382 | E_MASK_XL  , E_XL   ,    OP_TYPE_OR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_crorc"    , 0x7C000342, 0x7C000342 | E_MASK_XL  , E_XL   ,    OP_TYPE_OR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_crxor"    , 0x7C000182, 0x7C000182 | E_MASK_XL  , E_XL   ,   OP_TYPE_XOR, COND_AL, {TYPE_CR, TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE}},
  { "e_lbz"      , 0x30000000, 0x30000000 | E_MASK_D   , E_D    ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_lbzu"     , 0x18000000, 0x18000000 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_lha"      , 0x38000000, 0x38000000 | E_MASK_D   , E_D    ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_lhau"     , 0x18000300, 0x18000300 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  // 5b0b0000
  { "e_lhz"      , 0x58000000, 0x58000000 | E_MASK_D   , E_D    ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_lhzu"     , 0x18000100, 0x18000100 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_li"       , 0x70000000, 0x70000000 | E_MASK_LI20, E_LI20 ,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},

  { "e_lis"      , 0x7000E000, 0x7000E000 | E_MASK_I16L, E_I16LS,   OP_TYPE_MOV, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_lmw"      , 0x18000800, 0x18000800 | E_MASK_D8  , E_D8   ,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_lwz"      , 0x50000000, 0x53000000 | E_MASK_D   , E_D    ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_lwzu"     , 0x18000200, 0x18000200 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_mcrf"     , 0x7C000020, 0x7C000020 | E_MASK_XL  , E_XLSP ,   OP_TYPE_MOV, COND_AL, {TYPE_CR, TYPE_CR, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
  { "e_mull2i"   , 0x7000A000, 0x7000A000 | E_MASK_I16A, E_I16A ,   OP_TYPE_MUL, COND_AL, {TYPE_IMM, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_mulli"    , 0x1800A000, 0x1800A000 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_MUL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_or2i"     , 0x7000C000, 0x7000C000 | E_MASK_I16L, E_I16L ,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_or2is"    , 0x7000D000, 0x7000D000 | E_MASK_I16L, E_I16LS,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_ori"      , 0x1800D000, 0x1800D000 | E_MASK_SCI8, E_SCI8I ,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_ori."     , 0x1800D800, 0x1800D800 | E_MASK_SCI8, E_SCI8I ,    OP_TYPE_OR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_rlw"      , 0x7C000230, 0x7C000230 | E_MASK_X   , E_XRA  ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_rlw."     , 0x7C000231, 0x7C000231 | E_MASK_X   , E_XRA  ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_rlwi"     , 0x7C000270, 0x7C000270 | E_MASK_X   , E_XRA  ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_rlwi."    , 0x7C000271, 0x7C000271 | E_MASK_X   , E_XRA  ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_rlwimi"   , 0x74000000, 0x74000000 | E_MASK_M   , E_M    ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_rlwinm"   , 0x74000001, 0x74000001 | E_MASK_M   , E_M    ,   OP_TYPE_ROR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_slwi"     , 0x7C000070, 0x7C000070 | E_MASK_X   , E_XRA  ,   OP_TYPE_SHL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_slwi."    , 0x7C000071, 0x7C000071 | E_MASK_X   , E_XRA  ,   OP_TYPE_SHL, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_srwi"     , 0x7C000470, 0x7C000470 | E_MASK_X   , E_XRA  ,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_srwi."    , 0x7C000471, 0x7C000471 | E_MASK_X   , E_XRA  ,   OP_TYPE_SHR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_NONE, TYPE_NONE}},
  { "e_stb"      , 0x34000000, 0x34000000 | E_MASK_D   , E_D    , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_stbu"     , 0x18000400, 0x18000400 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_sth"      , 0x5C000000, 0x5C000000 | E_MASK_D   , E_D    , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_sthu"     , 0x18000500, 0x18000500 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_stmw"     , 0x18000900, 0x18000900 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_stw"      , 0x54000000, 0x56000000 | E_MASK_D   , E_D    , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},
  { "e_stwu"     , 0x18000600, 0x18000600 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE}},


   /* 1d53a:	18 21 11 00 	e_stmvsprw 0(r1) */
   /* 1d53e:	18 81 11 10 	e_stmvsrrw 16(r1) */
   /* 1d5a4:	18 81 10 10 	e_ldmvsrrw 16(r1) */
   /* 1d5a8:	18 21 10 00 	e_ldmvsprw 0(r1) */


/* e_ldmvgprw 6  (0b0001_1000_000 RA 0b0001_0000 D8 */
/* e_stmvgprw 6  (0b0001_1000_000 RA 0b0001_0001 D8 */
/* e_ldmvsprw 6  (0b0001_1000_001 RA 0b0001_0000 D8 */
/* e_stmvsprw 6  (0b0001_1000_001 RA 0b0001_0001 D8 */
/* e_ldmvsrrw 6  (0b0001_1000_100 RA 0b0001_0000 D8 */
/* e_stmvsrrw 6  (0b0001_1000_100 RA 0b0001_0001 D8 */
/* e_ldmvcsrrw 6 (0b0001_1000_101 RA 0b0001_0000 D8 */
/* e_stmvcsrrw 6 (0b0001_1000_101 RA 0b0001_0001 D8 */
/* e_ldmvdsrrw 6 (0b0001_1000_110 RA 0b0001_0000 D8 */
/* e_stmvdsrrw 6 (0b0001_1000_110 RA 0b0001_0001 D8 */

// TODO
	{ "e_ldmvcsrrw" , 0x18A01000, 0x18A01000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_ldmvdsrrw" , 0x18C01000, 0x18C01000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_ldmvgprw"  , 0x18001000, 0x18001000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_ldmvsprw"  , 0x18201000, 0x18201000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_ldmvsrrw"  , 0x18801000, 0x18801000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmvcsrrw"  , 0x18A01000, 0x18A01000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmvdsrrw"  , 0x18C01000, 0x18C01000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmvgprw"   , 0x18001000, 0x18001000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmvmcsrrw" , 0x18E01000, 0x18E01000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmvsprw"   , 0x18201000, 0x18201000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_lmvsrrw"   , 0x18801000, 0x18801000 | E_MASK_D8  , E_D8_N  , OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_stmvcsrrw" , 0x18A01100, 0x18A01100 | E_MASK_D8  , E_D8_N  , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_stmvdsrrw" , 0x18C01100, 0x18C01100 | E_MASK_D8  , E_D8_N  , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_stmvgprw"  , 0x18001100, 0x18001100 | E_MASK_D8  , E_D8_N  , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_stmvmcsrrw", 0x18E01100, 0x18E01000 | E_MASK_D8  , E_D8_N  , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_stmvsprw"  , 0x18201100, 0x18201100 | E_MASK_D8  , E_D8_N  , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},
	{ "e_stmvsrrw"  , 0x18801100, 0x18801100 | E_MASK_D8  , E_D8_N  , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_NONE, TYPE_NONE, TYPE_NONE}},



  { "e_ldmvgprw" , 0x18001000, 0x18001000 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_stmvgprw" , 0x18001100, 0x18001100 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_ldmvsprw" , 0x18201000, 0x18201000 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_stmvsprw" , 0x18201100, 0x18201100 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_ldmvsrrw" , 0x18801000, 0x18801000 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_stmvsrrw" , 0x18801100, 0x18801100 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_ldmvcsrrw", 0x18a01000, 0x18a01000 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_stmvcsrrw", 0x18a01100, 0x18a01100 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_ldmvdsrrw", 0x18c01000, 0x18c01000 | E_MASK_D8  , E_D8   ,  OP_TYPE_LOAD, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},
  { "e_stmvcsrrw", 0x18c01100, 0x18c01100 | E_MASK_D8  , E_D8   , OP_TYPE_STORE, COND_AL, {TYPE_REG, TYPE_MEM, TYPE_REG, TYPE_NONE, TYPE_NONE}},


  { "e_subfic"   , 0x1800B000, 0x1800B000 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_subfic."  , 0x1800B800, 0x1800B800 | E_MASK_SCI8, E_SCI8 ,   OP_TYPE_SUB, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_xori"     , 0x1800E000, 0x1800E000 | E_MASK_SCI8, E_SCI8I,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
  { "e_xori."    , 0x1800E800, 0x1800E800 | E_MASK_SCI8, E_SCI8I,   OP_TYPE_XOR, COND_AL, {TYPE_REG, TYPE_REG, TYPE_IMM, TYPE_IMM, TYPE_IMM}},
};

const se_vle_t se_ops[] = {
//  { "name"      , op    , mask  , n,   op_type           , {{field ,shr,shl,  +, i, TYPE_REG}, ...}
  { "se_illegal", 0x0000, 0x0000, 0,   OP_TYPE_ILL, COND_NV, {{0}, {0}, {0}, {0}, {0}}},
  { "se_isync"  , 0x0001, 0x0001, 0,  OP_TYPE_SYNC, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_sc"     , 0x0002, 0x0002, 0,   OP_TYPE_SWI, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_blr"    , 0x0004, 0x0004, 0,   OP_TYPE_RET, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_blrl"   , 0x0005, 0x0005, 0,   OP_TYPE_RET, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_bctr"   , 0x0006, 0x0006, 0,  OP_TYPE_RJMP, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_bctrl"  , 0x0007, 0x0007, 0, OP_TYPE_RCALL, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_rfi"    , 0x0008, 0x0008, 0,  OP_TYPE_TRAP, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_rfci"   , 0x0009, 0x0009, 0,  OP_TYPE_TRAP, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_rfdi"   , 0x000A, 0x000A, 0,  OP_TYPE_TRAP, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_rfmci"  , 0x000B, 0x000B, 0,  OP_TYPE_TRAP, COND_AL, {{0}, {0}, {0}, {0}, {0}}},
  { "se_not"    , 0x0020, 0x002F, 1,   OP_TYPE_NOT, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_neg"    , 0x0030, 0x003F, 1,   OP_TYPE_NOT, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_mflr"   , 0x0080, 0x008F, 1,   OP_TYPE_MOV, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_mtlr"   , 0x0090, 0x009F, 1,   OP_TYPE_MOV, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_mfctr"  , 0x00A0, 0x00AF, 1,   OP_TYPE_MOV, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_mtctr"  , 0x00B0, 0x00BF, 1,   OP_TYPE_MOV, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_extzb"  , 0x00C0, 0x00CF, 1,    OP_TYPE_OR, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_extsb"  , 0x00D0, 0x00DF, 1,    OP_TYPE_OR, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_extzh"  , 0x00E0, 0x00EF, 1,    OP_TYPE_OR, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_extsh"  , 0x00F0, 0x00FF, 1,    OP_TYPE_OR, COND_AL, {{0x000F,  0,  0,  0, 0, TYPE_REG}, {0}, {0}, {0}, {0}}},
  { "se_mr"     , 0x0100, 0x01FF, 2,   OP_TYPE_MOV, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_mtar"   , 0x0200, 0x02FF, 2,   OP_TYPE_MOV, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  8,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_mfar"   , 0x0300, 0x03FF, 2,   OP_TYPE_MOV, COND_AL, {{0x00F0,  4,  0,  8, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_add"    , 0x0400, 0x04FF, 2,   OP_TYPE_ADD, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_mullw"  , 0x0500, 0x05FF, 2,   OP_TYPE_MUL, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_sub"    , 0x0600, 0x06FF, 2,   OP_TYPE_SUB, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_subf"   , 0x0700, 0x07FF, 2,   OP_TYPE_SUB, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmp"    , 0x0C00, 0x0CFF, 2,   OP_TYPE_CMP, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmpl"   , 0x0D00, 0x0DFF, 2,   OP_TYPE_CMP, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmph"   , 0x0E00, 0x0EFF, 2,   OP_TYPE_CMP, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmphl"  , 0x0F00, 0x0FFF, 2,   OP_TYPE_CMP, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_addi"   , 0x2000, 0x21FF, 2,   OP_TYPE_ADD, COND_AL, {{0x01F0,  4,  0,  1, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_and"    , 0x4600, 0x46FF, 2,   OP_TYPE_AND, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_and."   , 0x4700, 0x47FF, 2,   OP_TYPE_AND, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_andi"   , 0x2E00, 0x2FFF, 2,   OP_TYPE_AND, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_andc"   , 0x4500, 0x45FF, 2,   OP_TYPE_AND, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_b"      , 0xE800, 0xE8FF, 1,   OP_TYPE_JMP, COND_AL, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_bl"     , 0xE900, 0xE9FF, 1,  OP_TYPE_CALL, COND_AL, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  // cr0
  // e2 e5
  { "se_bge"    , 0xE000, 0xE0FF, 1,  OP_TYPE_CJMP, COND_GE, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_ble"    , 0xE000, 0xE1FF, 1,  OP_TYPE_CJMP, COND_LE, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_bne"    , 0xE000, 0xE2FF, 1,  OP_TYPE_CJMP, COND_NE, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_bns"    , 0xE000, 0xE3FF, 1,  OP_TYPE_CJMP, COND_VC, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_blt"    , 0xE000, 0xE4FF, 1,  OP_TYPE_CJMP, COND_LT, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_bgt"    , 0xE000, 0xE5FF, 1,  OP_TYPE_CJMP, COND_GT, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_beq"    , 0xE000, 0xE6FF, 1,  OP_TYPE_CJMP, COND_EQ, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_bso"    , 0xE000, 0xE7FF, 1,  OP_TYPE_CJMP, COND_VS, {{0x00FF,  0,  1,  0, 0, TYPE_JMP}, {0}, {0}, {0}, {0}}},
  { "se_bc"     , 0xE000, 0xE7FF, 2,  OP_TYPE_CJMP, COND_VS, {{0x0700,  8,  0, 32, 0, TYPE_JMP}, {0x00FF,  0,  1,  0,  1, TYPE_IMM}, {0}, {0}, {0}}},
  { "se_bclri"  , 0x6000, 0x61FF, 2,    OP_TYPE_OR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_bgeni"  , 0x6200, 0x63FF, 2,    OP_TYPE_OR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_bmaski" , 0x2C00, 0x2DFF, 2,    OP_TYPE_OR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_bseti"  , 0x6400, 0x65FF, 2,    OP_TYPE_OR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_btsti"  , 0x6600, 0x67FF, 2,    OP_TYPE_OR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmpi"   , 0x2A00, 0x2BFF, 2,   OP_TYPE_CMP, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmpl"   , 0x0D00, 0x0DFF, 2,   OP_TYPE_CMP, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_cmpli"  , 0x2200, 0x23FF, 2,   OP_TYPE_CMP, COND_AL, {{0x01F0,  4,  0,  1, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_lbz"    , 0x8000, 0x8FFF, 3,  OP_TYPE_LOAD, COND_AL, {{0x0F00,  8,  0,  0, 2, TYPE_MEM}, {0x00F0,  4,  0,  0,  0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}}},
  { "se_lhz"    , 0xA000, 0xAFFF, 3,  OP_TYPE_LOAD, COND_AL, {{0x0F00,  7,  0,  0, 2, TYPE_MEM}, {0x00F0,  4,  0,  0,  0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}}},
  { "se_li"     , 0x4800, 0x4FFF, 2,   OP_TYPE_MOV, COND_AL, {{0x07F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_lwz"    , 0xC000, 0xCFFF, 3,  OP_TYPE_LOAD, COND_AL, {{0x0F00,  6,  0,  0, 2, TYPE_MEM}, {0x00F0,  4,  0,  0,  0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}}},
  { "se_or"     , 0x4400, 0x44FF, 2,    OP_TYPE_OR, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_slw"    , 0x4200, 0x42FF, 2,   OP_TYPE_SHL, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_slwi"   , 0x6C00, 0x6DFF, 2,   OP_TYPE_SHL, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_sraw"   , 0x4100, 0x41FF, 2,   OP_TYPE_SHR, COND_AL, {{0x00F0,  4,  0,  0, 1, TYPE_REG}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_srawi"  , 0x6A00, 0x6BFF, 2,   OP_TYPE_SHR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_srw"    , 0x4000, 0x40FF, 2,   OP_TYPE_SHR, COND_AL, {{0x00F0,  4,  0,  0, 0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}, {0}}},
  { "se_srwi"   , 0x6800, 0x69FF, 2,   OP_TYPE_SHR, COND_AL, {{0x01F0,  4,  0,  0, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_stb"    , 0x9000, 0x9FFF, 3, OP_TYPE_STORE, COND_AL, {{0x0F00,  8,  0,  0, 2, TYPE_MEM}, {0x00F0,  4,  0,  0,  0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}}},
  { "se_sth"    , 0xB000, 0xBFFF, 3, OP_TYPE_STORE, COND_AL, {{0x0F00,  7,  0,  0, 2, TYPE_MEM}, {0x00F0,  4,  0,  0,  0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}}},
  { "se_stw"    , 0xD000, 0xDFFF, 3, OP_TYPE_STORE, COND_AL, {{0x0F00,  6,  0,  0, 2, TYPE_MEM}, {0x00F0,  4,  0,  0,  0, TYPE_REG}, {0x000F,  0,  0,  0,  1, TYPE_REG}, {0}, {0}}},
  { "se_subi"   , 0x2400, 0x25FF, 2,   OP_TYPE_SUB, COND_AL, {{0x01F0,  4,  0,  1, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
  { "se_subi."  , 0x2600, 0x27FF, 2,   OP_TYPE_SUB, COND_AL, {{0x01F0,  4,  0,  1, 1, TYPE_IMM}, {0x000F,  0,  0,  0,  0, TYPE_REG}, {0}, {0}, {0}}},
};


static void set_e_fields(vle_t * v, const e_vle_t* p, ut32 data, ut32 addr) {
	if (!v) {
		return;
	}
	switch (p->type) {
		case E_X:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case E_XRA:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x3E00000) >> 21;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case E_XL:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case E_D:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = data & 0xFFFF;
			if (v->fields[2].value & 0x8000) {
				v->fields[2].value = 0xFFFF0000 | v->fields[2].value;
			}
			v->fields[2].type = p->types[2];
		}
			break;
		case E_D8:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = data & 0xFF;
			if (v->fields[2].value & 0x80) {
				v->fields[2].value = 0xFFFFFF00 | v->fields[2].value;
			}
			v->fields[2].type = p->types[2];
		}
			break;
		case E_D8_N:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[0];
			v->fields[1].value = data & 0xFF;
			/*if (v->fields[1].value & 0x80) {
				v->fields[1].value = 0xFFFFFF00 | v->fields[1].value;
			}*/
			v->fields[1].type = p->types[1];
		}
			break;
		case E_IA16U:
		{
			v->n = 2;
			v->fields[1].value = (data & 0x3E00000) >> 10;
			v->fields[1].type = p->types[0];
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[1];
			v->fields[1].value |= (data & 0x7FF);
		}
			break;
		case E_IA16:
		case E_I16A:
		{
			v->n = 2;
			v->fields[1].value = (data & 0x3E00000) >> 10;
			v->fields[1].type = p->types[0];
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[1];
			v->fields[1].value |= (data & 0x7FF);
			if (v->fields[1].value & 0x8000) {
				v->fields[1].value = 0xFFFF0000 | v->fields[1].value;
			}
		}
			break;
		case E_SCI8:
		case E_SCI8CR:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			if (p->type == E_SCI8CR) {
				v->fields[0].value &= 0x3;
			}
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			ut32 ui8 = data & 0xFF;
			ut32 scl = (data & 0x300) >> 8;
			ut32 f = data & 0x400;
			switch (scl) {
				case 0:
					v->fields[2].value = ui8 | (f ? 0xffffff00 : 0);
					break;
				case 1:
					v->fields[2].value = (ui8 << 8) | (f ? 0xffff00ff : 0);
					break;
				case 2:
					v->fields[2].value = (ui8 << 16) | (f ? 0xff00ffff : 0);
					break;
				default:
					v->fields[2].value = (ui8 << 24) | (f ? 0x00ffffff : 0);
					break;
			}
			v->fields[2].type = p->types[2];
		}
			break;
		case E_SCI8I:
		{
			v->n = 3;
			v->fields[1].value = (data & 0x3E00000) >> 21;
			v->fields[1].type = p->types[0];
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[1];
			ut32 ui8 = data & 0xFF;
			ut32 scl = (data & 0x300) >> 8;
			ut32 f = data & 0x400;
			switch (scl) {
				case 0:
					v->fields[2].value = ui8 | (f ? 0xffffff00 : 0);
					break;
				case 1:
					v->fields[2].value = (ui8 << 8) | (f ? 0xffff00ff : 0);
					break;
				case 2:
					v->fields[2].value = (ui8 << 16) | (f ? 0xff00ffff : 0);
					break;
				default:
					v->fields[2].value = (ui8 << 24) | (f ? 0x00ffffff : 0);
					break;
			}
			v->fields[2].type = p->types[2];
		}
			break;
		case E_I16L:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 5;
			v->fields[1].value |= (data & 0x7FF);
			v->fields[1].type = p->types[1];
		}
			break;
		case E_I16LS:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 5;
			v->fields[1].value |= (data & 0x7FF);
			v->fields[1].type = p->types[1];
		}
			break;
		case E_BD24:
		{
			v->n = 1;
			v->fields[0].value = data & 0x3FFFFFE;
			if (v->fields[0].value & 0x1000000) {
				v->fields[0].value |= 0xFE000000;
			}
			v->fields[0].type = p->types[0];
		}
			break;
		case E_BD15:
		{
			v->n = 2;
			v->fields[0].value = (data & 0xC0000) >> 18;
			v->fields[0].type = p->types[0];
			v->fields[1].value = data & 0xFFFE;
			if (v->fields[1].value & 0x8000) {
				v->fields[1].value |= 0xFFFF0000;
			}
			v->fields[1].type = p->types[1];
		}
			break;
		case E_BD15b: // TODO check
		{
			v->n = 3;
			v->fields[0].value = (data & 0x300000) >> 20;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0xF0000) >> 16;
			v->fields[1].type = p->types[0];
			v->fields[2].value = data & 0xFFFE;
			if (v->fields[2].value & 0x8000) {
				v->fields[2].value |= 0xFFFF0000;
			}
			v->fields[2].type = p->types[2];
		}
			break;
		case E_BD15c: // TODO check
		{
			v->n = 1;
			v->fields[0].value = data & 0xFFFE;
			if (v->fields[0].value & 0x8000) {
				v->fields[0].value |= 0xFFFF0000;
			}
			v->fields[0].type = p->types[0];
		}
			break;
		case E_LI20:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x03E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = ((data & 0x001F0000) >> 5);
			v->fields[1].value |= ((data & 0x7800) << 5);
			v->fields[1].value |= (data & 0x7FF);
			v->fields[1].type = p->types[1];
			if (v->fields[1].value & 0x80000) {
				int m = 1U << (20 - 1);
                v->fields[1].value = (v->fields[1].value ^ m) - m;
				//v->fields[1].value = 0xFFF00000 | v->fields[1].value;
			}
		}
			break;
		case E_M:
		{
			v->n = 5;
			v->fields[1].value = (data & 0x3E00000) >> 21;
			v->fields[1].type = p->types[1];
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[0];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
			v->fields[3].value = (data & 0x7C0) >> 6;
			v->fields[3].type = p->types[3];
			v->fields[4].value = (data & 0x3E) >> 1;
			v->fields[4].type = p->types[4];
		}
			break;
		case E_XCR:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3000000) >> 24;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case E_XLSP:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3800000) >> 23;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1C0000) >> 18;
			v->fields[1].type = p->types[1];
		}
			break;
		case E_NONE:
		default:
			v->n = 0;
			break;
	}
	ut16 i;
	for (i = 0; i < v->n; ++i) {
		if (v->fields[i].type == TYPE_JMP) {
			v->fields[i].value += addr;
		}
	}
}

static void set_ppc_fields(vle_t * v, const ppc_t* p, ut32 data, ut32 addr) {
	if (!v) {
		return;
	}
	switch (p->type) {
		case F_X:
		case F_XO:
		case F_EVX:
		{
			v->n = 0;
			if (p->types[0] != TYPE_NONE) {
				v->fields[0].value = (data & 0x3E00000) >> 21;
				v->fields[0].type = p->types[0];
				v->n++;
			}
			if (p->types[1] != TYPE_NONE) {
				v->fields[1].value = (data & 0x1F0000) >> 16;
				v->fields[1].type = p->types[1];
				v->n++;
			}
			if (p->types[2] != TYPE_NONE) {
				v->fields[2].value = (data & 0xF800) >> 11;
				v->fields[2].type = p->types[2];
				v->n++;
			}
		}
			break;
		case F_X_SH:
		{
			v->n = 0;
			if (p->types[0] != TYPE_NONE) {
				v->fields[0].value = (data & 0x3E00000) >> 21;
				v->fields[0].type = p->types[0];
				v->n++;
			}
			if (p->types[1] != TYPE_NONE) {
				v->fields[1].value = (data & 0x1F0000) >> 16;
				v->fields[1].type = p->types[1];
				v->n++;
			}
			if (p->types[2] != TYPE_NONE) {
				v->fields[2].value = (data & 0xF800) >> 11;
				v->fields[2].value = v->fields[2].value << 3;
				v->fields[2].type = p->types[2];
				v->n++;
			}
		}
			break;
		/*case F_FRA:
		{
			v->n = 1;
			v->fields[0].value = (data & 0x8000) >> 15;
			v->fields[0].type = p->types[0];
		}
			break;*/
		case F_X_IMM:
		{
			v->n = 0;
			if (p->types[0] != TYPE_NONE) {
				v->fields[0].value = (data & 0x3E00000) >> 21;
				v->fields[0].type = p->types[0];
				v->n++;
			}
			if (p->types[2] != TYPE_NONE) {
				v->fields[2].value = (data & 0x1F0000) >> 16;
				v->fields[2].type = p->types[1];
				v->n++;
			}
			if (p->types[1] != TYPE_NONE) {
				v->fields[1].value = (data & 0xF800) >> 11;
				v->fields[1].type = p->types[2];
				v->n++;
			}
		}
			break;
		case F_XRA:
		{
			v->n = 3;
			v->fields[1].value = (data & 0x3E00000) >> 21;
			v->fields[1].type = p->types[0];
			v->fields[0].value = (data & 0x1F0000) >> 16;
			v->fields[0].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case F_CMP:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x3800000) >> 23;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case F_DCBF:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x0E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case F_DCBL:
		{
			v->n = 3;
			v->fields[0].value = (data & 0x1E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
		}
			break;
		case F_DCI:
		{
			v->n = 1;
			v->fields[0].value = (data & 0xE00000) >> 21;
			v->fields[0].type = p->types[0];
		}
			break;
		case F_EXT:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
		}
			break;
		case F_A:
		{
			v->n = 4;
			v->fields[0].value = (data & 0x1E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
			v->fields[3].value = (data & 0x7C0) >> 6;
			v->fields[3].type = p->types[3];
		}
			break;
		case F_AP:
		{
			v->n = 4;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1F0000) >> 16;
			v->fields[1].type = p->types[1];
			v->fields[2].value = (data & 0xF800) >> 11;
			v->fields[2].type = p->types[2];
			v->fields[3].value = (data & 0x7C0) >> 6;
			v->fields[3].type = p->types[3];
		}
			break;
		case F_XFX:
		{
			v->n = 1;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
		}
			break;
		case F_CFH:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x3E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0xF800) >> 11;
			v->fields[1].type = p->types[1];
		}
			break;
		case F_XER:
		{
			v->n = 1;
			v->fields[0].value = (data & 0x3800000) >> 23;
			v->fields[0].type = p->types[0];
		}
			break;
		case F_MFPR:
		{
			v->n = 2;
			v->fields[0].value = (data & 0x1E00000) >> 21;
			v->fields[0].type = p->types[0];
			v->fields[1].value = (data & 0x1FF800) >> 11;
			v->fields[1].type = p->types[1];
			break;
		}
		case F_MTPR:
		{
			v->n = 2;
			//inverted
			v->fields[1].value = (data & 0x1E00000) >> 21;
			v->fields[1].type = p->types[1];
			v->fields[0].value = (data & 0x1FF800) >> 11;
			v->fields[0].type = p->types[0];
		}
			break;
        case F_X_2:
        {
            v->n = 0;
            if (p->types[1] != TYPE_NONE) {
                v->fields[v->n].value = (data & 0x1F0000) >> 16;
                v->fields[v->n].type = p->types[1];
                v->n++;
            }
            if (p->types[0] != TYPE_NONE) {
                v->fields[v->n].value = (data & 0x3E00000) >> 21;
                v->fields[v->n].type = p->types[0];
                v->n++;
            }
            if (p->types[2] != TYPE_NONE) {
                v->fields[v->n].value = (data & 0xF800) >> 11;
                v->fields[v->n].type = p->types[2];
                v->n++;
            }
        }
            break;
		case E_NONE:
		default:
			v->n = 0;
			break;
	}
	ut16 i;
	for (i = 0; i < v->n; ++i) {
		if (v->fields[i].type == TYPE_JMP) {
			v->fields[i].value += addr;
		}
	}
}

static vle_t *find_ppc(const ut8* buffer, ut32 addr) {
	ut32 i;
	ut32 data = (buffer[0] << 24) | (buffer[1] << 16) | (buffer[2] << 8) | buffer[3];
	const ppc_t* p = NULL;
	const ut32 size = sizeof (ppc_ops) / sizeof (ppc_t);
	for (i = 0; i < size; ++i) {
		p = &ppc_ops[i];
		if ((p->op & data) == p->op && (p->mask & data) == data) {
			vle_t* ret = (vle_t*) calloc(1, sizeof(vle_t));
			ret->name = p->name;
			ret->size = 4;
			ret->n = 0;
            ret->op_type = p->op_type;
			set_ppc_fields (ret, p, data, addr);
			return ret;
		}
	}
	return NULL;
}

static vle_t *find_e(const ut8* buffer, ut32 addr) {
	ut32 i;
	ut32 data = (buffer[0] << 24) | (buffer[1] << 16) | (buffer[2] << 8) | buffer[3];
	const e_vle_t* p = NULL;
	const ut32 size = sizeof (e_ops) / sizeof (e_vle_t);
	for (i = 0; i < size; ++i) {
		p = &e_ops[i];
		if ((p->op & data) == p->op && (p->mask & data) == data) {
			vle_t* ret = (vle_t*) calloc(1, sizeof(vle_t));
			ret->name = p->name;
			ret->size = 4;
			ret->n = 0;
            ret->op_type = p->op_type;
            ret->cond = p->cond;
            ret->cond = p->cond;
			set_e_fields (ret, p, data, addr);
			return ret;
		}
	}
	return NULL;
}

static vle_t *find_se(const ut8* buffer, ut32 addr) {
	ut32 i, j, k;
	ut16 data = (buffer[0] << 8) | buffer[1];
	const se_vle_t* p = NULL;
	const ut32 size = sizeof (se_ops) / sizeof (se_vle_t);
	for (i = 0; i < size; ++i) {
		p = &se_ops[i];
		if ((p->op & data) == p->op && (p->mask & data) == data) {
			vle_t* ret = (vle_t*) calloc(1, sizeof(vle_t));
			ret->name = p->name;
			ret->size = 2;
            ret->op_type = p->op_type;
            ret->cond = p->cond;
			for (j = 0; j < p->n; ++j) {
				for (k = 0; k < p->n; ++k) {
					if (p->fields[k].idx == j) {
						ret->fields[j].value = data & p->fields[k].mask;
						ret->fields[j].value >>= p->fields[k].shr;
						ret->fields[j].value <<= p->fields[k].shl;
						ret->fields[j].value += p->fields[k].add;
						ret->fields[j].value &= 0xFFFF;
						if (p->fields[k].type == TYPE_REG && p->fields[k].add == 8) {
							//ret->fields[j].value = (ret->fields[j].value + 0x8);
						} else if (p->fields[k].type == TYPE_REG && ret->fields[j].value & 0x8) {
							ret->fields[j].value = (ret->fields[j].value & 0x7) + 24;
						} 
						
						if (p->fields[k].type == TYPE_JMP) {
							if (ret->fields[j].value & 0x0100) {
								ret->fields[j].value = 0xFFFFFE00 | ret->fields[j].value;
							}
							ret->fields[j].value += addr;
						}
						ret->fields[j].type = p->fields[k].type;
						break;
					}
				}
			}
			ret->n = p->n;
			return ret;
		}
	}
	return NULL;
}

/*
int vle_init(vle_handle* handle, const uint8_t* buffer, const uint32_t size) {
  if (!handle || !buffer || size < 2) {
    return 1;
  }
  handle->pos = buffer;
  handle->end = buffer + size;
  handle->inc = 0;
  return 0;
}

int vle_next(vle_handle* handle, vle_t* ret) {
  vle_t *op = NULL;
  if (!handle || handle->pos + handle->inc >= handle->end) {
    return 0;
  }
  handle->pos += handle->inc;
  // ppc subset, e(32 bits) and then se(16 bits)
  memset(ret, 0, sizeof(vle_t));

  if (handle->pos + 4 <= handle->end) {
    op = find_ppc (handle->pos, ret);
  }
  if (!op && handle->pos + 4 <= handle->end) {
    op = find_e (handle->pos, ret);
  }
  if (!op && handle->pos + 2 <= handle->end) {
    op = find_se (handle->pos, ret);
  }

  handle->inc = op ? op->size : 0;
  return 1;
}*/

vle_t* vle_decode_one(const ut8* buffer, const ut32 size, ut32 current_address) {
	vle_t *op = NULL;
	if (size < 2) {
		return NULL;
	}
	if (size > 3) {
		op = find_ppc (buffer, current_address);
	}
	if (!op && size > 3) {
		op = find_e (buffer, current_address);
	}
	if (!op && size > 1) {
		op = find_se (buffer, current_address);
	}
	return op;
}


void vle_free(vle_t* instr) {
  free (instr);
}

void vle_snprint(char* str, int size, uint64_t addr, vle_t* instr) {
  uint32_t i;
  int bufsize = size, add = 0;
  add = snprintf (str, bufsize, "%s", instr->name);
  for (i = 0; add > 0 && i < instr->n && add < bufsize; ++i) {
    if (instr->fields[i].type == TYPE_REG) {
      add += snprintf (str + add, bufsize - add, " r%u", instr->fields[i].value);
    } else if (instr->fields[i].type == TYPE_IMM) {
      add += snprintf (str + add, bufsize - add, " 0x%x", instr->fields[i].value);
    } else if (instr->fields[i].type == TYPE_MEM) {
      add += snprintf (str + add, bufsize - add, " 0x%x(r%d)", instr->fields[i + 1].value, instr->fields[i].value);
      i++;
    } else if (instr->fields[i].type == TYPE_JMP) {
      add += snprintf (str + add, bufsize - add, " 0x%" PFMT64x, addr + instr->fields[i].value);
    } else if (instr->fields[i].type == TYPE_CR) {
      add += snprintf (str + add, bufsize - add, " cr%u", instr->fields[i].value);
    }
  }
}