64-bit back-end interface fails

[jjts]

This was reported by Salima

a test case should be created

if the problem exists it should be fixed

can the axi ram we have been using support 64-bits?

[jjts]

related to iob-soc #433

[jjts]

A CPU trap issue occurs when the backend data width is set to 64 instead of 32, when cache is in iob-soc

iob-soc issue iob-soc #433 has been closed

[spzeno]

Hi，I've fonud a testcase you mentioned above:

the iob-cache's parameter set is:

It's backend is 64 bit AXI interface and it is connected with a AXI-bus-matrix's master port.
A 64 bit memory with AXI interface is connected with AXI-bus-matrix's slave port.

if the software is this:

*(volatile int *)(0xf0088000) = 0x2;
if (*(volatile int *)(0xf0088000) != 0x2)
  uart0_putline("0xf0088000 fail\n");

then no fail msg uart will put.

However, if the software is this:

*(volatile int *)(0xf0088000) = 0x2;
*(volatile int *)(0xf0090000) = 0x3;
*(volatile int *)(0xf0098000) = 0x4;
if (*(volatile int *)(0xf0088000) != 0x2)
  uart0_putline("0xf0088000 fail\n");

error will happen:

the waveform:

I think that the errors may because of these signals

EDIT: I found that if I set cache's N_WAYS to 1, there will be no error

[jjts]

Hi @spzeno , pls try branch fix#241 and let me know if it fixes the issue

[spzeno]

Oops，seems like it failed as soon as the first time try to write