-
Notifications
You must be signed in to change notification settings - Fork 116
/
Copy pathscalarizationOfDescriptorLoadsTest14.lgc
144 lines (130 loc) · 9.43 KB
/
scalarizationOfDescriptorLoadsTest14.lgc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool lgc --version 4
; RUN: lgc -mcpu=gfx1010 -print-after=lgc-builder-replayer -o - %s 2>&1 | FileCheck --check-prefixes=CHECK %s
; This test checks how the scalarization of descriptor loads works if some values are defined in the loop pre-header
; and others inside the loop and the returned value of lgc.create.image.sample.v4f32 call is used outside of the loop
; in lgc.create.image.store.
source_filename = "llpc_fragment_7"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8-p32:32:32"
target triple = "amdgcn--amdpal"
; Function Attrs: nounwind
define dllexport spir_func void @lgc.shader.FS.main() local_unnamed_addr #0 !spirv.ExecutionModel !8 !lgc.shaderstage !9 {
; CHECK-LABEL: define dllexport spir_func void @lgc.shader.FS.main(
; CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] !spirv.ExecutionModel [[META8:![0-9]+]] !lgc.shaderstage [[META9:![0-9]+]] {
; CHECK-NEXT: .entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.s.getpc()
; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[I:%.*]] = call i32 (...) @lgc.input.import.interpolated__i32(i1 false, i32 3, i32 0, i32 0, i32 poison, i32 1, i32 poison)
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @lgc.load.user.data__i32(i32 0)
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP4]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr addrspace(4)
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr addrspace(4) [[TMP7]], i32 4), "dereferenceable"(ptr addrspace(4) [[TMP7]], i32 -1) ]
; CHECK-NEXT: [[I1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP7]], i32 0
; CHECK-NEXT: [[TMP8:%.*]] = call i32 @lgc.load.user.data__i32(i32 0)
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP8]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = bitcast <2 x i32> [[TMP9]] to i64
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr addrspace(4)
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr addrspace(4) [[TMP11]], i32 4), "dereferenceable"(ptr addrspace(4) [[TMP11]], i32 -1) ]
; CHECK-NEXT: [[I2:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP11]], i32 32
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[PHI_IND:%.*]] = phi i32 [ 0, [[DOTENTRY:%.*]] ], [ [[IND:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[PHI_IMG:%.*]] = phi <4 x float> [ {{(splat \(float 1\.000000e\+00\))|(<float 1\.000000e\+00, float 1\.000000e\+00, float 1\.000000e\+00, float 1\.000000e\+00>)}}, [[DOTENTRY]] ], [ [[I11:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[I3:%.*]] = mul i32 [[PHI_IND]], 48
; CHECK-NEXT: [[I4:%.*]] = sext i32 [[I3]] to i64
; CHECK-NEXT: [[I5:%.*]] = getelementptr i8, ptr addrspace(4) [[I1]], i64 [[I4]]
; CHECK-NEXT: [[I6:%.*]] = mul i32 [[PHI_IND]], 48
; CHECK-NEXT: [[I7:%.*]] = sext i32 [[I6]] to i64
; CHECK-NEXT: [[I8:%.*]] = getelementptr i8, ptr addrspace(4) [[I2]], i64 [[I7]]
; CHECK-NEXT: [[TMP25:%.*]] = load <8 x i32>, ptr addrspace(4) [[I5]], align 4, !invariant.load [[META10:![0-9]+]]
; CHECK-NEXT: [[TMP26:%.*]] = load <4 x i32>, ptr addrspace(4) [[I8]], align 4, !invariant.load [[META10]]
; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.amdgcn.waterfall.begin.i32(i32 0, i32 [[I3]])
; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.amdgcn.waterfall.readfirstlane.i32.i32(i32 [[TMP12]], i32 [[I3]])
; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr addrspace(4) [[I1]], i64 [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = load <8 x i32>, ptr addrspace(4) [[TMP15]], align 4, !invariant.load [[META10]]
; CHECK-NEXT: [[TMP17:%.*]] = sext i32 [[TMP13]] to i64
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr addrspace(4) [[I2]], i64 [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP18]], align 4, !invariant.load [[META10]]
; CHECK-NEXT: [[TMP20:%.*]] = call reassoc nnan nsz arcp contract afn <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32{{(\.v8i32)?}}{{(\.v4i32)?}}(i32 15, float 0.000000e+00, float 0.000000e+00, <8 x i32> [[TMP16]], <4 x i32> [[TMP19]], i1 false, i32 0, i32 0)
; CHECK-NEXT: [[I11]] = call reassoc nnan nsz arcp contract afn <4 x float> @llvm.amdgcn.waterfall.end.v4f32(i32 [[TMP12]], <4 x float> [[TMP20]])
; CHECK-NEXT: [[I12:%.*]] = fadd <4 x float> [[PHI_IMG]], {{(splat \(float 1\.000000e\+00\))|(<float 1\.000000e\+00, float 1\.000000e\+00, float 1\.000000e\+00, float 1\.000000e\+00>)}}
; CHECK-NEXT: [[IND]] = add i32 [[PHI_IND]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp ne i32 [[IND]], 1000
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[TMP27:%.*]] = load <8 x i32>, ptr addrspace(4) [[I8]], align 4, !invariant.load [[META10]]
; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.amdgcn.waterfall.begin.i32(i32 0, i32 [[I6]])
; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.waterfall.readfirstlane.i32.i32(i32 [[TMP21]], i32 [[I6]])
; CHECK-NEXT: [[TMP23:%.*]] = sext i32 [[TMP22]] to i64
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr addrspace(4) [[I2]], i64 [[TMP23]]
; CHECK-NEXT: [[TMP28:%.*]] = load <8 x i32>, ptr addrspace(4) [[TMP24]], align 4, !invariant.load [[META10]]
; CHECK-NEXT: [[TMP29:%.*]] = call <8 x i32> @llvm.amdgcn.waterfall.last.use.v8i32(i32 [[TMP21]], <8 x i32> [[TMP28]])
; CHECK-NEXT: call void @llvm.amdgcn.image.store.1d.v4f32.i32{{(\.v8i32)?}}(<4 x float> [[I12]], i32 15, i32 1, <8 x i32> [[TMP29]], i32 0, i32 0)
; CHECK-NEXT: ret void
;
.entry:
%i = call i32 (...) @lgc.create.read.generic.input__i32(i32 3, i32 0, i32 0, i32 0, i32 17, i32 poison)
%i1 = call ptr addrspace(4) (...) @lgc.create.get.desc.ptr.p4(i32 1, i32 1, i64 0, i32 7)
%i2 = call ptr addrspace(4) (...) @lgc.create.get.desc.ptr.p4(i32 2, i32 2, i64 0, i32 7)
br label %loop
loop: ; preds = %loop, %.entry
%phi.ind = phi i32 [ 0, %.entry ], [ %ind, %loop ]
%phi.img = phi <4 x float> [ <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %.entry ], [ %i11, %loop ]
%a = call i32 (...) @lgc.create.get.desc.stride__i32(i32 1, i32 1, i64 0, i32 7)
%b = call i32 (...) @lgc.create.get.desc.stride__i32(i32 2, i32 2, i64 0, i32 7)
%i3 = mul i32 %phi.ind, %a
%i4 = sext i32 %i3 to i64
%i5 = getelementptr i8, ptr addrspace(4) %i1, i64 %i4
%i6 = mul i32 %phi.ind, %b
%i7 = sext i32 %i6 to i64
%i8 = getelementptr i8, ptr addrspace(4) %i2, i64 %i7
%i11 = call reassoc nnan nsz arcp contract afn <4 x float> (...) @lgc.create.image.sample.v4f32(i32 1, i32 24, ptr addrspace(4) %i5, ptr addrspace(4) %i8, i32 1, <2 x float> zeroinitializer)
%i12 = fadd <4 x float> %phi.img, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%ind = add i32 %phi.ind, 1
%cond = icmp ne i32 %ind, 1000
br i1 %cond, label %loop, label %exit
exit: ; preds = %loop
call void (...) @lgc.create.image.store(<4 x float> %i12, i32 0, i32 8, ptr addrspace(4) %i8, i32 1)
ret void
}
declare spir_func void @spirv.NonUniform.i32(i32) local_unnamed_addr
; Function Attrs: nounwind memory(none)
declare ptr addrspace(4) @lgc.create.get.desc.ptr.p4(...) local_unnamed_addr #1
; Function Attrs: nounwind memory(none)
declare i32 @lgc.create.get.desc.stride__i32(...) local_unnamed_addr #1
; Function Attrs: nounwind willreturn memory(read)
declare <4 x float> @lgc.create.image.sample.v4f32(...) local_unnamed_addr #2
; Function Attrs: nounwind willreturn memory(read)
declare i32 @lgc.create.read.generic.input__i32(...) local_unnamed_addr #2
; Function Attrs: nounwind memory(write)
declare void @lgc.create.image.store(...) local_unnamed_addr #3
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign" }
attributes #1 = { nounwind memory(none) }
attributes #2 = { nounwind willreturn memory(read) }
attributes #3 = { nounwind memory(write) }
!lgc.client = !{!0}
!lgc.unlinked = !{!1}
!lgc.options = !{!2}
!lgc.options.FS = !{!3}
!lgc.user.data.nodes = !{!4, !5}
!lgc.color.export.formats = !{!6}
!amdgpu.pal.metadata.msgpack = !{!7}
!0 = !{!"Vulkan"}
!1 = !{i32 1}
!2 = !{i32 -158725823, i32 1419665388, i32 -1015833383, i32 -491143713, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 256, i32 256, i32 2, i32 1}
!3 = !{i32 -1822594139, i32 1920663194, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 64, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 1800, i32 0, i32 0, i32 1}
!4 = !{!"DescriptorTableVaPtr", i32 7, i32 64, i32 0, i32 1, i32 1}
!5 = !{!"DescriptorCombinedTexture", i32 3, i32 64, i32 0, i32 192, i64 0, i32 7, i32 12}
!6 = !{i32 14, i32 7, i32 0, i32 0, i32 15}
!7 = !{!"\82\B0amdpal.pipelines\91\83\B0.spill_threshold\CD\FF\FF\B0.user_data_limit\00\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\E8\D2\98>j\B9B\94\CF2\DEF\BF\9Fx\BC1\AD.llpc_version\A470.1\AEamdpal.version\92\03\00"}
!8 = !{i32 4}
!9 = !{i32 6}
!10 = !{}
;.
; CHECK: [[META8]] = !{i32 4}
; CHECK: [[META9]] = !{i32 6}
; CHECK: [[META10]] = !{}
;.