1+ /*
2+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
3+ * Copyright (C) 2006-2015 Cadence Design Systems, Inc.
4+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
5+ *
6+ * SPDX-License-Identifier: MIT
7+ *
8+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
9+ * this software and associated documentation files (the "Software"), to deal in
10+ * the Software without restriction, including without limitation the rights to
11+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
12+ * the Software, and to permit persons to whom the Software is furnished to do so,
13+ * subject to the following conditions:
14+ *
15+ * The above copyright notice and this permission notice shall be included in all
16+ * copies or substantial portions of the Software.
17+ *
18+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
20+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
22+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24+ *
25+ * https://www.FreeRTOS.org
26+ * https://github.com/FreeRTOS
27+ *
28+ */
29+
130/*******************************************************************************
2- Copyright (c) 2006-2015 Cadence Design Systems Inc.
3-
4- Permission is hereby granted, free of charge, to any person obtaining
5- a copy of this software and associated documentation files (the
6- "Software"), to deal in the Software without restriction, including
7- without limitation the rights to use, copy, modify, merge, publish,
8- distribute, sublicense, and/or sell copies of the Software, and to
9- permit persons to whom the Software is furnished to do so, subject to
10- the following conditions:
11-
12- The above copyright notice and this permission notice shall be included
13- in all copies or substantial portions of the Software.
14-
15- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19- CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22- --------------------------------------------------------------------------------
2331
2432 XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
2533
@@ -87,16 +95,16 @@ NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
8795 INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
8896
8997 A stack frame of this structure is allocated for any interrupt or exception.
90- It goes on the current stack. If the RTOS has a system stack for handling
91- interrupts, every thread stack must allow space for just one interrupt stack
98+ It goes on the current stack. If the RTOS has a system stack for handling
99+ interrupts, every thread stack must allow space for just one interrupt stack
92100 frame, then nested interrupt stack frames go on the system stack.
93101
94- The frame includes basic registers (explicit) and "extra" registers introduced
102+ The frame includes basic registers (explicit) and "extra" registers introduced
95103 by user TIE or the use of the MAC16 option in the user's Xtensa config.
96104 The frame size is minimized by omitting regs not applicable to user's config.
97105
98106 For Windowed ABI, this stack frame includes the interruptee's base save area,
99- another base save area to manage gcc nested functions, and a little temporary
107+ another base save area to manage gcc nested functions, and a little temporary
100108 space to help manage the spilling of the register windows.
101109-------------------------------------------------------------------------------
102110*/
@@ -164,7 +172,7 @@ STRUCT_END(XtExcFrame)
164172
165173#else
166174
167- #define XT_STK_NEXT2 XT_STK_NEXT1
175+ #define XT_STK_NEXT2 XT_STK_NEXT1
168176
169177#endif
170178
@@ -181,20 +189,20 @@ STRUCT_END(XtExcFrame)
181189-------------------------------------------------------------------------------
182190 SOLICITED STACK FRAME FOR A THREAD
183191
184- A stack frame of this structure is allocated whenever a thread enters the
192+ A stack frame of this structure is allocated whenever a thread enters the
185193 RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
186194 It goes on the current thread's stack.
187195
188196 The solicited frame only includes registers that are required to be preserved
189- by the callee according to the compiler's ABI conventions, some space to save
197+ by the callee according to the compiler's ABI conventions, some space to save
190198 the return address for returning to the caller, and the caller's PS register.
191199
192200 For Windowed ABI, this stack frame includes the caller's base save area.
193201
194202 Note on XT_SOL_EXIT field:
195203 It is necessary to distinguish a solicited from an interrupt stack frame.
196204 This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
197- always at the same offset (0). It can be written with a code (usually 0)
205+ always at the same offset (0). It can be written with a code (usually 0)
198206 to distinguish a solicted frame from an interrupt frame. An RTOS port may
199207 opt to ignore this field if it has another way of distinguishing frames.
200208-------------------------------------------------------------------------------
@@ -239,7 +247,7 @@ STRUCT_END(XtSolFrame)
239247 and the context switch of that co-processor is then peformed by the handler.
240248 Ownership represents which thread's state is currently in the co-processor.
241249
242- Co-processors may not be used by interrupt or exception handlers. If an
250+ Co-processors may not be used by interrupt or exception handlers. If an
243251 co-processor instruction is executed by an interrupt or exception handler,
244252 the co-processor exception handler will trigger a kernel panic and freeze.
245253 This restriction is introduced to reduce the overhead of saving and restoring
@@ -250,7 +258,7 @@ STRUCT_END(XtSolFrame)
250258 such as in the thread control block or above the thread stack area. It need
251259 not be in the interrupt stack frame since interrupts don't use co-processors.
252260
253- Along with the save area for each co-processor, two bitmasks with flags per
261+ Along with the save area for each co-processor, two bitmasks with flags per
254262 co-processor (laid out as in the CPENABLE reg) help manage context-switching
255263 co-processors as efficiently as possible:
256264
@@ -266,10 +274,10 @@ STRUCT_END(XtSolFrame)
266274
267275 XT_CPSTORED
268276 A bitmask with the same layout as CPENABLE, a bit per co-processor.
269- Indicates whether the state of each co-processor is saved in the state
277+ Indicates whether the state of each co-processor is saved in the state
270278 save area. When a thread enters the kernel, only the state of co-procs
271- still enabled in CPENABLE is saved. When the co-processor exception
272- handler assigns ownership of a co-processor to a thread, it restores
279+ still enabled in CPENABLE is saved. When the co-processor exception
280+ handler assigns ownership of a co-processor to a thread, it restores
273281 the saved state only if this bit is set, and clears this bit.
274282
275283 XT_CP_CS_ST
@@ -352,7 +360,7 @@ STRUCT_END(XtSolFrame)
352360 For framed functions the frame is created and the return address saved at
353361 base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
354362 For frameless functions, there is no frame and return address remains in a0.
355- Note: Because CPP macros expand to a single line, macros requiring multi-line
363+ Note: Because CPP macros expand to a single line, macros requiring multi-line
356364 expansions are implemented as assembler macros.
357365-------------------------------------------------------------------------------
358366*/
@@ -365,7 +373,7 @@ STRUCT_END(XtSolFrame)
365373 addi sp , sp , - \size
366374 s32i a0 , sp , 0
367375 .endm
368- #define ENTRY0
376+ #define ENTRY0
369377 #define RET (sz ) ret1 sz
370378 .macro ret1 size = 0x10
371379 l32i a0 , sp , 0
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