diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json
index 81b6b205cd..6cf64e32cf 100644
--- a/unittests/InstructionCountCI/X87ldst-SVE.json
+++ b/unittests/InstructionCountCI/X87ldst-SVE.json
@@ -34,7 +34,7 @@
     },
     "2-store 80bit": {
       "x86InstructionCount": 2,
-      "ExpectedInstructionCount": 25,
+      "ExpectedInstructionCount": 24,
       "x86Insts": [
         "fstp tword [rax]",
         "fstp tword [rax+10]"
@@ -55,7 +55,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0xa (10)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -69,7 +68,7 @@
     },
     "8-store 80bit": {
       "x86InstructionCount": 8,
-      "ExpectedInstructionCount": 97,
+      "ExpectedInstructionCount": 90,
       "x86Insts": [
         "fstp tword [rax]",
         "fstp tword [rax+10]",
@@ -96,7 +95,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0xa (10)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -108,7 +106,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x14 (20)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -120,7 +117,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x1e (30)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -132,7 +128,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x28 (40)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -144,7 +139,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x32 (50)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -156,7 +150,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x3c (60)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -168,7 +161,6 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x46 (70)",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
@@ -201,7 +193,7 @@
     },
     "2-load 80bit": {
       "x86InstructionCount": 2,
-      "ExpectedInstructionCount": 22,
+      "ExpectedInstructionCount": 21,
       "x86Insts": [
         "fld tword [rax]",
         "fld tword [rax+10]"
@@ -210,7 +202,6 @@
         "ptrue p2.h, vl5",
         "ld1h {z2.h}, p2/z, [x4]",
         "add x20, x4, #0xa (10)",
-        "ptrue p2.h, vl5",
         "ld1h {z3.h}, p2/z, [x20]",
         "ldrb w20, [x28, #1019]",
         "sub w20, w20, #0x2 (2)",
@@ -233,7 +224,7 @@
     },
     "8-load 80bit": {
       "x86InstructionCount": 8,
-      "ExpectedInstructionCount": 59,
+      "ExpectedInstructionCount": 52,
       "x86Insts": [
         "fld tword [rax]",
         "fld tword [rax+10]",
@@ -248,25 +239,18 @@
         "ptrue p2.h, vl5",
         "ld1h {z2.h}, p2/z, [x4]",
         "add x20, x4, #0xa (10)",
-        "ptrue p2.h, vl5",
         "ld1h {z3.h}, p2/z, [x20]",
         "add x20, x4, #0x14 (20)",
-        "ptrue p2.h, vl5",
         "ld1h {z4.h}, p2/z, [x20]",
         "add x20, x4, #0x1e (30)",
-        "ptrue p2.h, vl5",
         "ld1h {z5.h}, p2/z, [x20]",
         "add x20, x4, #0x28 (40)",
-        "ptrue p2.h, vl5",
         "ld1h {z6.h}, p2/z, [x20]",
         "add x20, x4, #0x32 (50)",
-        "ptrue p2.h, vl5",
         "ld1h {z7.h}, p2/z, [x20]",
         "add x20, x4, #0x3c (60)",
-        "ptrue p2.h, vl5",
         "ld1h {z8.h}, p2/z, [x20]",
         "add x20, x4, #0x46 (70)",
-        "ptrue p2.h, vl5",
         "ld1h {z9.h}, p2/z, [x20]",
         "ldrb w20, [x28, #1019]",
         "sub w20, w20, #0x8 (8)",