Enable external reference clock #14

sq6emm · 2025-01-06T12:00:22Z

If possible, please enable external reference to be possible to be used.

FPSychotic · 2025-01-06T12:02:57Z

I have GPSDO, SI5351 device and Hackrf output to help to test that if needed

F5OEO · 2025-01-07T15:24:00Z

This request is for libresdr

VasylSamoilov · 2025-01-09T09:41:24Z

I also have GPSDO, can help with testing. It's just unclear how to set refclock to external and how to read status is it locked on external clock or not...

F5OEO · 2025-01-09T09:49:16Z

This is done by modifying the devicetree in u-boot-env : I plan to rewrite the UbootEnv.txt to be universal

sq6emm · 2025-01-11T06:26:24Z

I am ready for testing;P mmcx to sma jumper arrived;P

lubuntu-l100 · 2025-01-18T12:47:54Z

I have tested the LibreSDR-Tezuka firmware of January 16 2025 with SDR Console v3.4 beta. SDR Console v3.4 is now running fine in RX as well as TX over the QO100.

I am waiting for the enablement of the 10 Mhz external clock, due to the fact that the internal VCTTXO is not on frequency and is drifting a littlebit during transmission on the QO100. Locking on 10 Mhz is a need during qso's. I am following the github discussion around the Renovate of the original HDL in LibreSDR and the incorporation in the LibreSDR Tezuka firmware.

I am able to test this configuration with 10 Mhz and the Libresdr due to the fact that I have running already several Pluto's Rev B for DATV and measurement activities with GPSDO's and OCXO's since 2019.

LibreSDR with 10 Mhz supported could be a good and cheap alternative for the AD Pluto's.

lubuntu-l100 · 2025-01-18T12:49:57Z

I forgot my callsign in the previous post. My callsign is PA2JSA, see my QRZ.com pages.

sly547 · 2025-01-22T00:39:11Z

I am following the github discussion around the Renovate of the original HDL in LibreSDR and the incorporation in the LibreSDR Tezuka firmware.

Sorry to hijack but I can't seem to find that discussion (too many places to check, I'm lost). Could you give me a pointer please?

Also I wonder if the currently unused DAC that controls the VCTCXO can help with the drift. Without a reference the LibreSDR cannot measure the drift and thus not regulate the frequency, right?

lubuntu-l100 · 2025-01-22T08:28:49Z

Hello Michael, Some roughly explanation how the 10 Mhz needs to work. The 10 Mhz signals is connected to a driver IC and then connected to the FPGA. The 7z020 FPGA compares the 10 Mhz signal with the 40 Mhz from the VCTCXO. The differences in frequency is going to the DAC that corrects the VCTCXO. The output of the 40 Mhz is divided in 2 signals, 1 is going to the AD9363 and the other is going the FPGA. So the frequency correction is completely done outside the AD9363. So defining an external clock is not working due to the fact that the external clock is related to the AD9363 and not the way the LibreSDR is doing frequency correction. Below some links where this discussion is going. https://github.com/F5OEO/tezuka_fw/issues?q=state%3Aopen%20label%3A%22libresdr%22 https://github.com/sdy623/hdl sdy623/hdl@5b9bcef https://github.com/maia-sdr/plutosdr-fw Hope this will help you. 73 Jaap PA2JSA Call Sign: PA2JSA Operator: Jaap Schekkerman Location: JO22QE Country: The Netherlands Email: ***@***.*** ***@***.***>

…

__________________________IMPORTANT NOTICE_______________________ The content of this email and any attachments are confidential and intended for the named recipient(s) only. If you are not the intended recipient of this e-mail, any dissemination, distribution or copying of this e-mail, and any attachments thereto, is strictly prohibited. If you have received this e-mail in error, please immediately notify the sender by e-mail or by telephone and permanently delete all copies of this e-mail and any attachments. The name of the sender at the bottom of this message or contained anywhere else in this e-mail is only for identification and is not intended to and shall not act as a signature indicating agreement or the formation of a contract unless that is specifically stated in the body of the e-mail message. WARNING: Although PA2JSA has taken reasonable precautions to ensure no viruses are present in this email, PA2JSA cannot accept responsibility for any loss or damage arising from the use of this email or attachments. From: Michael Büchler ***@***.*** Sent: Wednesday, January 22, 2025 1:40 To: F5OEO/tezuka_fw ***@***.***> Cc: lubuntu-l100 ***@***.***>; Comment ***@***.***> Subject: Re: [F5OEO/tezuka_fw] Enable external reference clock (Issue #14) I am following the github discussion around the Renovate of the original HDL in LibreSDR and the incorporation in the LibreSDR Tezuka firmware. Sorry to hijack but I can't seem to find that discussion (too many places to check, I'm lost). Could you give me a pointer please? Also I wonder if the currently unused DAC that controls the VCTCXO can help with the drift. Without a reference the LibreSDR cannot measure the drift and thus not regulate the frequency, right? — Reply to this email directly, view it on GitHub <#14 (comment)> , or unsubscribe <https://github.com/notifications/unsubscribe-auth/AKF5VZWXNDIXSATZ2IE52HD2L3SELAVCNFSM6AAAAABUVO4N7GVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDMMBWGAZTEMJYGM> . You are receiving this because you commented. <https://github.com/notifications/beacon/AKF5VZWYDS64SGU3T6EFSHT2L3SELA5CNFSM6AAAAABUVO4N7GWGG33NNVSW45C7OR4XAZNMJFZXG5LFINXW23LFNZ2KUY3PNVWWK3TUL5UWJTU3KTSTO.gif> Message ID: ***@***.*** ***@***.***> >

sly547 · 2025-01-22T10:17:23Z

Hi!

Some roughly explanation how the 10 Mhz needs to work. The 10 Mhz signals is connected to a driver IC and then connected to the FPGA. The 7z020 FPGA compares the 10 Mhz signal with the 40 Mhz from the VCTCXO. The differences in frequency is going to the DAC that corrects the VCTCXO. The output of the 40 Mhz is divided in 2 signals, 1 is going to the AD9363 and the other is going the FPGA.

Ahh right, the AD9363 gets the 40 MHz directly from the oscillator, not through the FPGA, so we can't just multiply the external 10 MHz in the FPGA and route that to the AD9363. Thanks for explaining!

Are you aware of another PlutoSDR variant that is already doing this correction with the FPGA? I checked Pluto rev.D and Pluto+, they use the external frequency directly on the AD9363.

Below some links where this discussion is going.

Thanks! I need to check maia-sdr, this I did not really have on my radar yet. I thought there might be a single place where this discussion is happening, but then it is still scattered. I started one myself here: #42

lubuntu-l100 · 2025-01-22T10:40:25Z

Hi Michael, The Libresdr is a clone of the Ettus B210 and not a clone of the Adalm Pluto. The Ettus software supports the external 10 Mhz, the Pluto cloned software does not have supported for that. F5OEO got the routines from the Ettus B210 software and need to combine these with the pluto software in new to develop firmware for the Libresdr Tazuka project. I use at this time the fw from Tazuka v3e31 from last week that is running fine on my libresdr. F5OEO has announced to incorporate the 10 Mhz external clock in upcomming versions. I use the Libresdr together with ad plutos for communication over the QO100 satellite. Tx at 2.4 Ghz, Rx at 10 Ghz with a downconverter. Libresdr is 5.8 khz off frequency at 2.4 Ghz and drift around 500 hz. So F5OEO is working on a solution. 73 Jaap Pa2jsa ⁣BlueMail voor Android downloaden Op 22 jan 2025 11:18, om 11:18, "Michael Büchler" ***@***.***> schreef:

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Hi! > Some roughly explanation how the 10 Mhz needs to work. The 10 Mhz signals is connected to a driver IC and then connected to the FPGA. The 7z020 FPGA compares the 10 Mhz signal with the 40 Mhz from the VCTCXO. The differences in frequency is going to the DAC that corrects the VCTCXO. The output of the 40 Mhz is divided in 2 signals, 1 is going to the AD9363 and the other is going the FPGA. Ahh right, the AD9363 gets the 40 MHz directly from the oscillator, not through the FPGA, so we can't just multiply the external 10 MHz in the FPGA and route that to the AD9363. Thanks for explaining! Are you aware of another PlutoSDR variant that is already doing this correction with the FPGA? I checked Pluto rev.D and Pluto+, they use the external frequency directly on the AD9363. > Below some links where this discussion is going. Thanks! I need to check maia-sdr, this I did not really have on my radar yet. I thought there might be a single place where this discussion is happening, but then it is still scattered. I started one myself here: #42 -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you commented. Message ID: ***@***.***>

sly547 · 2025-01-23T01:02:12Z

Hello Jaap,

Thank you for clarifying some things. These devices are all new to me. I started looking into the Ettus repository a bit. It's great to find all of this as open source.

Communicating over QO100 looks like a good motivation to get the external clock working. Really nice that this QO100 is a thing now. I don't have a clear target application yet, but maybe something related to (mobile) telecom networks (see OSMOCOM / srsRAN). Also something with low drift requirements. But as I said, I'm new to this.

I will try to get the DAC working on my board, so I can control it from software and do simple tests.

Notupus · 2025-02-11T21:16:34Z

With the new commit apparently there is support for pps and 10mhz on tezuka now, but I dont know how to enable it since the led stays off when using my "gpsdo" which is the timepulse from a ublox gps receiver, which is a pps or 10mhz square wave . Not sure if that can work or be adapted to work.

F5OEO · 2025-02-11T21:27:42Z

This is a very early try thanks to discussion with hz12opensource/libresdr#10 (comment)
It should be automatic as soon as you have a 10Mhz, >2.5vpp.
I don't have opportunity to test right now.

sq6emm · 2025-02-11T21:33:25Z

Testing it right now...
But how can I detect if it is fixed to my reference?:)
Any reaction I should expect from LED or some /sys file content?

I do not see any reaction on the waterfall/scope (movement of signals)

and btw this (LED) is a general issue with LibreSDR still... during the firmware update there is not blinking of anything like with Pluto... so maybe just some simple correction is needed to enable LEDs?

lubuntu-l100 · 2025-02-12T07:48:24Z

When your fixed reference is connected at start up, de blue led of 10 mhz or pps should blink permanently when de firmware support the 10 Mgz reference in the firmware. When at startup de 10 mhz led blink shortly and the fpga led start blinking permanently, there is no support for the external reference. The 10 Mhz external connection goes to the Z7020 fpga where the 10 mhz is compared with the 40 mhz vtcxo in a pll circuit. A dac is controlling the 40 mhz vtcxo. The output of the 40 mhz is splitup and buffered. 1 signal is going back to the clock input of the ad9363 and the other part is going to the fpga. So the external 10 mhz is not connected to the external clock of the ad9363. This way of synchronisation is based on the firmware of the Ettus B210. ⁣BlueMail voor Android downloaden Op 11 feb 2025 22:33, om 22:33, Dawid SQ6EMM ***@***.***> schreef:

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Testing it right now... But how can I detect if it is fixed to my reference?:) Any reaction I should expect from LED or some /sys file content? -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you commented. Message ID: ***@***.***>

lubuntu-l100 · 2025-02-12T08:31:46Z

Zyncsdr Layout and led function explanation. Chinese Source.

PA2JSA

sq6emm · 2025-02-12T10:16:58Z

It blinks/lights during the startup, but later not.

lubuntu-l100 · 2025-02-12T10:28:12Z

Hi David, that means that the firmware used do not support the external 10 Mhz function. I have tested the Libresdr with fw for the B210 and than the 10 Mhz led is blinking all the time. However that fw was not supporting the Z7020 fpga. ⁣BlueMail voor Android downloaden Op 12 feb 2025 11:17, om 11:17, Dawid SQ6EMM ***@***.***> schreef:

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It blinks/lights during the startup, but later not. -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you commented. Message ID: ***@***.***>

sq6emm · 2025-02-12T10:30:24Z

Hey, well yes most probably.
I am using master branch of tezuka_fw - just reporting the state;) But I think it might be also connected with no LEDs are blinking during the firmware update... so maybe its just different pins are LEDs...

lubuntu-l100 · 2025-02-12T10:37:58Z

Hi David I use the F5OEO Tezuka v0.0.95 firmware that is running fine ftom the Sd card except the support of the 10 Mhz external clock. However the same fw 0.0.95 loaded and booted from flash has a problem during Tx. I use the Libresdr on the QO100 satellite in Nb. During tx over the satellite I have a broad spectrum of spikes in the signal. Booting from the Sd card, the tx signal over the QO100 is clean. So there is something different between booting from sd or booting from flash. ⁣BlueMail voor Android downloaden Op 12 feb 2025 11:30, om 11:30, Dawid SQ6EMM ***@***.***> schreef:

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Hey, well yes most probably. I am using master branch of tezuka_fw - just reporting the state;) But I think it might be also connected with no LEDs are blinking during the firmware update... so maybe its just different pins are LEDs... -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you commented. Message ID: ***@***.***>

Notupus · 2025-02-12T10:45:07Z

. I have a 10mhz at maybe 3 volts and 1pps at 3.3V. I do no see a difference in the tx frequency at 1.6ghz going to a rtl-sdr with or without the reference, it seems to not work, however turning the led on an off at whatever the vctcxo is being controlled with would make sense, and I would prefer PPS since I can measure that with a simple multimeter. I expect to see a small jump in frequency when plugging in the ref clock.

lubuntu-l100 · 2025-02-12T11:01:16Z

What do you mean with turning the led on and off? I have tested the vctcxo at 2.4 Ghz over the satellite. The result is that the 2.4 Ghz is 5.6 khz of frequency compared to a gpsdo locked receiver. Even so the vctcxo is drifting a 500 hz during warming up. ⁣BlueMail voor Android downloaden Op 12 feb 2025 11:45, om 11:45, Panagiotis Plessas ***@***.***> schreef:

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. I have a 10mhz at maybe 3 volts and 1pps at 3.3V. I do no see a difference in the tx frequency at 1.6ghz going to a rtl-sdr with or without the reference, it seems to not work, however turning the led on an off at whatever the vctcxo is being controlled with would make sense, and I would prefer PPS since I can measure that with a simple multimeter. I expect to see a small jump in frequency when plugging in the ref clock. -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you commented. Message ID: ***@***.***>

Notupus · 2025-02-12T11:11:53Z

Okay, so you are claiming with tezuka_fw 0.1.0 and 10mhz input you can see the tuning? If so I will try to confirm this in due course maybe it doesnt like thats is a 10mpps signal.

lubuntu-l100 · 2025-02-12T11:34:31Z

Tezuka v0.1.0 does not support the 10 Mhz external reference at this time. Booted from sd card v0.1.0 is working fine with Sdr Console v3.4 beta, transmitting and receiving in full duplex over the QO100 satellite. Tx at 2.4 Ghz, Rx at 10 Ghz. ⁣BlueMail voor Android downloaden Op 12 feb 2025 12:12, om 12:12, Panagiotis Plessas ***@***.***> schreef:

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Okay, so you are claiming with tezuka_fw 0.1.0 and 10mhz input you can see the tuning? If so I will try to confirm this in due course maybe it doesnt like thats is a 10mpps signal. -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you commented. Message ID: ***@***.***>

lubuntu-l100 · 2025-02-13T13:07:28Z

The Link below on Github is a description of how to implement the 10 Mhz and 1PPS External clock reference in the Libresdr. Header is Renovate the original HDL in LibreSDR from SDY623.

I hope F5OEO can use these scripts as input for implementing the 10 Mhz and 1 PPS in the TAZUKA Firmware.

Link: sdy623/hdl@5b9bcef#diff-6b183c60e27cdb85d400546826482fe3e196d85e3abfe0e56d000736af943d7c

PA2JSA

lubuntu-l100 · 2025-02-17T12:02:51Z

Hardware Modification: 40 Mhz External Reference Clock for AD9363 in ZyncSDR / LibrSDR

The Zyncsdr / Libresdr has a 10 Mhz external reference to lock the 40 Mhz internal VCTCXO via the FPGA 7Z020, however to support for this 10 Mhz synchronization is not available in current Tezuka Firmware for the Zyncsdr. With my experiences to modify the internal VTcxo of Adalm Pluto’s and replace that with an external 40 Mhz reference from a Leobodnar GPSDO. I decided to test if I can do the same with the Zyncsdr with the Tazuka FW 0.1.0.
Looking at the hardware diagram, you can see that the 40 Mhz VCTCXO is controlled by a PLL circuit in the FPGA 7Z020 where the 10 Mhz external reference is compared with the 40 Mhz of the VCTCXO. Differences in frequency are converted by a DAC5311 into a voltage that is steering the 40 MHZ VCTCXO.
The output of the 40 Mhz oscillator is buffered by a SN74AHC1G14DBVR and then split in two 40 Mhz signals and again buffered. 1 Signal is going back to the FPGA 7Z020 and the other part of the 40 Mhz signal is going to the AD9363 as 40Mhz internal clock signal.
At this point I decided to modify the 40 Mhz signal that is going to the AD9363 and replace that with a 40 Mhz signal from a 40 Mhz Leobodnar GPSDO signal.

In attached document:
ZyncSDR 40 Mhz External Reference.pdf

you can find how to modify the ZyncSDR to use an external 40 Mhz Reference signal for the AD9363. This hardware modification is equal to simular modifications in Adalm Pluto SDR transceivers. Test with the Tezuka 0.1.0 Firmware at the QO100 Satellite shows no difference between an AD Pluto or the Zyncsdr in terms of Stability and on Frequency.

Evenso at QRZ.com you can find the modification at PA2JSA page.

PA2JSA

F5OEO · 2025-02-17T12:10:37Z

Thanks for this hardware mod @lubuntu-l100 . Could be useful until the 10Mhz input could work directly (work in progress - not trivial).

lubuntu-l100 · 2025-02-20T17:11:01Z

You can easily check that on QO100 in NB. When starting up, you can see if Beacon is on frequency. I had a frequency that was 1.5 khz of at reception (739 Mhz and 5.5 khz off at Tx (2.4 Ghz) drifting 500 hz at warming up. A locked signal at 40 Mhz was spot on. 73 Pa2jsa ⁣BlueMail voor Android downloaden Op 20 feb 2025 17:35, om 17:35, F5OEO ***@***.***> schreef:

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F5OEO left a comment (F5OEO/tezuka_fw#14) Story continue : it seems that VCTXO is not a real one on my Hamgeek (as mentionned #45 (comment)). I will build a firmware with a test to see if the frequency change with vctxo is working. -- Reply to this email directly or view it on GitHub: #14 (comment) You are receiving this because you were mentioned. Message ID: ***@***.***>

F5OEO · 2025-02-26T13:24:13Z

@sq6emm it could be very interesting that I could test the firmware from opensourcelabs. We need to extract it from qspi and save it to sd for example or in ram and then transfer them over ssh.

sq6emm · 2025-02-26T13:29:43Z

@F5OEO happy to help, but how?:) I still have not flashed the opensourcelabs so its possible;)

F5OEO · 2025-02-26T13:33:44Z

I need to make a script to extract the firmware. As far as I know, it is the only one which is working with rf clck

sq6emm · 2025-02-26T14:16:50Z

Please remember that the original firmware is Linux (lubuntu) based....

sq6emm · 2025-02-26T22:20:32Z

dd of=boot.bin if=/dev/mtdblock0 bs=64k
dd of=u-boot-env.bin if=/dev/mtdblock1 bs=64k
dd of=firmware.frm if=/dev/mtdblock3 bs=64k

should do the job?

F5OEO · 2025-02-26T22:28:43Z

Exactly !

sq6emm · 2025-02-26T22:30:28Z

firmware.frm.gz

u-boot-env.bin.gz

boot.bin.gz

sq6emm · 2025-02-26T22:32:45Z

Please remember that the original firmware is Linux (lubuntu) based....

I was wrong with it. This is firmware on the sd card.
But the one on flash is:

______ _       _        _________________
| ___ \ |     | |      /  ___|  _  \ ___ \
| |_/ / |_   _| |_ ___ \ `--.| | | | |_/ /
|  __/| | | | | __/ _ \ `--. \ | | |    /
| |   | | |_| | || (_) /\__/ / |/ /| |\ \
\_|   |_|\__,_|\__\___/\____/|___/ \_| \_|

v0.37-dirty
https://wiki.analog.com/university/tools/pluto

and password is "root", not "analog"

F5OEO · 2025-02-26T22:37:06Z

Wow....Fantastic ! Will give it a try tomorrow !

sq6emm · 2025-02-26T22:39:15Z

# cat /opt/VERSIONS /etc/os-release 
device-fw v0.37-dirty
hdl dev_prj_2018_r1-1763-ge5660-dirty
buildroot 2021.02.7-adi-6643-g0d5db4-dirty
linux adi-xilinx-2020.1-98725-g3eae70-dirty
u-boot-xlnx v0.20-PlutoSDR-25-g90401c-dirty
NAME=Buildroot
VERSION=-g0d5db4a280-dirty
ID=buildroot
VERSION_ID=2022.02.3
PRETTY_NAME="Buildroot 2022.02.3"

sq6emm · 2025-02-26T22:40:47Z

This might help!

https://gitee.com/zyq-77/hdl/tree/dev_prj_2018_r1

F5OEO · 2025-02-26T22:59:44Z

This is an hdl repo, but where is the buildroot project !

F5OEO · 2025-02-27T15:11:55Z

Experimental version using 10Mhz (de18b11)
Put a 10Mhz source with at least 7dm, you should see led 10mhz ON.
If you have chance to have a vctxo (zynqsdr), it should pilot it. Not on my hamgeek libresdr.
Workaround :
Use a script /root/adj_10mhz.sh which should calculate and set xo_correction. (Need to check if the sign is ok).
Feedback welcomed !

F5OEO · 2025-02-27T15:38:03Z

And seems that chrony adjustement is not far from value calculated by 10mhz ref in.

./adj_10mhz.sh

Xo Correction 40000042
Xo Correction 40000044
Xo Correction 40000042
Xo Correction 40000044
Xo Correction 40000042
^C

./adj_chrony.sh

High accurate ppm = 1.249 +/- 0.385 slow
Correct 40000050
High accurate ppm = 1.249 +/- 0.385 slow
Correct 40000050

sq6emm · 2025-02-27T15:54:13Z

make libre_maiasdr_defconfig && make
[...]

  Downloaded 23 crates (12.4 MB) in 4.08s (largest was `aws-lc-sys` at 8.3 MB)
error: rustc 1.79.0 is not supported by the following packages:
  [email protected] requires rustc 1.81
  [email protected] requires rustc 1.81
  [email protected] requires rustc 1.80.0
  [email protected] requires rustc 1.80.0
  [email protected] requires rustc 1.80.0
  [email protected] requires rustc 1.81
Either upgrade rustc or select compatible dependency versions with
`cargo update <name>@<current-ver> --precise <compatible-ver>`
where `<compatible-ver>` is the latest version supporting rustc 1.79.0

>>> maia-httpd sweep Building
xz: /home/dawszy/git/original/tezuka_fw/buildroot-2024.08/output/build/maia-httpd-sweep//maia-httpd/target/armv7-unknown-linux-gnueabihf/release/maia-httpd: No such file or directory
>>> maia-httpd sweep Installing to target
/usr/bin/install -D /home/dawszy/git/original/tezuka_fw/buildroot-2024.08/output/build/maia-httpd-sweep//maia-httpd/target/armv7-unknown-linux-gnueabihf/release/maia-httpd.xz /home/dawszy/git/original/tezuka_fw/buildroot-2024.08/output/target/usr/bin/
/usr/bin/install: cannot stat '/home/dawszy/git/original/tezuka_fw/buildroot-2024.08/output/build/maia-httpd-sweep//maia-httpd/target/armv7-unknown-linux-gnueabihf/release/maia-httpd.xz': No such file or directory
make[1]: *** [package/pkg-generic.mk:380: /home/dawszy/git/original/tezuka_fw/buildroot-2024.08/output/build/maia-httpd-sweep/.stamp_target_installed] Error 1
make: *** [Makefile:83: _all] Error 2

F5OEO · 2025-02-27T16:09:46Z

You need to migrate to latest buildroot : wget https://buildroot.org/downloads/buildroot-2024.11.1.tar.gz

sq6emm · 2025-02-27T16:22:58Z

You need to migrate to latest buildroot : wget https://buildroot.org/downloads/buildroot-2024.11.1.tar.gz

Yeah my mistake;) Thanks, on it.

sq6emm · 2025-02-27T18:36:20Z

I dont have time to test more today, but LED is not ON as on original firmware;)

sq6emm · 2025-02-27T18:41:14Z

I confirm.
7dBm works. LED is on and ./adj_10mhz.sh is working fine!
Congrats!

F5OEO · 2025-02-28T08:13:56Z

Could be a good idea to test with 1 pps also..I will try to use a low cost GPS pour that. Don't know if 3.3V pulse is not too much

Notupus · 2025-02-28T08:32:19Z

Is it in theory already supported?

F5OEO · 2025-02-28T08:39:00Z

Yes...

Notupus · 2025-02-28T09:21:17Z

Well no led and adj 10mhz is not working

F5OEO · 2025-02-28T09:36:37Z

Can you uncomment this line (directly with nano under /root/adj_10mhz.sh)

tezuka_fw/board/pluto/overlay_maia/root/adj_10mhz.sh

Line 5 in 696b9be

#echo "Reg $read_register"

And give me what it outputs...

sq6emm · 2025-02-28T11:00:04Z

Well no led and adj 10mhz is not working

7dBm of 10MHz signal is important.... below it wont work. Make sure you have that level. Unless you have opensourcelabsdr then it works from -10 dBm

sq6emm · 2025-02-28T15:38:16Z

firmware.frm.gz

u-boot-env.bin.gz

boot.bin.gz

@F5OEO based on those files... you think this version of software might be needed running yet for any tests yet or I can flash it to tezuka?:)

F5OEO · 2025-02-28T16:46:25Z

I began to analyse it...but not yet compelety extracted. It is precious..keep it on the flash, and test tezuka on sd !

sq6emm · 2025-02-28T20:32:50Z

I began to analyse it...but not yet compelety extracted. It is precious..keep it on the flash, and test tezuka on sd !

Yes Sir!

Notupus · 2025-02-28T22:08:46Z

Can you uncomment this line (directly with nano under /root/adj_10mhz.sh)

tezuka_fw/board/pluto/overlay_maia/root/adj_10mhz.sh

Line 5 in 696b9be
#echo "Reg $read_register"

And give me what it outputs...

WIth PPS the register reads as such (noled)
devmem 0x41210000
0x00000008
10MHZ square wave from ublox( probably weak but I have the opensourcelabs version)(led on)
devmem 0x41210000
0x0000000A
and nothing
devmem 0x41210000
0x00000008
Maybe you can use a radiosonde to do pps for testing.

F5OEO added the enhancement New feature or request label Jan 7, 2025

F5OEO added the libresdr label Jan 8, 2025

Enable external reference clock #14

Enable external reference clock #14

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./adj_10mhz.sh

./adj_chrony.sh

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