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x86 decoding table contains a number of incorrect categories #7410
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This affects the Public v2 Google Workload Traces. |
derekbruening
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Mar 28, 2025
Adds a check that the load and store categories strictly match the instr_{reads,writes}_memory() on every x86 opcode. This revealed a number of incorrect catLoad and catStore labels which are now removed from: + OP_lea (see also below) + OP_lahf (see also below) + OP_vbroadcastf32x2 + OP_vbroadcasti32x2 + OP_fld with only register operands + OP_fst{,p} with only register operands + OP_fld* which insert literals Fixes {v,}movntdqa which the above check detected had its operands in the wrong order: it was listed as a store in the table when it is in fact a load. Also adds catSIMD to some variants that were missing it. Fixes the following x86 ISA category errors: + OP_lea is now catMath instead of catLoad + OP_nop_modrm is now catOther instead of catSIMD + OP_lahf is now catState instead of catLoad Categorizes the following previously uncategorized opcodes: + OP_xchg and OP_fxchg are now catMove + OP_pushf is now catStore|catState + OP_popf is now catLoad|catState + OP_sahf is now catState + OP_cmov* is now catMove + OP_nop is now catOther Fixes #7410
derekbruening
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Mar 31, 2025
Adds a check that the load and store categories strictly match the instr_{reads,writes}_memory() on every x86 opcode. This revealed a number of incorrect catLoad and catStore labels which are now removed from: + OP_lea (see also below) + OP_lahf (see also below) + OP_vbroadcastf32x2 + OP_vbroadcasti32x2 + OP_fld with only register operands + OP_fst{,p} with only register operands + OP_fld* which insert literals Splits the ir_x86_{3,4}args_avx512_evex_mask files up further to avoid OOM in 32-bit VS (xref #3992, #4610). Fixes {v,}movntdqa which the above check detected had its operands in the wrong order: it was listed as a store in the table when it is in fact a load. Also adds catSIMD to some variants that were missing it. Fixes the following x86 ISA category errors: + OP_lea is now catMath instead of catLoad + OP_nop_modrm is now catOther instead of catSIMD + OP_lahf is now catState instead of catLoad Categorizes the following previously uncategorized opcodes: + OP_xchg and OP_fxchg are now catMove + OP_pushf is now catStore|catState + OP_popf is now catLoad|catState + OP_sahf is now catState + OP_cmov* is now catMove + OP_nop is now catOther None of these changes affect other IR interfaces like instr_{reads,write}_memory(). There is no compatibility issue with drmemtrace address traces: no raw trace impact; the final trace is impacted for movntdqa and (for regdeps) the categories but there's no compatibility change: just an increase in accuracy from raw2trace or record_filter output. Fixes #7410
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#6238 added initial categorization to a bunch of x86 opcodes in decode_table, with load/store added dynamically to those that vary.
But later I noticed a number of categories that are incorrect:
I'm going to add a check to api.ir that the load and store categories are not present if the instruction does not do a load or store.
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