From 68392804e760db1993343193b0c94bec748cf02a Mon Sep 17 00:00:00 2001 From: "David Benes (FEKT)" Date: Wed, 6 Nov 2024 09:10:50 +0000 Subject: [PATCH] CARDS: [FEATURE] Add Support for Terasic A2700 Accelerator card --- apps/minimal/build/a2700/Makefile | 23 + apps/minimal/build/a2700/Quartus.tcl | 31 + apps/minimal/build/a2700/app_conf.tcl | 24 + cards/terasic/a2700/config/card_conf.tcl | 89 ++ cards/terasic/a2700/config/card_const.tcl | 56 ++ cards/terasic/a2700/constr/device.qsf | 12 + cards/terasic/a2700/constr/general.qsf | 68 ++ cards/terasic/a2700/constr/pcie.qsf | 118 +++ cards/terasic/a2700/constr/qsfp.qsf | 149 ++++ cards/terasic/a2700/constr/qsfp_200G.qsf | 64 ++ cards/terasic/a2700/constr/qsfp_misc.qsf | 36 + cards/terasic/a2700/constr/qsfp_virtual.qsf | 18 + cards/terasic/a2700/constr/sodimm0.qsf | 151 ++++ cards/terasic/a2700/constr/sodimm1.qsf | 151 ++++ cards/terasic/a2700/constr/sodimm2.qsf | 151 ++++ cards/terasic/a2700/constr/sodimm_hps.qsf | 147 ++++ cards/terasic/a2700/constr/timing.sdc | 44 + cards/terasic/a2700/readme.rst | 66 ++ cards/terasic/a2700/scripts/generate_jic.sh | 79 ++ cards/terasic/a2700/scripts/write_jic.sh | 53 ++ cards/terasic/a2700/src/Modules.tcl | 57 ++ cards/terasic/a2700/src/Quartus.inc.tcl | 65 ++ cards/terasic/a2700/src/card.mk | 42 + cards/terasic/a2700/src/fpga.vhd | 800 ++++++++++++++++++ .../a2700/src/ip/ddr4_calibration.ip.tcl | 36 + cards/terasic/a2700/src/ip/ftile_eth.ip.tcl | 42 + cards/terasic/a2700/src/ip/ftile_pll.ip.tcl | 22 + cards/terasic/a2700/src/ip/iopll.ip.tcl | 62 ++ .../terasic/a2700/src/ip/onboard_ddr4.ip.tcl | 79 ++ cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl | 85 ++ doc/source/index.rst | 1 + 31 files changed, 2821 insertions(+) create mode 100644 apps/minimal/build/a2700/Makefile create mode 100644 apps/minimal/build/a2700/Quartus.tcl create mode 100644 apps/minimal/build/a2700/app_conf.tcl create mode 100644 cards/terasic/a2700/config/card_conf.tcl create mode 100644 cards/terasic/a2700/config/card_const.tcl create mode 100644 cards/terasic/a2700/constr/device.qsf create mode 100644 cards/terasic/a2700/constr/general.qsf create mode 100644 cards/terasic/a2700/constr/pcie.qsf create mode 100644 cards/terasic/a2700/constr/qsfp.qsf create mode 100644 cards/terasic/a2700/constr/qsfp_200G.qsf create mode 100644 cards/terasic/a2700/constr/qsfp_misc.qsf create mode 100644 cards/terasic/a2700/constr/qsfp_virtual.qsf create mode 100644 cards/terasic/a2700/constr/sodimm0.qsf create mode 100644 cards/terasic/a2700/constr/sodimm1.qsf create mode 100644 cards/terasic/a2700/constr/sodimm2.qsf create mode 100644 cards/terasic/a2700/constr/sodimm_hps.qsf create mode 100644 cards/terasic/a2700/constr/timing.sdc create mode 100644 cards/terasic/a2700/readme.rst create mode 100644 cards/terasic/a2700/scripts/generate_jic.sh create mode 100644 cards/terasic/a2700/scripts/write_jic.sh create mode 100644 cards/terasic/a2700/src/Modules.tcl create mode 100644 cards/terasic/a2700/src/Quartus.inc.tcl create mode 100644 cards/terasic/a2700/src/card.mk create mode 100644 cards/terasic/a2700/src/fpga.vhd create mode 100644 cards/terasic/a2700/src/ip/ddr4_calibration.ip.tcl create mode 100644 cards/terasic/a2700/src/ip/ftile_eth.ip.tcl create mode 100644 cards/terasic/a2700/src/ip/ftile_pll.ip.tcl create mode 100644 cards/terasic/a2700/src/ip/iopll.ip.tcl create mode 100644 cards/terasic/a2700/src/ip/onboard_ddr4.ip.tcl create mode 100644 cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl diff --git a/apps/minimal/build/a2700/Makefile b/apps/minimal/build/a2700/Makefile new file mode 100644 index 000000000..3141a13a7 --- /dev/null +++ b/apps/minimal/build/a2700/Makefile @@ -0,0 +1,23 @@ +# Makefile: Makefile for Terasic Mercury A2700 Accelerator Card +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +COMBO_BASE = ../../../.. +CARD_BASE = $(COMBO_BASE)/cards/terasic/a2700 +APP_CONF = app_conf.tcl + + +OUTPUT_NAME = a2700-400g-minimal + +all: 400g1 + +400g1 : ETH_PORT_SPEED=400 +400g1 : ETH_PORT_CHAN=1 +400g1 : OUTPUT_NAME:=$(OUTPUT_NAME)-400g1 +400g1 : EHIP_PORT_TYPE=0 +400g1 : build +1x400g-8: 400g-1 + +include $(CARD_BASE)/src/card.mk diff --git a/apps/minimal/build/a2700/Quartus.tcl b/apps/minimal/build/a2700/Quartus.tcl new file mode 100644 index 000000000..0ebe6073e --- /dev/null +++ b/apps/minimal/build/a2700/Quartus.tcl @@ -0,0 +1,31 @@ +# Quartus.tcl: Quartus tcl script to compile whole FPGA design +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: The purpose of this file is described in the Parameterization section of +# the NDK-CORE documentation. + +# ----- Setting basic synthesis options --------------------------------------- +# NDK & user constants +source $env(CARD_BASE)/src/Quartus.inc.tcl + +# Create only a Quartus project for further design flow driven from Quartus GUI +# "0" ... full design flow in command line +# "1" ... project composition only for further dedesign flow in GUI +set SYNTH_FLAGS(PROJ_ONLY) "0" + +# Associative array which is propagated to APPLICATION_CORE, add other +# parameters if necessary. +set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE + +# Convert associative array to list +set APP_ARCHGRP_L [array get APP_ARCHGRP] + +# ----- Add application core to main component list --------------------------- +lappend HIERARCHY(COMPONENTS) \ + [list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L] + +# Call main function which handle targets +nb_main diff --git a/apps/minimal/build/a2700/app_conf.tcl b/apps/minimal/build/a2700/app_conf.tcl new file mode 100644 index 000000000..d4d0cdbeb --- /dev/null +++ b/apps/minimal/build/a2700/app_conf.tcl @@ -0,0 +1,24 @@ +# app_conf.tcl: User parameters for Terasic Mercury A2700 Accelerator Card +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration. + +# ------------------------------------------------------------------------------ +# DMA parameters: +# ------------------------------------------------------------------------------ +# The minimum number of RX/TX DMA channels for this card is 32. +set DMA_RX_CHANNELS 32 +set DMA_TX_CHANNELS 32 +# In blocking mode, packets are dropped only when the RX DMA channel is off. +# In non-blocking mode, packets are dropped whenever they cannot be sent. +set DMA_RX_BLOCKING_MODE true + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set PROJECT_NAME "NDK_MINIMAL" +set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS" +set PROJECT_VERSION [exec cat ../../../../VERSION] diff --git a/cards/terasic/a2700/config/card_conf.tcl b/cards/terasic/a2700/config/card_conf.tcl new file mode 100644 index 000000000..e425c73e1 --- /dev/null +++ b/cards/terasic/a2700/config/card_conf.tcl @@ -0,0 +1,89 @@ +# card_conf.tcl: Default parameters for Terasic A2700 +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# NOTE: For the detailed description of this file, visit the Parametrization section +# in the documentation of the NDK-FPGA/core repository. +# +# Mandatory project parameters +set PROJECT_NAME "" + +# ------------------------------------------------------------------------------ +# ETH parameters: +# ------------------------------------------------------------------------------ +# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED ! +# Note that there are two QSFP ports available, but only 400G is supported. +set ETH_PORTS 1 +# Speed for each one of the ETH_PORTS (allowed values: 400, 200, 100, 50, 40, 25, 10) +# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and +# each index has associated a required port speed. +# NOTE: at this moment, all ports must have same speed ! +set ETH_PORT_SPEED(0) $env(ETH_PORT_SPEED) +# Number of channels for each one of the ETH_PORTS (allowed values: 1, 2, 4, 8) +# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and +# each index has associated a required number of channels this port has. +# NOTE: at this moment, all ports must have same number of channels ! +set ETH_PORT_CHAN(0) $env(ETH_PORT_CHAN) +# Number of lanes for each one of the ETH_PORTS +# Typical values: 4 (QSFP), 8 (QSFP-DD) +set ETH_PORT_LANES(0) 8 +# EHIP_PORT_TYPE is an array where each index represents given ETH_PORT and +# each index has associated a required type of IP core, which this port has. +# NOTE: at this moment, all ports must have same type of IP core ! +set EHIP_PORT_TYPE(0) $env(EHIP_PORT_TYPE) + +# ------------------------------------------------------------------------------ +# PCIe parameters (not all combinations work): +# ------------------------------------------------------------------------------ +# Supported combinations for this card: +# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 +# 1x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: limited DMA performance) +# ------------------------------------------------------------------------------ + +# Set default PCIe configuration +set PCIE_CONF "1xGen5x8x8" +if { [info exist env(PCIE_CONF)] } { + set PCIE_CONF $env(PCIE_CONF) +} + +# Parsing PCIE_CONF string to list of parameters +set pcie_conf_list [ParsePcieConf $PCIE_CONF] + +# PCIe Generation (possible values: 4, 5): +# 4 = PCIe Gen4 (Stratix 10 with P-Tile or Agilex) +# 5 = PCIe Gen5 (Agilex with R-Tile) +set PCIE_GEN [lindex $pcie_conf_list 1] +# PCIe endpoints (possible values: 2, 4): +# 2 = 2x PCIe x16 in two slot OR 2x PCIe x8 in one slot (bifurcation x8+x8) +# 4 = 4x PCIe x8 in two slots (bifurcation x8+x8) +set PCIE_ENDPOINTS [lindex $pcie_conf_list 0] +# PCIe endpoint mode (possible values: 1): +# 1 = 2x8 lanes (bifurcation x8+x8) +set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2] + +# ------------------------------------------------------------------------------ +# DMA parameters: +# ------------------------------------------------------------------------------ +# This variable can be set in COREs *.mk file or as a parameter when launching the make +set DMA_TYPE $env(DMA_TYPE) +# The minimum number of RX/TX DMA channels for this card is 32. +set DMA_RX_CHANNELS 32 +set DMA_TX_CHANNELS 32 +# In blocking mode, packets are dropped only when the RX DMA channel is off. +# In non-blocking mode, packets are dropped whenever they cannot be sent. +set DMA_RX_BLOCKING_MODE true + +# ------------------------------------------------------------------------------ +# DDR4 parameters: +# ------------------------------------------------------------------------------ +# Set this parameter to either 0 or 4. Other values are not supported. +# 0 = Disable SO-DIMM Memory +# 4 = Use all SO-DIMM modules +set DDR4_PORTS 4 + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +set TSU_ENABLE true diff --git a/cards/terasic/a2700/config/card_const.tcl b/cards/terasic/a2700/config/card_const.tcl new file mode 100644 index 000000000..68224a784 --- /dev/null +++ b/cards/terasic/a2700/config/card_const.tcl @@ -0,0 +1,56 @@ +# card_const.tcl: Card specific parameters for Terasic A2700 (developer only) +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# WARNING: The user should not deliberately change parameters in this file. For +# the description of this file, visit the Parametrization section in the +# documentation of the NDK-CORE repostiory + +set CARD_NAME "TERASIC-A2700" +# Achitecture of Clock generator +set CLOCK_GEN_ARCH "INTEL" +# Achitecture of PCIe module +set PCIE_MOD_ARCH "R_TILE" +# Achitecture of Network module +set NET_MOD_ARCH "F_TILE" +# Achitecture of SDM/SYSMON module +set SDM_SYSMON_ARCH "INTEL_SDM" +# Boot controller type - SDM +set BOOT_TYPE 4 + +# Total number of QSFP cages +set QSFP_CAGES 1 +# I2C address of each QSFP cage +set QSFP_I2C_ADDR(0) "0xA0" + +# ------------------------------------------------------------------------------ +# Checking of parameter compatibility +# ------------------------------------------------------------------------------ + +if {!(($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 1) || + ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} { + error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE! +Allowed PCIe configurations: +- 2xGen4x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 +- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1" +} + +#DDR4 +if {!($DDR4_PORTS == 0 || $DDR4_PORTS == 4) } { + error "Unsupported number of DDR4_PORTS: Select either 0 or 4" +} + +# Enable/add PCIe Gen5 x16 for experiments only! +#($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) || +#- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0" + +# ------------------------------------------------------------------------------ +# Other parameters: +# ------------------------------------------------------------------------------ +# Current setup is same for all IP cores, due to use of one pll with frequency (830,156Mhz), for all IP's: +# This setup value is defined as half of pll frequency +set TSU_FREQUENCY 415039062 + +setVhdlPkgInt DDR4_PORTS $DDR4_PORTS diff --git a/cards/terasic/a2700/constr/device.qsf b/cards/terasic/a2700/constr/device.qsf new file mode 100644 index 000000000..5f056663e --- /dev/null +++ b/cards/terasic/a2700/constr/device.qsf @@ -0,0 +1,12 @@ +# device.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Global assignments +# ============================================================================== + +set_global_assignment -name DEVICE AGIB027R29A1E2VB +set_global_assignment -name FAMILY Agilex diff --git a/cards/terasic/a2700/constr/general.qsf b/cards/terasic/a2700/constr/general.qsf new file mode 100644 index 000000000..941e81d01 --- /dev/null +++ b/cards/terasic/a2700/constr/general.qsf @@ -0,0 +1,68 @@ +# general.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Global assignments +# ============================================================================== + +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name DEVICE_IO_STANDARD_ALL "1.2 V" + +set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 +set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" +set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 75 +set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" +set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" + +#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" +# This is used for boot via SDM +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" +set_global_assignment -name USE_CONF_DONE SDM_IO16 +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ + +# F-Tile XCVR PRESERVE_UNUSED_XCVR_CHANNEL +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL AUTO +set_global_assignment -name CVP_MODE OFF +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN OFF +set_global_assignment -name HPS_DAP_SPLIT_MODE DISABLED +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 64 +#set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_115MHZ_IOSC +set_global_assignment -name GENERATE_COMPRESSED_SOF ON + + +set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1" + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +#50MHz +set_location_assignment PIN_J41 -to AG_SYSCLK1_P + +#100MHz - There may be a bug in Quartus that makes it virtually impossible to use this constraint with multiple EMIF controllers. +#It is possible to use this pin if Quartus assigns it automatically. More information here: +#https://community.intel.com/t5/Intel-Quartus-Prime-Software/Stratix-10-HPS-DDR4-EMIF-placement-error/m-p/1601633 +#set_location_assignment PIN_LB60 -to AG_SYSCLK1_P + +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK0_P +set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK1_P +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK0_P +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK1_P + + +set_global_assignment -name OCP_HW_EVAL DISABLE +# this parameter was set as disable because it makes problem with build for ftile IP cores diff --git a/cards/terasic/a2700/constr/pcie.qsf b/cards/terasic/a2700/constr/pcie.qsf new file mode 100644 index 000000000..4c26da8ef --- /dev/null +++ b/cards/terasic/a2700/constr/pcie.qsf @@ -0,0 +1,118 @@ +# pcie.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +set_location_assignment PIN_DR68 -to PCIE_CLK0_P +set_location_assignment PIN_CU68 -to PCIE_CLK1_P +set_location_assignment PIN_CD58 -to PCIE_PERST_N + +set_location_assignment PIN_DL74 -to PCIE_TX_P[0] +set_location_assignment PIN_DB77 -to PCIE_TX_P[1] +set_location_assignment PIN_CW74 -to PCIE_TX_P[2] +set_location_assignment PIN_CJ77 -to PCIE_TX_P[3] +set_location_assignment PIN_CF74 -to PCIE_TX_P[4] +set_location_assignment PIN_BU77 -to PCIE_TX_P[5] +set_location_assignment PIN_BP74 -to PCIE_TX_P[6] +set_location_assignment PIN_BE77 -to PCIE_TX_P[7] +set_location_assignment PIN_BB74 -to PCIE_TX_P[8] +set_location_assignment PIN_AM77 -to PCIE_TX_P[9] +set_location_assignment PIN_AJ74 -to PCIE_TX_P[10] +set_location_assignment PIN_Y77 -to PCIE_TX_P[11] +set_location_assignment PIN_V74 -to PCIE_TX_P[12] +set_location_assignment PIN_K74 -to PCIE_TX_P[13] +set_location_assignment PIN_C71 -to PCIE_TX_P[14] +set_location_assignment PIN_M71 -to PCIE_TX_P[15] + +set_location_assignment PIN_DH73 -to PCIE_TX_N[0] +set_location_assignment PIN_DE76 -to PCIE_TX_N[1] +set_location_assignment PIN_CT73 -to PCIE_TX_N[2] +set_location_assignment PIN_CM76 -to PCIE_TX_N[3] +set_location_assignment PIN_CC73 -to PCIE_TX_N[4] +set_location_assignment PIN_BY76 -to PCIE_TX_N[5] +set_location_assignment PIN_BL73 -to PCIE_TX_N[6] +set_location_assignment PIN_BH76 -to PCIE_TX_N[7] +set_location_assignment PIN_AW73 -to PCIE_TX_N[8] +set_location_assignment PIN_AR76 -to PCIE_TX_N[9] +set_location_assignment PIN_AF73 -to PCIE_TX_N[10] +set_location_assignment PIN_AC76 -to PCIE_TX_N[11] +set_location_assignment PIN_T73 -to PCIE_TX_N[12] +set_location_assignment PIN_G73 -to PCIE_TX_N[13] +set_location_assignment PIN_E69 -to PCIE_TX_N[14] +set_location_assignment PIN_P69 -to PCIE_TX_N[15] + +set_location_assignment PIN_DE82 -to PCIE_RX_P[0] +set_location_assignment PIN_CW80 -to PCIE_RX_P[1] +set_location_assignment PIN_CM82 -to PCIE_RX_P[2] +set_location_assignment PIN_CF80 -to PCIE_RX_P[3] +set_location_assignment PIN_BY82 -to PCIE_RX_P[4] +set_location_assignment PIN_BP80 -to PCIE_RX_P[5] +set_location_assignment PIN_BH82 -to PCIE_RX_P[6] +set_location_assignment PIN_BB80 -to PCIE_RX_P[7] +set_location_assignment PIN_AR82 -to PCIE_RX_P[8] +set_location_assignment PIN_AJ80 -to PCIE_RX_P[9] +set_location_assignment PIN_AC82 -to PCIE_RX_P[10] +set_location_assignment PIN_V80 -to PCIE_RX_P[11] +set_location_assignment PIN_P82 -to PCIE_RX_P[12] +set_location_assignment PIN_K80 -to PCIE_RX_P[13] +set_location_assignment PIN_M77 -to PCIE_RX_P[14] +set_location_assignment PIN_C77 -to PCIE_RX_P[15] + +set_location_assignment PIN_DB83 -to PCIE_RX_N[0] +set_location_assignment PIN_CT79 -to PCIE_RX_N[1] +set_location_assignment PIN_CJ83 -to PCIE_RX_N[2] +set_location_assignment PIN_CC79 -to PCIE_RX_N[3] +set_location_assignment PIN_BU83 -to PCIE_RX_N[4] +set_location_assignment PIN_BL79 -to PCIE_RX_N[5] +set_location_assignment PIN_BE83 -to PCIE_RX_N[6] +set_location_assignment PIN_AW79 -to PCIE_RX_N[7] +set_location_assignment PIN_AM83 -to PCIE_RX_N[8] +set_location_assignment PIN_AF79 -to PCIE_RX_N[9] +set_location_assignment PIN_Y83 -to PCIE_RX_N[10] +set_location_assignment PIN_T79 -to PCIE_RX_N[11] +set_location_assignment PIN_M83 -to PCIE_RX_N[12] +set_location_assignment PIN_G79 -to PCIE_RX_N[13] +set_location_assignment PIN_P76 -to PCIE_RX_N[14] +set_location_assignment PIN_E76 -to PCIE_RX_N[15] + +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_CLK0_P +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_CLK1_P +set_instance_assignment -name IO_STANDARD "1.0 V" -to PCIE_PERST_N + +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[4] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[5] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[6] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[7] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[8] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[9] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[10] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[11] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[12] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[13] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[14] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_TX_P[15] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[4] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[5] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[6] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[7] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[8] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[9] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[10] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[11] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[12] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[13] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[14] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_RX_P[15] diff --git a/cards/terasic/a2700/constr/qsfp.qsf b/cards/terasic/a2700/constr/qsfp.qsf new file mode 100644 index 000000000..52d855a8b --- /dev/null +++ b/cards/terasic/a2700/constr/qsfp.qsf @@ -0,0 +1,149 @@ +# qsfp.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_INITMODE +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_INT_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_MODPRS_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_MODSEL_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_RST_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_I2C_SDA + +set_location_assignment PIN_KE79 -to QSFP_RX_N[7] +set_location_assignment PIN_KH80 -to QSFP_RX_P[7] +set_location_assignment PIN_KB82 -to QSFP_RX_N[6] +set_location_assignment PIN_JW83 -to QSFP_RX_P[6] +set_location_assignment PIN_JN79 -to QSFP_RX_N[5] +set_location_assignment PIN_JT80 -to QSFP_RX_P[5] +set_location_assignment PIN_JK82 -to QSFP_RX_N[4] +set_location_assignment PIN_JG83 -to QSFP_RX_P[4] +set_location_assignment PIN_JA79 -to QSFP_RX_N[3] +set_location_assignment PIN_JD80 -to QSFP_RX_P[3] +set_location_assignment PIN_HU82 -to QSFP_RX_N[2] +set_location_assignment PIN_HP83 -to QSFP_RX_P[2] +set_location_assignment PIN_HE82 -to QSFP_RX_N[1] +set_location_assignment PIN_HB83 -to QSFP_RX_P[1] +set_location_assignment PIN_GN82 -to QSFP_RX_N[0] +set_location_assignment PIN_GK83 -to QSFP_RX_P[0] + +set_location_assignment PIN_KB76 -to QSFP_TX_N[7] +set_location_assignment PIN_JW77 -to QSFP_TX_P[7] +set_location_assignment PIN_JN73 -to QSFP_TX_N[6] +set_location_assignment PIN_JT74 -to QSFP_TX_P[6] +set_location_assignment PIN_JK76 -to QSFP_TX_N[5] +set_location_assignment PIN_JG77 -to QSFP_TX_P[5] +set_location_assignment PIN_HU76 -to QSFP_TX_N[4] +set_location_assignment PIN_HP77 -to QSFP_TX_P[4] +set_location_assignment PIN_HH79 -to QSFP_TX_N[3] +set_location_assignment PIN_HL80 -to QSFP_TX_P[3] +set_location_assignment PIN_HE76 -to QSFP_TX_N[2] +set_location_assignment PIN_HB77 -to QSFP_TX_P[2] +set_location_assignment PIN_GT79 -to QSFP_TX_N[1] +set_location_assignment PIN_GW80 -to QSFP_TX_P[1] +set_location_assignment PIN_GK77 -to QSFP_TX_N[0] +set_location_assignment PIN_GG78 -to QSFP_TX_P[0] + + +set_location_assignment PIN_JD74 -to QSFP_REFCLK0_P +set_location_assignment PIN_LL59 -to QSFP_INITMODE +set_location_assignment PIN_LL57 -to QSFP_INT_N +set_location_assignment PIN_KW57 -to QSFP_MODPRS_N +set_location_assignment PIN_LH56 -to QSFP_MODSEL_N +set_location_assignment PIN_KJ57 -to QSFP_RST_N +set_location_assignment PIN_LB58 -to QSFP_I2C_SCL +set_location_assignment PIN_LB56 -to QSFP_I2C_SDA + + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[4] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[5] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[6] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_P[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[4] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[5] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[6] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_RX_N[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[4] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[5] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[6] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_P[7] + +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[0] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[1] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[2] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[3] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[4] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[5] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[6] +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_TX_N[7] + +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[0] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[1] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[2] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[3] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[4] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[5] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[6] +set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to QSFP_RX_P[7] + +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[0] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[1] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[2] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[3] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[4] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[5] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[6] +set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to QSFP_RX_P[7] + +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[0] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[0] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[0] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[0] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[1] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[1] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[1] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[1] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[2] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[2] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[2] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[2] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[3] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[3] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[3] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[3] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[4] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[4] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[4] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[4] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[5] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[5] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[5] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[5] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[6] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[6] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[6] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[6] +set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=25" -to QSFP_TX_P[7] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to QSFP_TX_P[7] +set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to QSFP_TX_P[7] +set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to QSFP_TX_P[7] diff --git a/cards/terasic/a2700/constr/qsfp_200G.qsf b/cards/terasic/a2700/constr/qsfp_200G.qsf new file mode 100644 index 000000000..e589dff53 --- /dev/null +++ b/cards/terasic/a2700/constr/qsfp_200G.qsf @@ -0,0 +1,64 @@ +# QSFPDDA_200.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to MB71 + +# ============================================================================== +# For the future use +# ============================================================================== + +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDADDA_INITMODE +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDA_INT_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDA_MODPRS_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDA_MODSEL_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDA_RST_N +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDA_I2C_SCL +#set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFPDDA_I2C_SDA +# +#set_location_assignment PIN_KH74 -to QSFPDDA_TX_P[0] +#set_location_assignment PIN_KL77 -to QSFPDDA_TX_P[1] +#set_location_assignment PIN_LA74 -to QSFPDDA_TX_P[2] +#set_location_assignment PIN_LD77 -to QSFPDDA_TX_P[3] +#set_location_assignment PIN_LM74 -to QSFPDDA_TX_P[4] +#set_location_assignment PIN_LY74 -to QSFPDDA_TX_P[5] +#set_location_assignment PIN_MJ74 -to QSFPDDA_TX_P[6] +#set_location_assignment PIN_MB71 -to QSFPDDA_TX_P[7] +# +#set_location_assignment PIN_KL83 -to QSFPDDA_RX_P[0] +#set_location_assignment PIN_LA80 -to QSFPDDA_RX_P[1] +#set_location_assignment PIN_LD83 -to QSFPDDA_RX_P[2] +#set_location_assignment PIN_LM80 -to QSFPDDA_RX_P[3] +#set_location_assignment PIN_LP83 -to QSFPDDA_RX_P[4] +#set_location_assignment PIN_LY80 -to QSFPDDA_RX_P[5] +#set_location_assignment PIN_LP77 -to QSFPDDA_RX_P[6] +#set_location_assignment PIN_MB77 -to QSFPDDA_RX_P[7] +# +#set_location_assignment PIN_KE73 -to QSFPDDA_TX_N[0] +#set_location_assignment PIN_KP76 -to QSFPDDA_TX_N[1] +#set_location_assignment PIN_KV73 -to QSFPDDA_TX_N[2] +#set_location_assignment PIN_LG76 -to QSFPDDA_TX_N[3] +#set_location_assignment PIN_LK73 -to QSFPDDA_TX_N[4] +#set_location_assignment PIN_LV73 -to QSFPDDA_TX_N[5] +#set_location_assignment PIN_MG73 -to QSFPDDA_TX_N[6] +#set_location_assignment PIN_ME69 -to QSFPDDA_TX_N[7] +# +#set_location_assignment PIN_KP82 -to QSFPDDA_RX_N[0] +#set_location_assignment PIN_KV79 -to QSFPDDA_RX_N[1] +#set_location_assignment PIN_LG82 -to QSFPDDA_RX_N[2] +#set_location_assignment PIN_LK79 -to QSFPDDA_RX_N[3] +#set_location_assignment PIN_LT82 -to QSFPDDA_RX_N[4] +#set_location_assignment PIN_LV79 -to QSFPDDA_RX_N[5] +#set_location_assignment PIN_LT76 -to QSFPDDA_RX_N[6] +#set_location_assignment PIN_ME76 -to QSFPDDA_RX_N[7] +# +#set_location_assignment PIN_HJ68 -to QSFPDDA_REFCLK_p +#set_location_assignment PIN_KR59 -to QSFPDDA_INITMODE +#set_location_assignment PIN_KJ59 -to QSFPDDA_INT_N +#set_location_assignment PIN_KF56 -to QSFPDDA_MODPRS_N +#set_location_assignment PIN_LH58 -to QSFPDDA_MODSEL_N +#set_location_assignment PIN_KU60 -to QSFPDDA_RST_N +#set_location_assignment PIN_KR61 -to QSFPDDA_I2C_SCL +#set_location_assignment PIN_KU58 -to QSFPDDA_I2C_SDA diff --git a/cards/terasic/a2700/constr/qsfp_misc.qsf b/cards/terasic/a2700/constr/qsfp_misc.qsf new file mode 100644 index 000000000..202d0c0fb --- /dev/null +++ b/cards/terasic/a2700/constr/qsfp_misc.qsf @@ -0,0 +1,36 @@ +# qsfp_misc.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +#Terasic +set_location_assignment PIN_LB58 -to QSFP_I2C_SCL +set_location_assignment PIN_LB56 -to QSFP_I2C_SDA +set_location_assignment PIN_KW57 -to QSFP_MODPRS_N +set_location_assignment PIN_LL59 -to QSFP_INITMODE +set_location_assignment PIN_LH56 -to QSFP_MODSEL_N +set_location_assignment PIN_LL57 -to QSFP_INT_N +set_location_assignment PIN_KJ57 -to QSFP_RST_N + +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_MODPRS_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_INITMODE +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_MODSEL_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_INT_N +set_instance_assignment -name IO_STANDARD "1.2 V" -to QSFP_RST_N + +set_location_assignment PIN_B51 -to SI5397A_I2C_SCL +set_location_assignment PIN_D48 -to SI5397A_I2C_SDA +set_location_assignment PIN_D50 -to SI5397A_OE_n +set_location_assignment PIN_J49 -to SI5397A_RST_n + +set_instance_assignment -name IO_STANDARD "1.2 V" -to SI5397A_I2C_SCL +set_instance_assignment -name IO_STANDARD "1.2 V" -to SI5397A_I2C_SDA +set_instance_assignment -name IO_STANDARD "1.2 V" -to SI5397A_OE_n +set_instance_assignment -name IO_STANDARD "1.2 V" -to SI5397A_RST_n diff --git a/cards/terasic/a2700/constr/qsfp_virtual.qsf b/cards/terasic/a2700/constr/qsfp_virtual.qsf new file mode 100644 index 000000000..b44337c47 --- /dev/null +++ b/cards/terasic/a2700/constr/qsfp_virtual.qsf @@ -0,0 +1,18 @@ +# qsfp_virtual.qsf +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +#set_location_assignment PIN_JD74 -to QSFP_REFCLK0_P +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_REFCLK0_P +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_REFCLK0_N +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_REFCLK1_P +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_REFCLK1_N + +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_RX_P +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_RX_N +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_TX_P +set_instance_assignment -name VIRTUAL_PIN ON -to QSFP_TX_N + +set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to GK83 diff --git a/cards/terasic/a2700/constr/sodimm0.qsf b/cards/terasic/a2700/constr/sodimm0.qsf new file mode 100644 index 000000000..b9cfb41ae --- /dev/null +++ b/cards/terasic/a2700/constr/sodimm0.qsf @@ -0,0 +1,151 @@ +# sodimm0.qsf - DDR4B constraint file +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +#============================================================ +# DDR4B +#============================================================ +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to SODIMM0_REFCLK_P +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM0_REFCLK_P +set_location_assignment PIN_AG63 -to SODIMM0_REFCLK_P +set_location_assignment PIN_N59 -to SODIMM0_A[0] +set_location_assignment PIN_L60 -to SODIMM0_A[1] +set_location_assignment PIN_U59 -to SODIMM0_A[2] +set_location_assignment PIN_W60 -to SODIMM0_A[3] +set_location_assignment PIN_N61 -to SODIMM0_A[4] +set_location_assignment PIN_L62 -to SODIMM0_A[5] +set_location_assignment PIN_U61 -to SODIMM0_A[6] +set_location_assignment PIN_W62 -to SODIMM0_A[7] +set_location_assignment PIN_N63 -to SODIMM0_A[8] +set_location_assignment PIN_L64 -to SODIMM0_A[9] +set_location_assignment PIN_U63 -to SODIMM0_A[10] +set_location_assignment PIN_W64 -to SODIMM0_A[11] +set_location_assignment PIN_AT64 -to SODIMM0_A[12] +set_location_assignment PIN_AG65 -to SODIMM0_A[13] +set_location_assignment PIN_AK66 -to SODIMM0_A[14] +set_location_assignment PIN_AV65 -to SODIMM0_A[15] +set_location_assignment PIN_AT66 -to SODIMM0_A[16] +set_location_assignment PIN_AK70 -to SODIMM0_BA[0] +set_location_assignment PIN_AV68 -to SODIMM0_BA[1] +set_location_assignment PIN_AT70 -to SODIMM0_BG[0] +set_location_assignment PIN_B59 -to SODIMM0_BG[1] +set_location_assignment PIN_B63 -to SODIMM0_PCK +#set_location_assignment PIN_BJ68 -to SODIMM0_PCK[1] +set_location_assignment PIN_D64 -to SODIMM0_NCK +#set_location_assignment PIN_BM70 -to SODIMM0_NCK[1] +set_location_assignment PIN_J61 -to SODIMM0_CKE +#set_location_assignment PIN_H62 -to SODIMM0_CKE[1] +set_location_assignment PIN_AV47 -to SODIMM0_PDQS[0] +set_location_assignment PIN_AA53 -to SODIMM0_PDQS[1] +set_location_assignment PIN_AV53 -to SODIMM0_PDQS[2] +set_location_assignment PIN_AA47 -to SODIMM0_PDQS[3] +set_location_assignment PIN_N55 -to SODIMM0_PDQS[4] +set_location_assignment PIN_AA59 -to SODIMM0_PDQS[5] +set_location_assignment PIN_BJ59 -to SODIMM0_PDQS[6] +set_location_assignment PIN_AV59 -to SODIMM0_PDQS[7] +set_location_assignment PIN_B55 -to SODIMM0_PDQS[8] +set_location_assignment PIN_AT48 -to SODIMM0_NDQS[0] +set_location_assignment PIN_AD54 -to SODIMM0_NDQS[1] +set_location_assignment PIN_AT54 -to SODIMM0_NDQS[2] +set_location_assignment PIN_AD48 -to SODIMM0_NDQS[3] +set_location_assignment PIN_L56 -to SODIMM0_NDQS[4] +set_location_assignment PIN_AD60 -to SODIMM0_NDQS[5] +set_location_assignment PIN_BM60 -to SODIMM0_NDQS[6] +set_location_assignment PIN_AT60 -to SODIMM0_NDQS[7] +set_location_assignment PIN_D56 -to SODIMM0_NDQS[8] +set_location_assignment PIN_BF50 -to SODIMM0_DQ[0] +set_location_assignment PIN_BC49 -to SODIMM0_DQ[1] +set_location_assignment PIN_AV45 -to SODIMM0_DQ[2] +set_location_assignment PIN_AT46 -to SODIMM0_DQ[3] +set_location_assignment PIN_AT50 -to SODIMM0_DQ[4] +set_location_assignment PIN_AV49 -to SODIMM0_DQ[5] +set_location_assignment PIN_BC45 -to SODIMM0_DQ[6] +set_location_assignment PIN_BF46 -to SODIMM0_DQ[7] +set_location_assignment PIN_AA51 -to SODIMM0_DQ[8] +set_location_assignment PIN_AK52 -to SODIMM0_DQ[9] +set_location_assignment PIN_AK56 -to SODIMM0_DQ[10] +set_location_assignment PIN_AD56 -to SODIMM0_DQ[11] +set_location_assignment PIN_AN51 -to SODIMM0_DQ[12] +set_location_assignment PIN_AN55 -to SODIMM0_DQ[13] +set_location_assignment PIN_AA55 -to SODIMM0_DQ[14] +set_location_assignment PIN_AD52 -to SODIMM0_DQ[15] +set_location_assignment PIN_BC51 -to SODIMM0_DQ[16] +set_location_assignment PIN_AV51 -to SODIMM0_DQ[17] +set_location_assignment PIN_AT56 -to SODIMM0_DQ[18] +set_location_assignment PIN_AV55 -to SODIMM0_DQ[19] +set_location_assignment PIN_BC55 -to SODIMM0_DQ[20] +set_location_assignment PIN_BF52 -to SODIMM0_DQ[21] +set_location_assignment PIN_BF56 -to SODIMM0_DQ[22] +set_location_assignment PIN_AT52 -to SODIMM0_DQ[23] +set_location_assignment PIN_AK50 -to SODIMM0_DQ[24] +set_location_assignment PIN_AK46 -to SODIMM0_DQ[25] +set_location_assignment PIN_AA45 -to SODIMM0_DQ[26] +set_location_assignment PIN_AA49 -to SODIMM0_DQ[27] +set_location_assignment PIN_AD46 -to SODIMM0_DQ[28] +set_location_assignment PIN_AN45 -to SODIMM0_DQ[29] +set_location_assignment PIN_AN49 -to SODIMM0_DQ[30] +set_location_assignment PIN_AD50 -to SODIMM0_DQ[31] +set_location_assignment PIN_N53 -to SODIMM0_DQ[32] +set_location_assignment PIN_L54 -to SODIMM0_DQ[33] +set_location_assignment PIN_U57 -to SODIMM0_DQ[34] +set_location_assignment PIN_W58 -to SODIMM0_DQ[35] +set_location_assignment PIN_U53 -to SODIMM0_DQ[36] +set_location_assignment PIN_W54 -to SODIMM0_DQ[37] +set_location_assignment PIN_N57 -to SODIMM0_DQ[38] +set_location_assignment PIN_L58 -to SODIMM0_DQ[39] +set_location_assignment PIN_AK58 -to SODIMM0_DQ[40] +set_location_assignment PIN_AA57 -to SODIMM0_DQ[41] +set_location_assignment PIN_AN61 -to SODIMM0_DQ[42] +set_location_assignment PIN_AN57 -to SODIMM0_DQ[43] +set_location_assignment PIN_AA61 -to SODIMM0_DQ[44] +set_location_assignment PIN_AD58 -to SODIMM0_DQ[45] +set_location_assignment PIN_AD62 -to SODIMM0_DQ[46] +set_location_assignment PIN_AK62 -to SODIMM0_DQ[47] +set_location_assignment PIN_BV62 -to SODIMM0_DQ[48] +set_location_assignment PIN_CA61 -to SODIMM0_DQ[49] +set_location_assignment PIN_CA57 -to SODIMM0_DQ[50] +set_location_assignment PIN_BV58 -to SODIMM0_DQ[51] +set_location_assignment PIN_BM62 -to SODIMM0_DQ[52] +set_location_assignment PIN_BJ61 -to SODIMM0_DQ[53] +set_location_assignment PIN_BJ57 -to SODIMM0_DQ[54] +set_location_assignment PIN_BM58 -to SODIMM0_DQ[55] +set_location_assignment PIN_BC61 -to SODIMM0_DQ[56] +set_location_assignment PIN_AV61 -to SODIMM0_DQ[57] +set_location_assignment PIN_BF58 -to SODIMM0_DQ[58] +set_location_assignment PIN_AV57 -to SODIMM0_DQ[59] +set_location_assignment PIN_BF62 -to SODIMM0_DQ[60] +set_location_assignment PIN_AT62 -to SODIMM0_DQ[61] +set_location_assignment PIN_BC57 -to SODIMM0_DQ[62] +set_location_assignment PIN_AT58 -to SODIMM0_DQ[63] +set_location_assignment PIN_B57 -to SODIMM0_DQ[64] +set_location_assignment PIN_B53 -to SODIMM0_DQ[65] +set_location_assignment PIN_D54 -to SODIMM0_DQ[66] +set_location_assignment PIN_J57 -to SODIMM0_DQ[67] +set_location_assignment PIN_H54 -to SODIMM0_DQ[68] +set_location_assignment PIN_J53 -to SODIMM0_DQ[69] +set_location_assignment PIN_H58 -to SODIMM0_DQ[70] +set_location_assignment PIN_D58 -to SODIMM0_DQ[71] +set_location_assignment PIN_BC47 -to SODIMM0_DM_DBI[0] +set_location_assignment PIN_AN53 -to SODIMM0_DM_DBI[1] +set_location_assignment PIN_BC53 -to SODIMM0_DM_DBI[2] +set_location_assignment PIN_AN47 -to SODIMM0_DM_DBI[3] +set_location_assignment PIN_U55 -to SODIMM0_DM_DBI[4] +set_location_assignment PIN_AN59 -to SODIMM0_DM_DBI[5] +set_location_assignment PIN_CA59 -to SODIMM0_DM_DBI[6] +set_location_assignment PIN_BC59 -to SODIMM0_DM_DBI[7] +set_location_assignment PIN_J55 -to SODIMM0_DM_DBI[8] +set_location_assignment PIN_J59 -to SODIMM0_NCS +#set_location_assignment PIN_J63 -to SODIMM0_NCS[1] +set_location_assignment PIN_D60 -to SODIMM0_NRST +set_location_assignment PIN_B61 -to SODIMM0_ODT +#set_location_assignment PIN_D62 -to SODIMM0_ODT[1] +set_location_assignment PIN_H64 -to SODIMM0_PAR +set_location_assignment PIN_AG68 -to SODIMM0_NALERT +set_location_assignment PIN_H60 -to SODIMM0_NACT +set_location_assignment PIN_AV63 -to SODIMM0_OCT_RZQ diff --git a/cards/terasic/a2700/constr/sodimm1.qsf b/cards/terasic/a2700/constr/sodimm1.qsf new file mode 100644 index 000000000..fad160be5 --- /dev/null +++ b/cards/terasic/a2700/constr/sodimm1.qsf @@ -0,0 +1,151 @@ +# sodimm1.qsf - DDR4C constraint file +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +#============================================================ +# DDR4C +#============================================================ +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to SODIMM1_REFCLK_P +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM1_REFCLK_P +set_location_assignment PIN_KU36 -to SODIMM1_REFCLK_P +set_location_assignment PIN_LH42 -to SODIMM1_A[0] +set_location_assignment PIN_LL43 -to SODIMM1_A[1] +set_location_assignment PIN_KW43 -to SODIMM1_A[2] +set_location_assignment PIN_LB42 -to SODIMM1_A[3] +set_location_assignment PIN_LH40 -to SODIMM1_A[4] +set_location_assignment PIN_LL41 -to SODIMM1_A[5] +set_location_assignment PIN_LB40 -to SODIMM1_A[6] +set_location_assignment PIN_KW41 -to SODIMM1_A[7] +set_location_assignment PIN_LH38 -to SODIMM1_A[8] +set_location_assignment PIN_LL39 -to SODIMM1_A[9] +set_location_assignment PIN_KW39 -to SODIMM1_A[10] +set_location_assignment PIN_LB38 -to SODIMM1_A[11] +set_location_assignment PIN_KF36 -to SODIMM1_A[12] +set_location_assignment PIN_KU34 -to SODIMM1_A[13] +set_location_assignment PIN_KR35 -to SODIMM1_A[14] +set_location_assignment PIN_KF34 -to SODIMM1_A[15] +set_location_assignment PIN_KJ35 -to SODIMM1_A[16] +set_location_assignment PIN_KR33 -to SODIMM1_BA[0] +set_location_assignment PIN_KJ33 -to SODIMM1_BA[1] +set_location_assignment PIN_KF32 -to SODIMM1_BG[0] +set_location_assignment PIN_KR43 -to SODIMM1_BG[1] +set_location_assignment PIN_KR39 -to SODIMM1_PCK +#set_location_assignment PIN_JP32 -to SODIMM1_PCK[1] +set_location_assignment PIN_KU38 -to SODIMM1_NCK +#set_location_assignment PIN_JL33 -to SODIMM1_NCK[1] +set_location_assignment PIN_KF40 -to SODIMM1_CKE +#set_location_assignment PIN_KJ41 -to SODIMM1_CKE[1] +set_location_assignment PIN_LH34 -to SODIMM1_PDQS[0] +set_location_assignment PIN_MH30 -to SODIMM1_PDQS[1] +set_location_assignment PIN_MH11 -to SODIMM1_PDQS[2] +set_location_assignment PIN_LW17 -to SODIMM1_PDQS[3] +set_location_assignment PIN_LW33 -to SODIMM1_PDQS[4] +set_location_assignment PIN_MH23 -to SODIMM1_PDQS[5] +set_location_assignment PIN_LW5 -to SODIMM1_PDQS[6] +set_location_assignment PIN_LW27 -to SODIMM1_PDQS[7] +set_location_assignment PIN_LH28 -to SODIMM1_PDQS[8] +set_location_assignment PIN_LL35 -to SODIMM1_NDQS[0] +set_location_assignment PIN_MK31 -to SODIMM1_NDQS[1] +set_location_assignment PIN_MK13 -to SODIMM1_NDQS[2] +set_location_assignment PIN_MA19 -to SODIMM1_NDQS[3] +set_location_assignment PIN_MA34 -to SODIMM1_NDQS[4] +set_location_assignment PIN_MK25 -to SODIMM1_NDQS[5] +set_location_assignment PIN_MA7 -to SODIMM1_NDQS[6] +set_location_assignment PIN_MA28 -to SODIMM1_NDQS[7] +set_location_assignment PIN_LL29 -to SODIMM1_NDQS[8] +set_location_assignment PIN_LB32 -to SODIMM1_DQ[0] +set_location_assignment PIN_LB36 -to SODIMM1_DQ[1] +set_location_assignment PIN_LL33 -to SODIMM1_DQ[2] +set_location_assignment PIN_LH32 -to SODIMM1_DQ[3] +set_location_assignment PIN_KW33 -to SODIMM1_DQ[4] +set_location_assignment PIN_KW37 -to SODIMM1_DQ[5] +set_location_assignment PIN_LL37 -to SODIMM1_DQ[6] +set_location_assignment PIN_LH36 -to SODIMM1_DQ[7] +set_location_assignment PIN_MK29 -to SODIMM1_DQ[8] +set_location_assignment PIN_MD32 -to SODIMM1_DQ[9] +set_location_assignment PIN_MC33 -to SODIMM1_DQ[10] +set_location_assignment PIN_MD28 -to SODIMM1_DQ[11] +set_location_assignment PIN_MC29 -to SODIMM1_DQ[12] +set_location_assignment PIN_MK33 -to SODIMM1_DQ[13] +set_location_assignment PIN_MH28 -to SODIMM1_DQ[14] +set_location_assignment PIN_MH32 -to SODIMM1_DQ[15] +set_location_assignment PIN_MD7 -to SODIMM1_DQ[16] +set_location_assignment PIN_MC17 -to SODIMM1_DQ[17] +set_location_assignment PIN_MC9 -to SODIMM1_DQ[18] +set_location_assignment PIN_MD15 -to SODIMM1_DQ[19] +set_location_assignment PIN_MF5 -to SODIMM1_DQ[20] +set_location_assignment PIN_MH15 -to SODIMM1_DQ[21] +set_location_assignment PIN_MH7 -to SODIMM1_DQ[22] +set_location_assignment PIN_MK17 -to SODIMM1_DQ[23] +set_location_assignment PIN_MA15 -to SODIMM1_DQ[24] +set_location_assignment PIN_MA23 -to SODIMM1_DQ[25] +set_location_assignment PIN_LN15 -to SODIMM1_DQ[26] +set_location_assignment PIN_LR21 -to SODIMM1_DQ[27] +set_location_assignment PIN_LR13 -to SODIMM1_DQ[28] +set_location_assignment PIN_LW13 -to SODIMM1_DQ[29] +set_location_assignment PIN_LN23 -to SODIMM1_DQ[30] +set_location_assignment PIN_LW21 -to SODIMM1_DQ[31] +set_location_assignment PIN_MA36 -to SODIMM1_DQ[32] +set_location_assignment PIN_LW35 -to SODIMM1_DQ[33] +set_location_assignment PIN_LW31 -to SODIMM1_DQ[34] +set_location_assignment PIN_LR31 -to SODIMM1_DQ[35] +set_location_assignment PIN_LR35 -to SODIMM1_DQ[36] +set_location_assignment PIN_LN36 -to SODIMM1_DQ[37] +set_location_assignment PIN_MA32 -to SODIMM1_DQ[38] +set_location_assignment PIN_LN32 -to SODIMM1_DQ[39] +set_location_assignment PIN_MK21 -to SODIMM1_DQ[40] +set_location_assignment PIN_MD26 -to SODIMM1_DQ[41] +set_location_assignment PIN_MH19 -to SODIMM1_DQ[42] +set_location_assignment PIN_MC21 -to SODIMM1_DQ[43] +set_location_assignment PIN_MC27 -to SODIMM1_DQ[44] +set_location_assignment PIN_MK27 -to SODIMM1_DQ[45] +set_location_assignment PIN_MD19 -to SODIMM1_DQ[46] +set_location_assignment PIN_MH26 -to SODIMM1_DQ[47] +set_location_assignment PIN_LR9 -to SODIMM1_DQ[48] +set_location_assignment PIN_LW9 -to SODIMM1_DQ[49] +set_location_assignment PIN_MA4 -to SODIMM1_DQ[50] +set_location_assignment PIN_LW2 -to SODIMM1_DQ[51] +set_location_assignment PIN_MA11 -to SODIMM1_DQ[52] +set_location_assignment PIN_LN11 -to SODIMM1_DQ[53] +set_location_assignment PIN_MC5 -to SODIMM1_DQ[54] +set_location_assignment PIN_LU4 -to SODIMM1_DQ[55] +set_location_assignment PIN_LN26 -to SODIMM1_DQ[56] +set_location_assignment PIN_MA26 -to SODIMM1_DQ[57] +set_location_assignment PIN_LR29 -to SODIMM1_DQ[58] +set_location_assignment PIN_LN30 -to SODIMM1_DQ[59] +set_location_assignment PIN_LW25 -to SODIMM1_DQ[60] +set_location_assignment PIN_LR25 -to SODIMM1_DQ[61] +set_location_assignment PIN_LW29 -to SODIMM1_DQ[62] +set_location_assignment PIN_MA30 -to SODIMM1_DQ[63] +set_location_assignment PIN_KW27 -to SODIMM1_DQ[64] +set_location_assignment PIN_LH30 -to SODIMM1_DQ[65] +set_location_assignment PIN_LL31 -to SODIMM1_DQ[66] +set_location_assignment PIN_LH26 -to SODIMM1_DQ[67] +set_location_assignment PIN_LB26 -to SODIMM1_DQ[68] +set_location_assignment PIN_LL27 -to SODIMM1_DQ[69] +set_location_assignment PIN_LB30 -to SODIMM1_DQ[70] +set_location_assignment PIN_KW31 -to SODIMM1_DQ[71] +set_location_assignment PIN_LB34 -to SODIMM1_DM_DBI[0] +set_location_assignment PIN_MD30 -to SODIMM1_DM_DBI[1] +set_location_assignment PIN_MD11 -to SODIMM1_DM_DBI[2] +set_location_assignment PIN_LR17 -to SODIMM1_DM_DBI[3] +set_location_assignment PIN_LR33 -to SODIMM1_DM_DBI[4] +set_location_assignment PIN_MD23 -to SODIMM1_DM_DBI[5] +set_location_assignment PIN_LR5 -to SODIMM1_DM_DBI[6] +set_location_assignment PIN_LR27 -to SODIMM1_DM_DBI[7] +set_location_assignment PIN_LB28 -to SODIMM1_DM_DBI[8] +set_location_assignment PIN_KF42 -to SODIMM1_NCS +#set_location_assignment PIN_KF38 -to SODIMM1_NCS[1] +set_location_assignment PIN_KU42 -to SODIMM1_NRST +set_location_assignment PIN_KU40 -to SODIMM1_ODT +#set_location_assignment PIN_KR41 -to SODIMM1_ODT[1] +set_location_assignment PIN_KJ39 -to SODIMM1_PAR +set_location_assignment PIN_KU32 -to SODIMM1_NALERT +set_location_assignment PIN_KJ43 -to SODIMM1_NACT +set_location_assignment PIN_KJ37 -to SODIMM1_OCT_RZQ diff --git a/cards/terasic/a2700/constr/sodimm2.qsf b/cards/terasic/a2700/constr/sodimm2.qsf new file mode 100644 index 000000000..3948b502b --- /dev/null +++ b/cards/terasic/a2700/constr/sodimm2.qsf @@ -0,0 +1,151 @@ +# sodimm2.qsf - DDR4D constraint file +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +#============================================================ +# DDR4D +#============================================================ +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to SODIMM2_REFCLK_P +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM2_REFCLK_P +set_location_assignment PIN_MA44 -to SODIMM2_REFCLK_P +set_location_assignment PIN_KR45 -to SODIMM2_A[0] +set_location_assignment PIN_KU44 -to SODIMM2_A[1] +set_location_assignment PIN_KJ45 -to SODIMM2_A[2] +set_location_assignment PIN_KF44 -to SODIMM2_A[3] +set_location_assignment PIN_KU46 -to SODIMM2_A[4] +set_location_assignment PIN_KR47 -to SODIMM2_A[5] +set_location_assignment PIN_KF46 -to SODIMM2_A[6] +set_location_assignment PIN_KJ47 -to SODIMM2_A[7] +set_location_assignment PIN_KR49 -to SODIMM2_A[8] +set_location_assignment PIN_KU48 -to SODIMM2_A[9] +set_location_assignment PIN_KF48 -to SODIMM2_A[10] +set_location_assignment PIN_KJ49 -to SODIMM2_A[11] +set_location_assignment PIN_LR43 -to SODIMM2_A[12] +set_location_assignment PIN_LW45 -to SODIMM2_A[13] +set_location_assignment PIN_MA46 -to SODIMM2_A[14] +set_location_assignment PIN_LR45 -to SODIMM2_A[15] +set_location_assignment PIN_LN46 -to SODIMM2_A[16] +set_location_assignment PIN_LW47 -to SODIMM2_BA[0] +set_location_assignment PIN_LN48 -to SODIMM2_BA[1] +set_location_assignment PIN_LR47 -to SODIMM2_BG[0] +set_location_assignment PIN_LH44 -to SODIMM2_BG[1] +set_location_assignment PIN_LH48 -to SODIMM2_PCK +#set_location_assignment PIN_LR53 -to SODIMM2_PCK[1] +set_location_assignment PIN_LL49 -to SODIMM2_NCK +#set_location_assignment PIN_LN54 -to SODIMM2_NCK[1] +set_location_assignment PIN_LB46 -to SODIMM2_CKE +#set_location_assignment PIN_KW47 -to SODIMM2_CKE[1] +set_location_assignment PIN_LH52 -to SODIMM2_PDQS[0] +set_location_assignment PIN_MH60 -to SODIMM2_PDQS[1] +set_location_assignment PIN_MH54 -to SODIMM2_PDQS[2] +set_location_assignment PIN_LW57 -to SODIMM2_PDQS[3] +set_location_assignment PIN_MH48 -to SODIMM2_PDQS[4] +set_location_assignment PIN_MH36 -to SODIMM2_PDQS[5] +set_location_assignment PIN_MH42 -to SODIMM2_PDQS[6] +set_location_assignment PIN_LW39 -to SODIMM2_PDQS[7] +set_location_assignment PIN_KU52 -to SODIMM2_PDQS[8] +set_location_assignment PIN_LL53 -to SODIMM2_NDQS[0] +set_location_assignment PIN_MK61 -to SODIMM2_NDQS[1] +set_location_assignment PIN_MK55 -to SODIMM2_NDQS[2] +set_location_assignment PIN_MA58 -to SODIMM2_NDQS[3] +set_location_assignment PIN_MK49 -to SODIMM2_NDQS[4] +set_location_assignment PIN_MK37 -to SODIMM2_NDQS[5] +set_location_assignment PIN_MK43 -to SODIMM2_NDQS[6] +set_location_assignment PIN_MA40 -to SODIMM2_NDQS[7] +set_location_assignment PIN_KR53 -to SODIMM2_NDQS[8] +set_location_assignment PIN_LL55 -to SODIMM2_DQ[0] +set_location_assignment PIN_LB54 -to SODIMM2_DQ[1] +set_location_assignment PIN_LH50 -to SODIMM2_DQ[2] +set_location_assignment PIN_LH54 -to SODIMM2_DQ[3] +set_location_assignment PIN_KW51 -to SODIMM2_DQ[4] +set_location_assignment PIN_LB50 -to SODIMM2_DQ[5] +set_location_assignment PIN_LL51 -to SODIMM2_DQ[6] +set_location_assignment PIN_KW55 -to SODIMM2_DQ[7] +set_location_assignment PIN_MC63 -to SODIMM2_DQ[8] +set_location_assignment PIN_MH62 -to SODIMM2_DQ[9] +set_location_assignment PIN_MK59 -to SODIMM2_DQ[10] +set_location_assignment PIN_MH58 -to SODIMM2_DQ[11] +set_location_assignment PIN_MD62 -to SODIMM2_DQ[12] +set_location_assignment PIN_MC59 -to SODIMM2_DQ[13] +set_location_assignment PIN_MK63 -to SODIMM2_DQ[14] +set_location_assignment PIN_MD58 -to SODIMM2_DQ[15] +set_location_assignment PIN_MD56 -to SODIMM2_DQ[16] +set_location_assignment PIN_MK57 -to SODIMM2_DQ[17] +set_location_assignment PIN_MH52 -to SODIMM2_DQ[18] +set_location_assignment PIN_MD52 -to SODIMM2_DQ[19] +set_location_assignment PIN_MC57 -to SODIMM2_DQ[20] +set_location_assignment PIN_MC53 -to SODIMM2_DQ[21] +set_location_assignment PIN_MK53 -to SODIMM2_DQ[22] +set_location_assignment PIN_MH56 -to SODIMM2_DQ[23] +set_location_assignment PIN_LN60 -to SODIMM2_DQ[24] +set_location_assignment PIN_MA60 -to SODIMM2_DQ[25] +set_location_assignment PIN_LR55 -to SODIMM2_DQ[26] +set_location_assignment PIN_LW55 -to SODIMM2_DQ[27] +set_location_assignment PIN_LN56 -to SODIMM2_DQ[28] +set_location_assignment PIN_LW59 -to SODIMM2_DQ[29] +set_location_assignment PIN_MA56 -to SODIMM2_DQ[30] +set_location_assignment PIN_LR59 -to SODIMM2_DQ[31] +set_location_assignment PIN_MK51 -to SODIMM2_DQ[32] +set_location_assignment PIN_MC47 -to SODIMM2_DQ[33] +set_location_assignment PIN_MD46 -to SODIMM2_DQ[34] +set_location_assignment PIN_MK47 -to SODIMM2_DQ[35] +set_location_assignment PIN_MC51 -to SODIMM2_DQ[36] +set_location_assignment PIN_MH50 -to SODIMM2_DQ[37] +set_location_assignment PIN_MH46 -to SODIMM2_DQ[38] +set_location_assignment PIN_MD50 -to SODIMM2_DQ[39] +set_location_assignment PIN_MH34 -to SODIMM2_DQ[40] +set_location_assignment PIN_MK39 -to SODIMM2_DQ[41] +set_location_assignment PIN_MC35 -to SODIMM2_DQ[42] +set_location_assignment PIN_MD38 -to SODIMM2_DQ[43] +set_location_assignment PIN_MK35 -to SODIMM2_DQ[44] +set_location_assignment PIN_MC39 -to SODIMM2_DQ[45] +set_location_assignment PIN_MD34 -to SODIMM2_DQ[46] +set_location_assignment PIN_MH38 -to SODIMM2_DQ[47] +set_location_assignment PIN_MC45 -to SODIMM2_DQ[48] +set_location_assignment PIN_MK41 -to SODIMM2_DQ[49] +set_location_assignment PIN_MH40 -to SODIMM2_DQ[50] +set_location_assignment PIN_MD40 -to SODIMM2_DQ[51] +set_location_assignment PIN_MH44 -to SODIMM2_DQ[52] +set_location_assignment PIN_MK45 -to SODIMM2_DQ[53] +set_location_assignment PIN_MD44 -to SODIMM2_DQ[54] +set_location_assignment PIN_MC41 -to SODIMM2_DQ[55] +set_location_assignment PIN_LR37 -to SODIMM2_DQ[56] +set_location_assignment PIN_LN42 -to SODIMM2_DQ[57] +set_location_assignment PIN_LN38 -to SODIMM2_DQ[58] +set_location_assignment PIN_LR41 -to SODIMM2_DQ[59] +set_location_assignment PIN_LW37 -to SODIMM2_DQ[60] +set_location_assignment PIN_MA38 -to SODIMM2_DQ[61] +set_location_assignment PIN_LW41 -to SODIMM2_DQ[62] +set_location_assignment PIN_MA42 -to SODIMM2_DQ[63] +set_location_assignment PIN_KR55 -to SODIMM2_DQ[64] +set_location_assignment PIN_KU54 -to SODIMM2_DQ[65] +set_location_assignment PIN_KJ51 -to SODIMM2_DQ[66] +set_location_assignment PIN_KF50 -to SODIMM2_DQ[67] +set_location_assignment PIN_KJ55 -to SODIMM2_DQ[68] +set_location_assignment PIN_KF54 -to SODIMM2_DQ[69] +set_location_assignment PIN_KU50 -to SODIMM2_DQ[70] +set_location_assignment PIN_KR51 -to SODIMM2_DQ[71] +set_location_assignment PIN_LB52 -to SODIMM2_DM_DBI[0] +set_location_assignment PIN_MD60 -to SODIMM2_DM_DBI[1] +set_location_assignment PIN_MD54 -to SODIMM2_DM_DBI[2] +set_location_assignment PIN_LR57 -to SODIMM2_DM_DBI[3] +set_location_assignment PIN_MD48 -to SODIMM2_DM_DBI[4] +set_location_assignment PIN_MD36 -to SODIMM2_DM_DBI[5] +set_location_assignment PIN_MD42 -to SODIMM2_DM_DBI[6] +set_location_assignment PIN_LR39 -to SODIMM2_DM_DBI[7] +set_location_assignment PIN_KF52 -to SODIMM2_DM_DBI[8] +set_location_assignment PIN_LB44 -to SODIMM2_NCS +#set_location_assignment PIN_KW49 -to SODIMM2_NCS[1] +set_location_assignment PIN_LL45 -to SODIMM2_NRST +set_location_assignment PIN_LH46 -to SODIMM2_ODT +#set_location_assignment PIN_LL47 -to SODIMM2_ODT[1] +set_location_assignment PIN_LB48 -to SODIMM2_PAR +set_location_assignment PIN_MA48 -to SODIMM2_NALERT +set_location_assignment PIN_KW45 -to SODIMM2_NACT +set_location_assignment PIN_LN44 -to SODIMM2_OCT_RZQ diff --git a/cards/terasic/a2700/constr/sodimm_hps.qsf b/cards/terasic/a2700/constr/sodimm_hps.qsf new file mode 100644 index 000000000..a170d089b --- /dev/null +++ b/cards/terasic/a2700/constr/sodimm_hps.qsf @@ -0,0 +1,147 @@ +# sodimm_hps.qsf - DDR4A constraint file +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# ============================================================================== +# Pinout and IO Standards +# ============================================================================== + +#============================================================ +# DDR4A +#============================================================ +set_instance_assignment -name IO_STANDARD "True Differential Signaling" -to SODIMM_HPS_REFCLK_P +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to SODIMM_HPS_REFCLK_P + +set_location_assignment PIN_AA31 -to SODIMM_HPS_REFCLK_P +set_location_assignment PIN_N33 -to SODIMM_HPS_A[0] +set_location_assignment PIN_L34 -to SODIMM_HPS_A[1] +set_location_assignment PIN_U33 -to SODIMM_HPS_A[2] +set_location_assignment PIN_W34 -to SODIMM_HPS_A[3] +set_location_assignment PIN_N31 -to SODIMM_HPS_A[4] +set_location_assignment PIN_L32 -to SODIMM_HPS_A[5] +set_location_assignment PIN_U31 -to SODIMM_HPS_A[6] +set_location_assignment PIN_W32 -to SODIMM_HPS_A[7] +set_location_assignment PIN_N29 -to SODIMM_HPS_A[8] +set_location_assignment PIN_L30 -to SODIMM_HPS_A[9] +set_location_assignment PIN_U29 -to SODIMM_HPS_A[10] +set_location_assignment PIN_W30 -to SODIMM_HPS_A[11] +set_location_assignment PIN_AK32 -to SODIMM_HPS_A[12] +set_location_assignment PIN_AA29 -to SODIMM_HPS_A[13] +set_location_assignment PIN_AD30 -to SODIMM_HPS_A[14] +set_location_assignment PIN_AN29 -to SODIMM_HPS_A[15] +set_location_assignment PIN_AK30 -to SODIMM_HPS_A[16] +set_location_assignment PIN_AD28 -to SODIMM_HPS_BA[0] +set_location_assignment PIN_AN27 -to SODIMM_HPS_BA[1] +set_location_assignment PIN_AK28 -to SODIMM_HPS_BG[0] +set_location_assignment PIN_AV37 -to SODIMM_HPS_BG[1] +set_location_assignment PIN_AV33 -to SODIMM_HPS_PCK +set_location_assignment PIN_AT34 -to SODIMM_HPS_NCK +set_location_assignment PIN_BC35 -to SODIMM_HPS_CKE +set_location_assignment PIN_N5 -to SODIMM_HPS_PDQS[0] +set_location_assignment PIN_B13 -to SODIMM_HPS_PDQS[1] +set_location_assignment PIN_B25 -to SODIMM_HPS_PDQS[2] +set_location_assignment PIN_B31 -to SODIMM_HPS_PDQS[3] +set_location_assignment PIN_N37 -to SODIMM_HPS_PDQS[4] +set_location_assignment PIN_AA41 -to SODIMM_HPS_PDQS[5] +set_location_assignment PIN_AV41 -to SODIMM_HPS_PDQS[6] +set_location_assignment PIN_AA35 -to SODIMM_HPS_PDQS[7] +set_location_assignment PIN_AV29 -to SODIMM_HPS_PDQS[8] +set_location_assignment PIN_L7 -to SODIMM_HPS_NDQS[0] +set_location_assignment PIN_D15 -to SODIMM_HPS_NDQS[1] +set_location_assignment PIN_D26 -to SODIMM_HPS_NDQS[2] +set_location_assignment PIN_D32 -to SODIMM_HPS_NDQS[3] +set_location_assignment PIN_L38 -to SODIMM_HPS_NDQS[4] +set_location_assignment PIN_AD42 -to SODIMM_HPS_NDQS[5] +set_location_assignment PIN_AT42 -to SODIMM_HPS_NDQS[6] +set_location_assignment PIN_AD36 -to SODIMM_HPS_NDQS[7] +set_location_assignment PIN_AT30 -to SODIMM_HPS_NDQS[8] +set_location_assignment PIN_W4 -to SODIMM_HPS_DQ[0] +set_location_assignment PIN_L4 -to SODIMM_HPS_DQ[1] +set_location_assignment PIN_U9 -to SODIMM_HPS_DQ[2] +set_location_assignment PIN_W11 -to SODIMM_HPS_DQ[3] +set_location_assignment PIN_U2 -to SODIMM_HPS_DQ[4] +set_location_assignment PIN_N2 -to SODIMM_HPS_DQ[5] +set_location_assignment PIN_N9 -to SODIMM_HPS_DQ[6] +set_location_assignment PIN_L11 -to SODIMM_HPS_DQ[7] +set_location_assignment PIN_H11 -to SODIMM_HPS_DQ[8] +set_location_assignment PIN_D11 -to SODIMM_HPS_DQ[9] +set_location_assignment PIN_B17 -to SODIMM_HPS_DQ[10] +set_location_assignment PIN_H19 -to SODIMM_HPS_DQ[11] +set_location_assignment PIN_H7 -to SODIMM_HPS_DQ[12] +set_location_assignment PIN_J9 -to SODIMM_HPS_DQ[13] +set_location_assignment PIN_D19 -to SODIMM_HPS_DQ[14] +set_location_assignment PIN_J17 -to SODIMM_HPS_DQ[15] +set_location_assignment PIN_B21 -to SODIMM_HPS_DQ[16] +set_location_assignment PIN_D23 -to SODIMM_HPS_DQ[17] +set_location_assignment PIN_D28 -to SODIMM_HPS_DQ[18] +set_location_assignment PIN_B27 -to SODIMM_HPS_DQ[19] +set_location_assignment PIN_J21 -to SODIMM_HPS_DQ[20] +set_location_assignment PIN_H23 -to SODIMM_HPS_DQ[21] +set_location_assignment PIN_H28 -to SODIMM_HPS_DQ[22] +set_location_assignment PIN_J27 -to SODIMM_HPS_DQ[23] +set_location_assignment PIN_B29 -to SODIMM_HPS_DQ[24] +set_location_assignment PIN_D30 -to SODIMM_HPS_DQ[25] +set_location_assignment PIN_J33 -to SODIMM_HPS_DQ[26] +set_location_assignment PIN_D34 -to SODIMM_HPS_DQ[27] +set_location_assignment PIN_H30 -to SODIMM_HPS_DQ[28] +set_location_assignment PIN_J29 -to SODIMM_HPS_DQ[29] +set_location_assignment PIN_B33 -to SODIMM_HPS_DQ[30] +set_location_assignment PIN_H34 -to SODIMM_HPS_DQ[31] +set_location_assignment PIN_N35 -to SODIMM_HPS_DQ[32] +set_location_assignment PIN_L40 -to SODIMM_HPS_DQ[33] +set_location_assignment PIN_U39 -to SODIMM_HPS_DQ[34] +set_location_assignment PIN_W40 -to SODIMM_HPS_DQ[35] +set_location_assignment PIN_U35 -to SODIMM_HPS_DQ[36] +set_location_assignment PIN_W36 -to SODIMM_HPS_DQ[37] +set_location_assignment PIN_N39 -to SODIMM_HPS_DQ[38] +set_location_assignment PIN_L36 -to SODIMM_HPS_DQ[39] +set_location_assignment PIN_AA43 -to SODIMM_HPS_DQ[40] +set_location_assignment PIN_AA39 -to SODIMM_HPS_DQ[41] +set_location_assignment PIN_AK40 -to SODIMM_HPS_DQ[42] +set_location_assignment PIN_AK44 -to SODIMM_HPS_DQ[43] +set_location_assignment PIN_AD40 -to SODIMM_HPS_DQ[44] +set_location_assignment PIN_AN39 -to SODIMM_HPS_DQ[45] +set_location_assignment PIN_AN43 -to SODIMM_HPS_DQ[46] +set_location_assignment PIN_AD44 -to SODIMM_HPS_DQ[47] +set_location_assignment PIN_AV43 -to SODIMM_HPS_DQ[48] +set_location_assignment PIN_AT44 -to SODIMM_HPS_DQ[49] +set_location_assignment PIN_BC39 -to SODIMM_HPS_DQ[50] +set_location_assignment PIN_BC43 -to SODIMM_HPS_DQ[51] +set_location_assignment PIN_AV39 -to SODIMM_HPS_DQ[52] +set_location_assignment PIN_AT40 -to SODIMM_HPS_DQ[53] +set_location_assignment PIN_BF40 -to SODIMM_HPS_DQ[54] +set_location_assignment PIN_BF44 -to SODIMM_HPS_DQ[55] +set_location_assignment PIN_AD34 -to SODIMM_HPS_DQ[56] +set_location_assignment PIN_AA37 -to SODIMM_HPS_DQ[57] +set_location_assignment PIN_AN33 -to SODIMM_HPS_DQ[58] +set_location_assignment PIN_AK34 -to SODIMM_HPS_DQ[59] +set_location_assignment PIN_AD38 -to SODIMM_HPS_DQ[60] +set_location_assignment PIN_AN37 -to SODIMM_HPS_DQ[61] +set_location_assignment PIN_AA33 -to SODIMM_HPS_DQ[62] +set_location_assignment PIN_AK38 -to SODIMM_HPS_DQ[63] +set_location_assignment PIN_BF28 -to SODIMM_HPS_DQ[64] +set_location_assignment PIN_BF32 -to SODIMM_HPS_DQ[65] +set_location_assignment PIN_AT32 -to SODIMM_HPS_DQ[66] +set_location_assignment PIN_AT28 -to SODIMM_HPS_DQ[67] +set_location_assignment PIN_BC31 -to SODIMM_HPS_DQ[68] +set_location_assignment PIN_AV31 -to SODIMM_HPS_DQ[69] +set_location_assignment PIN_BC27 -to SODIMM_HPS_DQ[70] +set_location_assignment PIN_AV27 -to SODIMM_HPS_DQ[71] +set_location_assignment PIN_U5 -to SODIMM_HPS_DM_DBI[0] +set_location_assignment PIN_J13 -to SODIMM_HPS_DM_DBI[1] +set_location_assignment PIN_J25 -to SODIMM_HPS_DM_DBI[2] +set_location_assignment PIN_J31 -to SODIMM_HPS_DM_DBI[3] +set_location_assignment PIN_U37 -to SODIMM_HPS_DM_DBI[4] +set_location_assignment PIN_AN41 -to SODIMM_HPS_DM_DBI[5] +set_location_assignment PIN_BC41 -to SODIMM_HPS_DM_DBI[6] +set_location_assignment PIN_AN35 -to SODIMM_HPS_DM_DBI[7] +set_location_assignment PIN_BC29 -to SODIMM_HPS_DM_DBI[8] +set_location_assignment PIN_BC37 -to SODIMM_HPS_NCS +set_location_assignment PIN_AT38 -to SODIMM_HPS_NRST +set_location_assignment PIN_AV35 -to SODIMM_HPS_ODT +set_location_assignment PIN_BF34 -to SODIMM_HPS_PAR +set_location_assignment PIN_AA27 -to SODIMM_HPS_NALERT +set_location_assignment PIN_BF38 -to SODIMM_HPS_NACT +set_location_assignment PIN_AN31 -to SODIMM_HPS_OCT_RZQ diff --git a/cards/terasic/a2700/constr/timing.sdc b/cards/terasic/a2700/constr/timing.sdc new file mode 100644 index 000000000..d735d9f97 --- /dev/null +++ b/cards/terasic/a2700/constr/timing.sdc @@ -0,0 +1,44 @@ +# timing.sdc: Timing constraints +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +derive_clock_uncertainty + +create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }] + +create_clock -name {AG_SYSCLK0} -period 10.000 [get_ports { AG_SYSCLK0_P }] +# create_clock -name {AG_SYSCLK1} -period 10.000 [get_ports { AG_SYSCLK1_P }] +create_clock -name {AG_SYSCLK1} -period 20.000 [get_ports { AG_SYSCLK1_P }] + +create_clock -name {PCIE_CLK0} -period 10.000 [get_ports { PCIE_CLK0_P }] +create_clock -name {PCIE_CLK1} -period 10.000 [get_ports { PCIE_CLK1_P }] +create_clock -name {QSFP_REFCLK0} -period 6.400 [get_ports { QSFP_REFCLK0_P }] + +# Cut (set_false_path) this JTAG clock from all other clocks in the design +set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] + +# DDR4A +create_clock -period 30 [get_ports SODIMM_HPS_REFCLK_P] +# DDR4B +create_clock -period 30 [get_ports SODIMM0_REFCLK_P] +# DDR4C +create_clock -period 30 [get_ports SODIMM1_REFCLK_P] +# DDR4D +create_clock -period 30 [get_ports SODIMM0_REFCLK_P] + + +# =========== +# Global clks +# =========== +set MI_CLK_CH3 [get_clocks ag_i|clk_gen_i|iopll_i|iopll_0_outclk3] + + +# ============ +# 400G1 design +# ============ +set FHIP_400G1_CLK_CH23 [get_clocks ag_i|network_mod_i|eth_core_g[0].network_mod_core_i|ftile_1x400g8_g.eth_ip_g[0].FTILE_1x400g8_i|ftile_eth_ip_i|eth_f_0|tx_clkout|ch23] + +# Fix hold timing issues for 400G1 design +set_clock_groups -asynchronous -group $MI_CLK_CH3 -group $FHIP_400G1_CLK_CH23 diff --git a/cards/terasic/a2700/readme.rst b/cards/terasic/a2700/readme.rst new file mode 100644 index 000000000..38ba76aae --- /dev/null +++ b/cards/terasic/a2700/readme.rst @@ -0,0 +1,66 @@ +.. _card_terasic-a2700: + +Terasic A2700 +---------------- + +- Card information: + - Vendor: Terasic + - Name: Mercury A2700 Accelerator Card + - Ethernet ports: 2x QSFP-DD + - 400G + - up to 200G (200/100/40/25/10) - Unsupported + - PCIe conectors: Edge connector + - `FPGA Card Website `_ +- FPGA specification: + - FPGA part number: ``AGIB027R29A1E2VB`` + - Ethernet Hard IP: F-Tile (up to 400G Ethernet) + - PCIe Hard IP: R-Tile (up to PCIe Gen5 x16) + - Four DDR4 SO-DIMM Socket + - One shared with HPS + +NDK firmware support +^^^^^^^^^^^^^^^^^^^^ + +- Ethernet cores that are supported in the NDK firmware: + - :ref:`F-Tile in the Network Module ` +- PCIe cores that are supported in the NDK firmware: + - :ref:`R-Tile in the PCIe Module ` +- Makefile targets for building the NDK firmware (valid for NDK-APP-Minimal, may vary for other apps): + - Use ``make 400g1`` command for firmware with 1x400GE (default). +- Support for booting the NDK firmware using the nfb-boot tool: + - TODO + +.. note:: + + To build the NDK firmware for this card, you must have the Intel Quartus Prime Pro installed, including a valid license. + Design requires enabled bifurcation (x8x8) on target machine + +Boot instructions (initial) +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Supported boot is handled by the Secure Device Manager (SDM), which has its own 1Gb flash to store Factory and User defined image. +To enable this method, it is necessary to set the switches on the board as follows: +- Ensure that the MSEL[2:0] switch on the board is set to 'Active Serial Normal' mode - MSEL[2:0] = 3'b011 + - Set SW4 to 2'b01 and SW5 to 2'b10. + - The SW4(1) set to 0 to load user image or to 1 to load factory image after power up. +- For more detailed description refer to `Mercury A2700 User Manual `_ + +Before you can use the nfb-boot tool, you must write the initial NDK firmware to flash memory using a regular JTAG programmer. +It is possible to use Micro-USB port marked as 'USB/UART' on the Terasic card for this purpose. + +- Build your application calling ``make`` in the build folder with 'Makefile'. +- After the NDK firmware build is complete, you will have a bitstream file called ``my_bitstream.sof``. +- Use the ``NDK-APP_root_directory/ndk_fpga/cards/terasic/a2700/scripts/generate_jic.sh my_bitstream.sof my_bitstream.sof`` command to convert the two bitstream files to .jic format for flash memory. + - This creates a flash image and sets address spaces in the flash to hold the factory and user images. +- On the host PC where the card is connected, write the .jic bitstream to the flash memory with the command `` +# +# SPDX-License-Identifier: BSD-3-Clause + +if [ $# != 2 ] ; then + echo "Usage:" + echo "------" + echo " sh generate_jic.sh " + echo " " + echo "Example:" + echo " sh generate_jic.sh factory.sof application.sof" + exit +fi + +my_folder=$(pwd) +file=$1 +file2=$2 +filename="initial_image" +extension=${file##*.} +extension2=${file2##*.} + +if [ $extension != "sof" -o $extension2 != "sof" ] ; then + echo "Usage:" + echo "------" + echo " sh generate_jic.sh " + exit +fi + +if [ $extension == "sof" -a $extension2 == "sof" ] ; then + touch ${filename}".pfg" + echo " + + + + + + + + Flash_Device_1 + + + + + $file + + + $file2 + + + + + + + + + + + + + AGIB027R29AR0 + + + + Bitstream_1 + + + Bitstream_2 + + + " > ${filename}".pfg" + + echo "Converting to JIC File." + quartus_pfg -c ${filename}.pfg + rm ${filename}.pfg + echo "JIC file generated successfully!" +fi diff --git a/cards/terasic/a2700/scripts/write_jic.sh b/cards/terasic/a2700/scripts/write_jic.sh new file mode 100644 index 000000000..2ce2d0c0a --- /dev/null +++ b/cards/terasic/a2700/scripts/write_jic.sh @@ -0,0 +1,53 @@ +#!/bin/bash +# +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# configuration +cable_index=1 # use jtagconfig command for check cable index + +if [ $# != 1 ] ; then + echo "Usage:" + echo "------" + echo " sh write_jic.sh " + echo " " + echo "Example:" + echo " sh write_jic.sh my_firmware.jic" + exit +fi + +file=$1 +filename=${file%.*} +extension=${file##*.} + +if [ $extension != "jic" ] ; then + echo "Only .jic file is allowed!" + exit +fi + +if [ $extension == "jic" ] ; then + touch ${filename}".cdf" + echo "/* Quartus Prime Version 24.2.0 Build 174 03/30/2022 SC Pro Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(AGIB027R29AR0) File(\"$file\") MfrSpec(OpMask(1) SEC_Device(MT25QU01G) Child_OpMask(1 1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd;" > ${filename}".cdf" + + # Set JTAG frequency + jtagconfig --setparam ${cable_index} JtagClock 16M + # Write .jic file to FPGA + quartus_pgm -c ${cable_index} ${filename}.cdf + # Clean + rm ${filename}.cdf + echo "Done." +fi diff --git a/cards/terasic/a2700/src/Modules.tcl b/cards/terasic/a2700/src/Modules.tcl new file mode 100644 index 000000000..8b08ebf7f --- /dev/null +++ b/cards/terasic/a2700/src/Modules.tcl @@ -0,0 +1,57 @@ +# Modules.tcl: script to compile Terasic A2700 +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# converting input list to associative array +array set ARCHGRP_ARR $ARCHGRP + +# Paths +set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top" +set BOOT_CTRL_BASE "$OFM_PATH/core/comp/misc/boot_ctrl" + +# Components +lappend COMPONENTS [list "FPGA_COMMON" $FPGA_COMMON_BASE $ARCHGRP] +lappend COMPONENTS [list "BOOT_CTRL" $BOOT_CTRL_BASE "FULL"] + +# IP components +set IP_COMMON_TCL $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/common.tcl +source $IP_COMMON_TCL + +set ARCHGRP_ARR(IP_COMMON_TCL) $IP_COMMON_TCL +set ARCHGRP_ARR(IP_TEMPLATE_BASE) $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/intel +set ARCHGRP_ARR(IP_MODIFY_BASE) $ENTITY_BASE/ip +set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex" +set ARCHGRP_ARR(IP_DEVICE) $ARCHGRP_ARR(FPGA) + +set PCIE_CONF [dict create 0 "1x16" 1 "2x8"] +set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" + +set ETH_CONF [dict create 400 "1x400g"] +set FTILE_ETH_IP_NAME "ftile_eth_1x400g" + +# see '$ARCHGRP_ARR(CORE_BASE)/src/ip/common.tcl' for more information regarding the fields +# script_path script_name ip_comp_name type modify +lappend IP_COMPONENTS [list "clk" "ftile_pll" "ftile_pll" 0 1] +# For 100 MHz sysclk use TYPE = 0 +# For 50 MHz sysclk use TYPE = 1 +lappend IP_COMPONENTS [list "clk" "iopll" "iopll_ip" 1 1] +lappend IP_COMPONENTS [list "mem" "ddr4_calibration" "sodimm_cal" 1 1] +lappend IP_COMPONENTS [list "mem" "onboard_ddr4" "sodimm" 0 1] +lappend IP_COMPONENTS [list "mem" "onboard_ddr4" "sodimm_hps" 1 1] +lappend IP_COMPONENTS [list "misc" "mailbox_client" "mailbox_client_ip" 0 0] +lappend IP_COMPONENTS [list "misc" "reset_release" "reset_release_ip" 0 0] +lappend IP_COMPONENTS [list "pcie" "rtile_pcie" $RTILE_PCIE_IP_NAME 0 1] +lappend IP_COMPONENTS [list "eth" "ftile_eth" $FTILE_ETH_IP_NAME 0 1] + + + +if {$ARCHGRP_ARR(VIRTUAL_DEBUG_ENABLE)} { + lappend IP_COMPONENTS [list "misc" "jtag_op" "jtag_op_ip" 0 0] +} + +lappend MOD {*}[get_ip_mod_files $IP_COMPONENTS [array get ARCHGRP_ARR]] + +# Top-level +lappend MOD "$ENTITY_BASE/fpga.vhd" diff --git a/cards/terasic/a2700/src/Quartus.inc.tcl b/cards/terasic/a2700/src/Quartus.inc.tcl new file mode 100644 index 000000000..66d68e4e2 --- /dev/null +++ b/cards/terasic/a2700/src/Quartus.inc.tcl @@ -0,0 +1,65 @@ +# Quartus.inc.tcl: Quartus.tcl include for Terasic A2700 +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# NDK constants (populates all NDK variables from env) +source $env(CORE_BASE)/config/core_bootstrap.tcl + +# Include card common script +source $CORE_BASE/Quartus.inc.tcl + +# Propagating card constants to the Modules.tcl files of the underlying components. +# The description of usage of this array is provided in the Parametrization section +# of the NDK-CORE repository. +set CARD_ARCHGRP(CORE_BASE) $CORE_BASE +set CARD_ARCHGRP(IP_BUILD_DIR) $CARD_BASE/src/ip +set CARD_ARCHGRP(NET_MOD_ARCH) $NET_MOD_ARCH +set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE +# Second dimension because of addition of an element of another array, just for clarity. +set CARD_ARCHGRP(ETH_PORT_SPEED,0) $ETH_PORT_SPEED(0) +set CARD_ARCHGRP(ETH_PORT_CHAN,0) $ETH_PORT_CHAN(0) +set CARD_ARCHGRP(EHIP_PORT_TYPE,0) $EHIP_PORT_TYPE(0) + +set CARD_FPGA "AGIB027R29A1E2VB" +set CARD_ARCHGRP(FPGA) $CARD_FPGA + +# make lists from associative arrays +set CARD_ARCHGRP_L [array get CARD_ARCHGRP] +set CORE_ARCHGRP_L [array get CORE_ARCHGRP] + +# concatenate lists to be handed as a part of the ARCHGRP to the TOPLEVEL +set ARCHGRP_ALL [concat $CARD_ARCHGRP_L $CORE_ARCHGRP_L] + +# Main component +lappend HIERARCHY(COMPONENTS) \ + [list "TOPLEVEL" $CARD_BASE/src $ARCHGRP_ALL] + +# Design parameters +set SYNTH_FLAGS(MODULE) "FPGA" +set SYNTH_FLAGS(FPGA) $CARD_FPGA +set SYNTH_FLAGS(BITSTREAM) "RPD_ASX4" +# Enable Quartus Support-Logic Generation stage +set SYNTH_FLAGS(QUARTUS_TLG) 1 +# Enable automatic clear old IP files before IP Generation +set SYNTH_FLAGS(IP_FILES_CLEAN_ENABLE) 1 + +# QSF constraints for specific parts of the design +set SYNTH_FLAGS(CONSTR) "" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/timing.sdc" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/device.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/general.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/sodimm_hps.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/sodimm0.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/sodimm1.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/sodimm2.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/pcie.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/qsfp_misc.qsf" +set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/qsfp_200G.qsf" + +if {$NET_MOD_ARCH == "F_TILE"} { + set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/qsfp.qsf" +} else { + set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/qsfp_virtual.qsf" +} diff --git a/cards/terasic/a2700/src/card.mk b/cards/terasic/a2700/src/card.mk new file mode 100644 index 000000000..96815ec23 --- /dev/null +++ b/cards/terasic/a2700/src/card.mk @@ -0,0 +1,42 @@ +# card.mk: Makefile include for Terasic A2700 +# Copyright (C) 2024 BrnoLogic, Ltd. +# Author(s): David Beneš +# +# SPDX-License-Identifier: BSD-3-Clause + +# Optional parameters (can be changed in user Makefile) +############################################################################### + +# Name for output files (rootname) +# This value is set as default in SYNTH_FLAGS(OUTPUT) +OUTPUT_NAME ?= a2700-400g + +USER_ENV ?= + +# Private parameters (do not change these values in user Makefile) +############################################################################### + +# Get directory of this Makefile.inc +CARD_BASE_LOCAL := $(dir $(lastword $(MAKEFILE_LIST))) +CARD_BASE ?= $(CARD_BASE_LOCAL)/.. +CORE_BASE ?= $(COMBO_BASE)/core + +#Load correct paths to build system +include $(CORE_BASE)/ndk_paths.mk + +NETCOPE_ENV = \ + OFM_PATH=$(OFM_PATH)\ + COMBO_BASE=$(COMBO_BASE)\ + FIRMWARE_BASE=$(FIRMWARE_BASE)\ + CARD_BASE=$(CARD_BASE) \ + CORE_BASE=$(CORE_BASE) \ + APP_CONF=$(APP_CONF) \ + OUTPUT_NAME=$(OUTPUT_NAME) \ + ETH_PORT_SPEED=$(ETH_PORT_SPEED) \ + ETH_PORT_CHAN=$(ETH_PORT_CHAN) \ + EHIP_PORT_TYPE=$(EHIP_PORT_TYPE) \ + DMA_TYPE=$(DMA_TYPE) \ + $(USER_ENV) + +include $(CORE_BASE)/core.mk +include $(OFM_PATH)/build/Makefile.Quartus.inc diff --git a/cards/terasic/a2700/src/fpga.vhd b/cards/terasic/a2700/src/fpga.vhd new file mode 100644 index 000000000..25fa1f690 --- /dev/null +++ b/cards/terasic/a2700/src/fpga.vhd @@ -0,0 +1,800 @@ +-- fpga.vhd: Terasic A2700 card top-level entity and architecture +-- Copyright (C) 2024 BrnoLogic, Ltd. +-- Author(s): David Beneš +-- +-- SPDX-License-Identifier: BSD-3-Clause + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.combo_const.all; +use work.combo_user_const.all; + +use work.math_pack.all; +use work.type_pack.all; +use work.dma_bus_pack.all; + +-- Note: Boot is currently handled by the SDM +entity FPGA is +port ( + + -- ========================================================================= + -- GENERAL CLOCKS AND PLL STATUS SIGNALS + -- ========================================================================= + -- External differential clocks (programmable via Ext. PLL) + AG_SYSCLK0_P : in std_logic; -- N/A MHz + -- SI5397A Oscillator - 50 MHz + AG_SYSCLK1_P : in std_logic; + + -- Warning! There are 100 MHz clocks available which cannot be used at the + -- moment because of a bug in Quartus 24.1 and 24.2 which makes it impossible + -- to implement the EMIF IP core if there is a clock instantiated in the same + -- I/O bank. (PIN_LB60) + + -- If you decide to use 100 MHz clock, be sure to regenerate the iopll IP core + -- for the new frequency + + -- It is possible to use 100 MHz clock if there is no EMIF IP core or Quartus + -- will instantiate itself (without .qsf constraint). + + -- ========================================================================= + -- PCIE INTERFACE + -- ========================================================================= + PCIE_CLK0_P : in std_logic; + PCIE_CLK1_P : in std_logic; + PCIE_PERST_N : in std_logic; + PCIE_RX_P : in std_logic_vector(15 downto 0); + PCIE_RX_N : in std_logic_vector(15 downto 0); + PCIE_TX_P : out std_logic_vector(15 downto 0); + PCIE_TX_N : out std_logic_vector(15 downto 0); + -- ========================================================================= + -- QSFP-DD INTERFACES - F-TILE + -- ========================================================================= + QSFP_I2C_SCL : inout std_logic; + QSFP_I2C_SDA : inout std_logic; + QSFP_MODSEL_N : out std_logic; + QSFP_INITMODE : out std_logic; + QSFP_RST_N : out std_logic; + QSFP_MODPRS_N : in std_logic; + QSFP_INT_N : in std_logic; + QSFP_REFCLK0_P : in std_logic; + QSFP_RX_P : in std_logic_vector(7 downto 0); + QSFP_RX_N : in std_logic_vector(7 downto 0); + QSFP_TX_P : out std_logic_vector(7 downto 0); + QSFP_TX_N : out std_logic_vector(7 downto 0); + -- ========================================================================= + -- SI5397A - External Clock Generator (QSFP & SYSCLK) + -- ========================================================================= + SI5397A_I2C_SCL : inout std_logic; + SI5397A_I2C_SDA : inout std_logic; + SI5397A_OE_n : out std_logic; + SI5397A_RST_n : out std_logic; + -- ========================================================================= + -- HPS (HARD PROCESSOR SYSTEM) INTERFACE - Available but not supported + -- ========================================================================= + -- ========================================================================= + -- SODIMM INTERFACES + -- ========================================================================= + -- SODIMM_REFCLK_P : DDR4 B port Reference Clock_p - 33.333 MHz (Si540) + -- SODIMM_OCT_RZQ : Calibrated pins for OCT block + -- SODIMM_PCK : Clock p + -- SODIMM_NCK : Clock n + -- SODIMM_A : Address + -- SODIMM_NACT : Activation Command Input n + -- SODIMM_BA : Bank Select + -- SODIMM_BG : Bank Group Select + -- SODIMM_CKE : Clock Enable pin + -- SODIMM_NCS : Chip Select n + -- SODIMM_ODT : On Die Termination + -- SODIMM_NRST : Chip Reset n + -- SODIMM_PAR : Command and Address Parity Input + -- SODIMM_NALERT : Register Alert n + -- SODIMM_PDQS : Data Strobe p + -- SODIMM_NDQS : Data strobe n + -- SODIMM_DM_DBI : Data Bus inversion n + -- SODIMM_DQ : Data + + -- Note that there are more pins available, but calibration will fail if + -- there is not enough DDR memory. These pins are available in the .qsf file + + SODIMM_HPS_REFCLK_P : in std_logic; + SODIMM_HPS_OCT_RZQ : in std_logic; + SODIMM_HPS_PCK : out std_logic; + SODIMM_HPS_NCK : out std_logic; + SODIMM_HPS_A : out std_logic_vector(17-1 downto 0); + SODIMM_HPS_NACT : out std_logic; + SODIMM_HPS_BA : out std_logic_vector(2-1 downto 0); + SODIMM_HPS_BG : out std_logic_vector(2-1 downto 0); + SODIMM_HPS_CKE : out std_logic; + SODIMM_HPS_NCS : out std_logic; + SODIMM_HPS_ODT : out std_logic; + SODIMM_HPS_NRST : out std_logic; + SODIMM_HPS_PAR : out std_logic; + SODIMM_HPS_NALERT : in std_logic; + SODIMM_HPS_PDQS : inout std_logic_vector(9-1 downto 0); + SODIMM_HPS_NDQS : inout std_logic_vector(9-1 downto 0); + SODIMM_HPS_DM_DBI : inout std_logic_vector(9-1 downto 0); + SODIMM_HPS_DQ : inout std_logic_vector(72-1 downto 0); + + SODIMM0_REFCLK_P : in std_logic; + SODIMM0_OCT_RZQ : in std_logic; + SODIMM0_PCK : out std_logic; + SODIMM0_NCK : out std_logic; + SODIMM0_A : out std_logic_vector(17-1 downto 0); + SODIMM0_NACT : out std_logic; + SODIMM0_BA : out std_logic_vector(2-1 downto 0); + SODIMM0_BG : out std_logic_vector(2-1 downto 0); + SODIMM0_CKE : out std_logic; + SODIMM0_NCS : out std_logic; + SODIMM0_ODT : out std_logic; + SODIMM0_NRST : out std_logic; + SODIMM0_PAR : out std_logic; + SODIMM0_NALERT : in std_logic; + SODIMM0_PDQS : inout std_logic_vector(9-1 downto 0); + SODIMM0_NDQS : inout std_logic_vector(9-1 downto 0); + SODIMM0_DM_DBI : inout std_logic_vector(9-1 downto 0); + SODIMM0_DQ : inout std_logic_vector(72-1 downto 0); + + SODIMM1_REFCLK_P : in std_logic; + SODIMM1_OCT_RZQ : in std_logic; + SODIMM1_PCK : out std_logic; + SODIMM1_NCK : out std_logic; + SODIMM1_A : out std_logic_vector(17-1 downto 0); + SODIMM1_NACT : out std_logic; + SODIMM1_BA : out std_logic_vector(2-1 downto 0); + SODIMM1_BG : out std_logic_vector(2-1 downto 0); + SODIMM1_CKE : out std_logic; + SODIMM1_NCS : out std_logic; + SODIMM1_ODT : out std_logic; + SODIMM1_NRST : out std_logic; + SODIMM1_PAR : out std_logic; + SODIMM1_NALERT : in std_logic; + SODIMM1_PDQS : inout std_logic_vector(9-1 downto 0); + SODIMM1_NDQS : inout std_logic_vector(9-1 downto 0); + SODIMM1_DM_DBI : inout std_logic_vector(9-1 downto 0); + SODIMM1_DQ : inout std_logic_vector(72-1 downto 0); + + SODIMM2_REFCLK_P : in std_logic; + SODIMM2_OCT_RZQ : in std_logic; + SODIMM2_PCK : out std_logic; + SODIMM2_NCK : out std_logic; + SODIMM2_A : out std_logic_vector(17-1 downto 0); + SODIMM2_NACT : out std_logic; + SODIMM2_BA : out std_logic_vector(2-1 downto 0); + SODIMM2_BG : out std_logic_vector(2-1 downto 0); + SODIMM2_CKE : out std_logic; + SODIMM2_NCS : out std_logic; + SODIMM2_ODT : out std_logic; + SODIMM2_NRST : out std_logic; + SODIMM2_PAR : out std_logic; + SODIMM2_NALERT : in std_logic; + SODIMM2_PDQS : inout std_logic_vector(9-1 downto 0); + SODIMM2_NDQS : inout std_logic_vector(9-1 downto 0); + SODIMM2_DM_DBI : inout std_logic_vector(9-1 downto 0); + SODIMM2_DQ : inout std_logic_vector(72-1 downto 0) + +); +end entity; + +architecture FULL of FPGA is + -- This IP enable usage of HPS reserved SODIMM in the FPGA logic + component sodimm_hps is + port ( + local_reset_req : in std_logic := 'X'; -- local_reset_req + local_reset_done : out std_logic; -- local_reset_done + pll_ref_clk : in std_logic := 'X'; -- clk + oct_rzqin : in std_logic := 'X'; -- oct_rzqin + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_a : out std_logic_vector(16 downto 0); -- mem_a + mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n + mem_ba : out std_logic_vector(1 downto 0); -- mem_ba + mem_bg : out std_logic_vector(1 downto 0); -- mem_bg + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n + mem_par : out std_logic_vector(0 downto 0); -- mem_par + mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n + mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n + mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq + mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + emif_usr_reset_n : out std_logic; -- reset_n + emif_usr_clk : out std_logic; -- clk + amm_ready_0 : out std_logic; -- waitrequest_n + amm_read_0 : in std_logic := 'X'; -- read + amm_write_0 : in std_logic := 'X'; -- write + amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address + amm_readdata_0 : out std_logic_vector(511 downto 0); -- readdata + amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata + amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount + amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable + amm_readdatavalid_0 : out std_logic; -- readdatavalid + calbus_read : in std_logic := 'X'; -- calbus_read + calbus_write : in std_logic := 'X'; -- calbus_write + calbus_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- calbus_address + calbus_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_wdata + calbus_rdata : out std_logic_vector(31 downto 0); -- calbus_rdata + calbus_seq_param_tbl : out std_logic_vector(4095 downto 0); -- calbus_seq_param_tbl + calbus_clk : in std_logic := 'X'; -- clk + + ctrl_ecc_user_interrupt_0 : out std_logic -- ctrl_ecc_user_interrupt + + ); + end component sodimm_hps; + + -- Regular EMIF IP + component sodimm is + port ( + local_reset_req : in std_logic := 'X'; -- local_reset_req + local_reset_done : out std_logic; -- local_reset_done + pll_ref_clk : in std_logic := 'X'; -- clk + oct_rzqin : in std_logic := 'X'; -- oct_rzqin + mem_ck : out std_logic_vector(0 downto 0); -- mem_ck + mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n + mem_a : out std_logic_vector(16 downto 0); -- mem_a + mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n + mem_ba : out std_logic_vector(1 downto 0); -- mem_ba + mem_bg : out std_logic_vector(1 downto 0); -- mem_bg + mem_cke : out std_logic_vector(0 downto 0); -- mem_cke + mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n + mem_odt : out std_logic_vector(0 downto 0); -- mem_odt + mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n + mem_par : out std_logic_vector(0 downto 0); -- mem_par + mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n + mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs + mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n + mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq + mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n + local_cal_success : out std_logic; -- local_cal_success + local_cal_fail : out std_logic; -- local_cal_fail + calbus_read : in std_logic := 'X'; -- calbus_read + calbus_write : in std_logic := 'X'; -- calbus_write + calbus_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- calbus_address + calbus_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_wdata + calbus_rdata : out std_logic_vector(31 downto 0); -- calbus_rdata + calbus_seq_param_tbl : out std_logic_vector(4095 downto 0); -- calbus_seq_param_tbl + calbus_clk : in std_logic := 'X'; -- clk + emif_usr_reset_n : out std_logic; -- reset_n + emif_usr_clk : out std_logic; -- clk + ctrl_ecc_user_interrupt_0 : out std_logic; -- ctrl_ecc_user_interrupt + amm_ready_0 : out std_logic; -- waitrequest_n + amm_read_0 : in std_logic := 'X'; -- read + amm_write_0 : in std_logic := 'X'; -- write + amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address + amm_readdata_0 : out std_logic_vector(511 downto 0); -- readdata + amm_writedata_0 : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata + amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount + amm_byteenable_0 : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable + amm_readdatavalid_0 : out std_logic -- readdatavalid + ); + end component sodimm; + + -- Each calibration IP can handle two emif controllers (due to the EMIF hard IP placement) + component sodimm_cal is + port ( + calbus_read_0 : out std_logic; -- calbus_read + calbus_write_0 : out std_logic; -- calbus_write + calbus_address_0 : out std_logic_vector(19 downto 0); -- calbus_address + calbus_wdata_0 : out std_logic_vector(31 downto 0); -- calbus_wdata + calbus_rdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_rdata + calbus_seq_param_tbl_0 : in std_logic_vector(4095 downto 0) := (others => 'X'); -- calbus_seq_param_tbl + calbus_read_1 : out std_logic; -- calbus_read + calbus_write_1 : out std_logic; -- calbus_write + calbus_address_1 : out std_logic_vector(19 downto 0); -- calbus_address + calbus_wdata_1 : out std_logic_vector(31 downto 0); -- calbus_wdata + calbus_rdata_1 : in std_logic_vector(31 downto 0) := (others => 'X'); -- calbus_rdata + calbus_seq_param_tbl_1 : in std_logic_vector(4095 downto 0) := (others => 'X'); -- calbus_seq_param_tbl; + calbus_clk : out std_logic -- clk + ); + end component sodimm_cal; + + function f_dma_endpoints(PCIE_ENDPOINTS : natural; PCIE_EP_MODE : natural; PCIE_GEN : natural) return natural is + variable dma_ep_v : natural; + begin + dma_ep_v := PCIE_ENDPOINTS; + if (PCIE_EP_MODE = 0) then + dma_ep_v := 2*dma_ep_v; + end if; + if (PCIE_GEN = 5) then + dma_ep_v := 2*dma_ep_v; + end if; + return dma_ep_v; + end function; + + constant PCIE_LANES : integer := 16; + constant PCIE_CLKS : integer := 2; + constant PCIE_CONS : integer := 1; + constant MISC_IN_WIDTH : integer := 64; + constant MISC_OUT_WIDTH : integer := 64 + 5; + constant ETH_LANES : integer := 8; + constant DMA_ENDPOINTS : integer := f_dma_endpoints(PCIE_ENDPOINTS,PCIE_ENDPOINT_MODE,PCIE_GEN); + constant MEM_PORTS : integer := DDR4_PORTS; + constant MEM_ADDR_WIDTH : integer := 27; + constant MEM_DATA_WIDTH : integer := 512; + constant MEM_BURST_WIDTH : integer := 7; + constant AMM_FREQ_KHZ : integer := 333333; + constant DEVICE : string := "AGILEX"; + + signal calbus_read : std_logic_vector(MEM_PORTS-1 downto 0); + signal calbus_write : std_logic_vector(MEM_PORTS-1 downto 0); + signal calbus_address : slv_array_t(MEM_PORTS-1 downto 0)(19 downto 0); + signal calbus_wdata : slv_array_t(MEM_PORTS-1 downto 0)(31 downto 0); + signal calbus_rdata : slv_array_t(MEM_PORTS-1 downto 0)(31 downto 0); + signal calbus_seq_param_tbl : slv_array_t(MEM_PORTS-1 downto 0)(4095 downto 0); + signal calbus_clk : std_logic_vector(MEM_PORTS-1 downto 0); + + signal mem_clk : std_logic_vector(MEM_PORTS-1 downto 0); + signal mem_rst : std_logic_vector(MEM_PORTS-1 downto 0); + signal mem_rst_n : std_logic_vector(MEM_PORTS-1 downto 0); + signal mem_rst_n_reg : std_logic_vector(MEM_PORTS-1 downto 0); + + signal mem_avmm_ready : std_logic_vector(MEM_PORTS-1 downto 0); + signal mem_avmm_read : std_logic_vector(MEM_PORTS-1 downto 0); + signal mem_avmm_write : std_logic_vector(MEM_PORTS-1 downto 0); + signal mem_avmm_address : slv_array_t(MEM_PORTS-1 downto 0)(MEM_ADDR_WIDTH-1 downto 0); + signal mem_avmm_burstcount : slv_array_t(MEM_PORTS-1 downto 0)(MEM_BURST_WIDTH-1 downto 0); + signal mem_avmm_writedata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0); + signal mem_avmm_readdata : slv_array_t(MEM_PORTS-1 downto 0)(MEM_DATA_WIDTH-1 downto 0); + signal mem_avmm_readdatavalid : std_logic_vector(MEM_PORTS-1 downto 0); + + signal emif_rst_req : std_logic_vector(MEM_PORTS-1 downto 0); + signal emif_rst_done : std_logic_vector(MEM_PORTS-1 downto 0); + signal emif_ecc_usr_int : std_logic_vector(MEM_PORTS-1 downto 0); + signal emif_cal_success : std_logic_vector(MEM_PORTS-1 downto 0); + signal emif_cal_fail : std_logic_vector(MEM_PORTS-1 downto 0); + + signal misc_in : std_logic_vector(MISC_IN_WIDTH-1 downto 0); + signal misc_out : std_logic_vector(MISC_OUT_WIDTH-1 downto 0); + + signal pcie_clk : std_logic; + signal pcie_reset : std_logic; + +begin + -- Keep I2C in high impedance + SI5397A_I2C_SCL <= 'Z'; + SI5397A_I2C_SDA <= 'Z'; + + -- Make sure the external oscillator is running + SI5397A_OE_n <= '0'; + SI5397A_RST_n <= '1'; + + ag_i : entity work.FPGA_COMMON + generic map ( + PCIE_CONS => PCIE_CONS, + PCIE_LANES => PCIE_LANES, + PCIE_CLKS => PCIE_CLKS, + + -- Cesnet (To change this value, regenerate the R-TILE IP core) + PCI_VENDOR_ID => X"18EC", + -- Generic Card (To change this value, regenerate the R-TILE IP core) + PCI_DEVICE_ID => X"C000", + PCI_SUBVENDOR_ID => X"0000", + PCI_SUBDEVICE_ID => X"0000", + + ETH_CORE_ARCH => NET_MOD_ARCH, + ETH_PORTS => ETH_PORTS, + ETH_PORT_SPEED => ETH_PORT_SPEED, + ETH_PORT_CHAN => ETH_PORT_CHAN, + ETH_PORT_LEDS => 8, + ETH_LANES => ETH_LANES, + + QSFP_PORTS => ETH_PORTS, + QSFP_I2C_PORTS => ETH_PORTS, + + MEM_PORTS => MEM_PORTS, + MEM_ADDR_WIDTH => MEM_ADDR_WIDTH, + MEM_DATA_WIDTH => MEM_DATA_WIDTH, + MEM_BURST_WIDTH => MEM_BURST_WIDTH, + AMM_FREQ_KHZ => AMM_FREQ_KHZ, + + STATUS_LEDS => 2, + + MISC_IN_WIDTH => MISC_IN_WIDTH, + MISC_OUT_WIDTH => MISC_OUT_WIDTH, + + BOARD => CARD_NAME, + DEVICE => DEVICE, + + PCIE_ENDPOINTS => PCIE_ENDPOINTS, + PCIE_ENDPOINT_TYPE => PCIE_MOD_ARCH, + PCIE_ENDPOINT_MODE => PCIE_ENDPOINT_MODE, + + DMA_ENDPOINTS => DMA_ENDPOINTS, + DMA_MODULES => 1, + DMA_RX_CHANNELS => DMA_RX_CHANNELS, + DMA_TX_CHANNELS => DMA_TX_CHANNELS + ) + port map( + SYSCLK => AG_SYSCLK1_P, + SYSRST => '0', + + PCIE_SYSCLK_P => PCIE_CLK1_P & PCIE_CLK0_P, + PCIE_SYSCLK_N => (others => '0'), + PCIE_SYSRST_N => (others => PCIE_PERST_N), + + PCIE_RX_P => PCIE_RX_P, + PCIE_RX_N => PCIE_RX_N, + + PCIE_TX_P => PCIE_TX_P, + PCIE_TX_N => PCIE_TX_N, + + ETH_REFCLK_P(0) => QSFP_REFCLK0_P, + ETH_REFCLK_N(0) => '0', + ETH_RX_P => QSFP_RX_P, + ETH_RX_N => QSFP_RX_N, + ETH_TX_P => QSFP_TX_P, + ETH_TX_N => QSFP_TX_N, + + QSFP_I2C_SCL(0) => QSFP_I2C_SCL, + QSFP_I2C_SDA(0) => QSFP_I2C_SDA, + + QSFP_MODSEL_N(0) => QSFP_MODSEL_N, + QSFP_LPMODE(0) => QSFP_INITMODE, + QSFP_RESET_N(0) => QSFP_RST_N, + QSFP_MODPRS_N(0) => QSFP_MODPRS_N, + QSFP_INT_N(0) => QSFP_INT_N, + + MEM_CLK => mem_clk, + MEM_RST => not mem_rst_n_reg, + + MEM_AVMM_READY => mem_avmm_ready, + MEM_AVMM_READ => mem_avmm_read, + MEM_AVMM_WRITE => mem_avmm_write, + MEM_AVMM_ADDRESS => mem_avmm_address, + MEM_AVMM_BURSTCOUNT => mem_avmm_burstcount, + MEM_AVMM_WRITEDATA => mem_avmm_writedata, + MEM_AVMM_READDATA => mem_avmm_readdata, + MEM_AVMM_READDATAVALID => mem_avmm_readdatavalid, + + EMIF_RST_REQ => emif_rst_req, + EMIF_RST_DONE => emif_rst_done, + EMIF_ECC_USR_INT => emif_ecc_usr_int, + EMIF_CAL_SUCCESS => emif_cal_success, + EMIF_CAL_FAIL => emif_cal_fail, + + STATUS_LED_G => open, + STATUS_LED_R => open, + + PCIE_CLK => pcie_clk, + PCIE_RESET => pcie_reset, + + MISC_IN => misc_in, + MISC_OUT => misc_out + ); + + -- --------------------------------------------------------------------------- + -- SODIMM Memory modules available on the Card (DDR4) + -- --------------------------------------------------------------------------- + sodimm_ddr4_g: if MEM_PORTS = 4 generate + -- Registers to ensure that the reset meets the timing constraints + mem_rst_g : for i in 0 to MEM_PORTS-1 generate + mem_pll_locked_sync_i : entity work.ASYNC_OPEN_LOOP + generic map( + IN_REG => false, + TWO_REG => false + ) + port map( + ACLK => '0', + BCLK => mem_clk(i), + ARST => '0', + BRST => '0', + ADATAIN => mem_rst_n(i), + BDATAOUT => mem_rst_n_reg(i) + ); + end generate; + + -- DDR4A - HPS compatible + -- This IP core enables usage of DDR4 in non-HPS system + sodimm_hps_i : component sodimm_hps + port map ( + local_reset_req => emif_rst_req(0), + local_reset_done => emif_rst_done(0), + pll_ref_clk => SODIMM_HPS_REFCLK_P, + oct_rzqin => SODIMM_HPS_OCT_RZQ, + mem_ck(0) => SODIMM_HPS_PCK, + mem_ck_n(0) => SODIMM_HPS_NCK, + mem_a => SODIMM_HPS_A, + mem_act_n(0) => SODIMM_HPS_NACT, + mem_ba => SODIMM_HPS_BA, + mem_bg => SODIMM_HPS_BG, + mem_cke(0) => SODIMM_HPS_CKE, + mem_cs_n(0) => SODIMM_HPS_NCS, + mem_odt(0) => SODIMM_HPS_ODT, + mem_reset_n(0) => SODIMM_HPS_NRST, + mem_par(0) => SODIMM_HPS_PAR, + mem_alert_n(0) => SODIMM_HPS_NALERT, + mem_dqs => SODIMM_HPS_PDQS, + mem_dqs_n => SODIMM_HPS_NDQS, + mem_dq => SODIMM_HPS_DQ, + mem_dbi_n => SODIMM_HPS_DM_DBI, + + emif_usr_reset_n => mem_rst_n(0), + emif_usr_clk => mem_clk(0), + + amm_ready_0 => mem_avmm_ready(0), + amm_read_0 => mem_avmm_read(0), + amm_write_0 => mem_avmm_write(0), + amm_address_0 => mem_avmm_address(0), + amm_readdata_0 => mem_avmm_readdata(0), + amm_writedata_0 => mem_avmm_writedata(0), + amm_burstcount_0 => mem_avmm_burstcount(0), + amm_readdatavalid_0 => mem_avmm_readdatavalid(0), + amm_byteenable_0 => (others => '1'), + + local_cal_success => emif_cal_success(0), + local_cal_fail => emif_cal_fail(0), + + calbus_read => calbus_read(0), + calbus_write => calbus_write(0), + calbus_address => calbus_address(0), + calbus_wdata => calbus_wdata(0), + calbus_rdata => calbus_rdata(0), + calbus_seq_param_tbl => calbus_seq_param_tbl(0), + calbus_clk => calbus_clk(0), + + ctrl_ecc_user_interrupt_0 => open + ); + + -- DDR4B + sodimm0_i : component sodimm + port map ( + local_reset_req => emif_rst_req(1), + local_reset_done => emif_rst_done(1), + pll_ref_clk => SODIMM0_REFCLK_P, + oct_rzqin => SODIMM0_OCT_RZQ, + mem_ck(0) => SODIMM0_PCK, + mem_ck_n(0) => SODIMM0_NCK, + mem_a => SODIMM0_A, + mem_act_n(0) => SODIMM0_NACT, + mem_ba => SODIMM0_BA, + mem_bg => SODIMM0_BG, + mem_cke(0) => SODIMM0_CKE, + mem_cs_n(0) => SODIMM0_NCS, + mem_odt(0) => SODIMM0_ODT, + mem_reset_n(0) => SODIMM0_NRST, + mem_par(0) => SODIMM0_PAR, + mem_alert_n(0) => SODIMM0_NALERT, + mem_dqs => SODIMM0_PDQS, + mem_dqs_n => SODIMM0_NDQS, + mem_dq => SODIMM0_DQ, + mem_dbi_n => SODIMM0_DM_DBI, + + emif_usr_reset_n => mem_rst_n(1), + emif_usr_clk => mem_clk(1), + + amm_ready_0 => mem_avmm_ready(1), + amm_read_0 => mem_avmm_read(1), + amm_write_0 => mem_avmm_write(1), + amm_address_0 => mem_avmm_address(1), + amm_readdata_0 => mem_avmm_readdata(1), + amm_writedata_0 => mem_avmm_writedata(1), + amm_burstcount_0 => mem_avmm_burstcount(1), + amm_readdatavalid_0 => mem_avmm_readdatavalid(1), + amm_byteenable_0 => (others => '1'), + + local_cal_success => emif_cal_success(1), + local_cal_fail => emif_cal_fail(1), + + calbus_read => calbus_read(1), + calbus_write => calbus_write(1), + calbus_address => calbus_address(1), + calbus_wdata => calbus_wdata(1), + calbus_rdata => calbus_rdata(1), + calbus_seq_param_tbl => calbus_seq_param_tbl(1), + calbus_clk => calbus_clk(0), + + ctrl_ecc_user_interrupt_0 => open + ); + + -- DDR4C + sodimm1_i : component sodimm + port map ( + local_reset_req => emif_rst_req(2), + local_reset_done => emif_rst_done(2), + pll_ref_clk => SODIMM1_REFCLK_P, + oct_rzqin => SODIMM1_OCT_RZQ, + mem_ck(0) => SODIMM1_PCK, + mem_ck_n(0) => SODIMM1_NCK, + mem_a => SODIMM1_A, + mem_act_n(0) => SODIMM1_NACT, + mem_ba => SODIMM1_BA, + mem_bg => SODIMM1_BG, + mem_cke(0) => SODIMM1_CKE, + mem_cs_n(0) => SODIMM1_NCS, + mem_odt(0) => SODIMM1_ODT, + mem_reset_n(0) => SODIMM1_NRST, + mem_par(0) => SODIMM1_PAR, + mem_alert_n(0) => SODIMM1_NALERT, + mem_dqs => SODIMM1_PDQS, + mem_dqs_n => SODIMM1_NDQS, + mem_dq => SODIMM1_DQ, + mem_dbi_n => SODIMM1_DM_DBI, + + emif_usr_reset_n => mem_rst_n(2), + emif_usr_clk => mem_clk(2), + + amm_ready_0 => mem_avmm_ready(2), + amm_read_0 => mem_avmm_read(2), + amm_write_0 => mem_avmm_write(2), + amm_address_0 => mem_avmm_address(2), + amm_readdata_0 => mem_avmm_readdata(2), + amm_writedata_0 => mem_avmm_writedata(2), + amm_burstcount_0 => mem_avmm_burstcount(2), + amm_readdatavalid_0 => mem_avmm_readdatavalid(2), + amm_byteenable_0 => (others => '1'), + + local_cal_success => emif_cal_success(2), + local_cal_fail => emif_cal_fail(2), + + calbus_read => calbus_read(2), + calbus_write => calbus_write(2), + calbus_address => calbus_address(2), + calbus_wdata => calbus_wdata(2), + calbus_rdata => calbus_rdata(2), + calbus_seq_param_tbl => calbus_seq_param_tbl(2), + calbus_clk => calbus_clk(1), + + ctrl_ecc_user_interrupt_0 => open + ); + + -- DDR4D + sodimm2_i : component sodimm + port map ( + local_reset_req => emif_rst_req(3), + local_reset_done => emif_rst_done(3), + pll_ref_clk => SODIMM2_REFCLK_P, + oct_rzqin => SODIMM2_OCT_RZQ, + mem_ck(0) => SODIMM2_PCK, + mem_ck_n(0) => SODIMM2_NCK, + mem_a => SODIMM2_A, + mem_act_n(0) => SODIMM2_NACT, + mem_ba => SODIMM2_BA, + mem_bg => SODIMM2_BG, + mem_cke(0) => SODIMM2_CKE, + mem_cs_n(0) => SODIMM2_NCS, + mem_odt(0) => SODIMM2_ODT, + mem_reset_n(0) => SODIMM2_NRST, + mem_par(0) => SODIMM2_PAR, + mem_alert_n(0) => SODIMM2_NALERT, + mem_dqs => SODIMM2_PDQS, + mem_dqs_n => SODIMM2_NDQS, + mem_dq => SODIMM2_DQ, + mem_dbi_n => SODIMM2_DM_DBI, + + emif_usr_reset_n => mem_rst_n(3), + emif_usr_clk => mem_clk(3), + + amm_ready_0 => mem_avmm_ready(3), + amm_read_0 => mem_avmm_read(3), + amm_write_0 => mem_avmm_write(3), + amm_address_0 => mem_avmm_address(3), + amm_readdata_0 => mem_avmm_readdata(3), + amm_writedata_0 => mem_avmm_writedata(3), + amm_burstcount_0 => mem_avmm_burstcount(3), + amm_readdatavalid_0 => mem_avmm_readdatavalid(3), + amm_byteenable_0 => (others => '1'), + + local_cal_success => emif_cal_success(3), + local_cal_fail => emif_cal_fail(3), + + calbus_read => calbus_read(3), + calbus_write => calbus_write(3), + calbus_address => calbus_address(3), + calbus_wdata => calbus_wdata(3), + calbus_rdata => calbus_rdata(3), + calbus_seq_param_tbl => calbus_seq_param_tbl(3), + calbus_clk => calbus_clk(1), + + ctrl_ecc_user_interrupt_0 => open + ); + + -- Memory calibration - HPS Compatible SODIMM & SODIMM0 + sodimm_cal_AB_i : component sodimm_cal + port map ( + calbus_read_0 => calbus_read(0), + calbus_write_0 => calbus_write(0), + calbus_address_0 => calbus_address(0), + calbus_wdata_0 => calbus_wdata(0), + calbus_rdata_0 => calbus_rdata(0), + calbus_seq_param_tbl_0 => calbus_seq_param_tbl(0), + calbus_read_1 => calbus_read(1), + calbus_write_1 => calbus_write(1), + calbus_address_1 => calbus_address(1), + calbus_wdata_1 => calbus_wdata(1), + calbus_rdata_1 => calbus_rdata(1), + calbus_seq_param_tbl_1 => calbus_seq_param_tbl(1), + calbus_clk => calbus_clk(0) + ); + + -- Memory calibration - SODIMM1 & SODIMM2 + sodimm_cal_CD_i : component sodimm_cal + port map ( + calbus_read_0 => calbus_read(2), + calbus_write_0 => calbus_write(2), + calbus_address_0 => calbus_address(2), + calbus_wdata_0 => calbus_wdata(2), + calbus_rdata_0 => calbus_rdata(2), + calbus_seq_param_tbl_0 => calbus_seq_param_tbl(2), + calbus_read_1 => calbus_read(3), + calbus_write_1 => calbus_write(3), + calbus_address_1 => calbus_address(3), + calbus_wdata_1 => calbus_wdata(3), + calbus_rdata_1 => calbus_rdata(3), + calbus_seq_param_tbl_1 => calbus_seq_param_tbl(3), + calbus_clk => calbus_clk(1) + ); + end generate; + + -- Disable SODIMM DDR4 + sodimm_ddr4_empty_g: if MEM_PORTS /= 4 generate + SODIMM_HPS_NACT <= 'Z'; + SODIMM_HPS_NRST <= 'Z'; + SODIMM_HPS_PAR <= 'Z'; + SODIMM_HPS_PCK <= 'Z'; + SODIMM_HPS_NCK <= 'Z'; + SODIMM_HPS_A <= (others => 'Z'); + SODIMM_HPS_BA <= (others => 'Z'); + SODIMM_HPS_BG <= (others => 'Z'); + SODIMM_HPS_CKE <= 'Z'; + SODIMM_HPS_NCS <= 'Z'; + SODIMM_HPS_ODT <= 'Z'; + SODIMM_HPS_PDQS <= (others => 'Z'); + SODIMM_HPS_NDQS <= (others => 'Z'); + SODIMM_HPS_DM_DBI <= (others => 'Z'); + SODIMM_HPS_DQ <= (others => 'Z'); + + SODIMM0_NACT <= 'Z'; + SODIMM0_NRST <= 'Z'; + SODIMM0_PAR <= 'Z'; + SODIMM0_PCK <= 'Z'; + SODIMM0_NCK <= 'Z'; + SODIMM0_A <= (others => 'Z'); + SODIMM0_BA <= (others => 'Z'); + SODIMM0_BG <= (others => 'Z'); + SODIMM0_CKE <= 'Z'; + SODIMM0_NCS <= 'Z'; + SODIMM0_ODT <= 'Z'; + SODIMM0_PDQS <= (others => 'Z'); + SODIMM0_NDQS <= (others => 'Z'); + SODIMM0_DM_DBI <= (others => 'Z'); + SODIMM0_DQ <= (others => 'Z'); + + SODIMM1_NACT <= 'Z'; + SODIMM1_NRST <= 'Z'; + SODIMM1_PAR <= 'Z'; + SODIMM1_PCK <= 'Z'; + SODIMM1_NCK <= 'Z'; + SODIMM1_A <= (others => 'Z'); + SODIMM1_BA <= (others => 'Z'); + SODIMM1_BG <= (others => 'Z'); + SODIMM1_CKE <= 'Z'; + SODIMM1_NCS <= 'Z'; + SODIMM1_ODT <= 'Z'; + SODIMM1_PDQS <= (others => 'Z'); + SODIMM1_NDQS <= (others => 'Z'); + SODIMM1_DM_DBI <= (others => 'Z'); + SODIMM1_DQ <= (others => 'Z'); + + SODIMM2_NACT <= 'Z'; + SODIMM2_NRST <= 'Z'; + SODIMM2_PAR <= 'Z'; + SODIMM2_PCK <= 'Z'; + SODIMM2_NCK <= 'Z'; + SODIMM2_A <= (others => 'Z'); + SODIMM2_BA <= (others => 'Z'); + SODIMM2_BG <= (others => 'Z'); + SODIMM2_CKE <= 'Z'; + SODIMM2_NCS <= 'Z'; + SODIMM2_ODT <= 'Z'; + SODIMM2_PDQS <= (others => 'Z'); + SODIMM2_NDQS <= (others => 'Z'); + SODIMM2_DM_DBI <= (others => 'Z'); + SODIMM2_DQ <= (others => 'Z'); + end generate; + +end architecture; diff --git a/cards/terasic/a2700/src/ip/ddr4_calibration.ip.tcl b/cards/terasic/a2700/src/ip/ddr4_calibration.ip.tcl new file mode 100644 index 000000000..43483013a --- /dev/null +++ b/cards/terasic/a2700/src/ip/ddr4_calibration.ip.tcl @@ -0,0 +1,36 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +# adjust parameters in "ddr4_calibration_ip" system +proc do_adjust_ddr4_calibration_ip {device family ipname filename} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + set_instance_parameter_value emif_cal_0 {AXM_ID_NUM} {0} + set_instance_parameter_value emif_cal_0 {DIAG_ENABLE_JTAG_UART} {0} + set_instance_parameter_value emif_cal_0 {DIAG_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_instance_parameter_value emif_cal_0 {DIAG_EXPORT_VJI} {0} + set_instance_parameter_value emif_cal_0 {DIAG_EXTRA_CONFIGS} {} + set_instance_parameter_value emif_cal_0 {DIAG_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} + set_instance_parameter_value emif_cal_0 {DIAG_SIM_VERBOSE} {0} + set_instance_parameter_value emif_cal_0 {DIAG_SYNTH_FOR_SIM} {0} + set_instance_parameter_value emif_cal_0 {ENABLE_DDRT} {0} + set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {2} + set_instance_parameter_value emif_cal_0 {PHY_DDRT_EXPORT_CLK_STP_IF} {0} + set_instance_parameter_value emif_cal_0 {SHORT_QSYS_INTERFACE_NAMES} {1} + set_instance_property emif_cal_0 AUTO_EXPORT true + + # add the exports + set_interface_property emif_calbus_0 EXPORT_OF emif_cal_0.emif_calbus_0 + set_interface_property emif_calbus_1 EXPORT_OF emif_cal_0.emif_calbus_1 + set_interface_property emif_calbus_clk EXPORT_OF emif_cal_0.emif_calbus_clk + + save_system $ipname +} + +do_adjust_ddr4_calibration_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] diff --git a/cards/terasic/a2700/src/ip/ftile_eth.ip.tcl b/cards/terasic/a2700/src/ip/ftile_eth.ip.tcl new file mode 100644 index 000000000..cccce3afd --- /dev/null +++ b/cards/terasic/a2700/src/ip/ftile_eth.ip.tcl @@ -0,0 +1,42 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +# adjust parameters in "ftile_eth_ip" system +proc do_adjust_ftile_eth_ip {device family ipname filename} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + # common IP core parameters + set_instance_parameter_value eth_f_0 {DV_OVERRIDE} {1} + set_instance_parameter_value eth_f_0 {ENABLE_ETK_GUI} {1} + set_instance_parameter_value eth_f_0 {SYSPLL_RATE_GUI} {1} + set_instance_parameter_value eth_f_0 {enforce_max_frame_size_gui} {1} + set_instance_parameter_value eth_f_0 {link_fault_mode_gui} {Bidirectional} + set_instance_parameter_value eth_f_0 {rx_max_frame_size_gui} {16383} + set_instance_parameter_value eth_f_0 {rx_vlan_detection_gui} {0} + set_instance_parameter_value eth_f_0 {tx_max_frame_size_gui} {16383} + set_instance_parameter_value eth_f_0 {tx_vlan_detection_gui} {0} + + # configuration-specific parameters + set_instance_parameter_value eth_f_0 {ENABLE_ADME_GUI} {1} + set_instance_parameter_value eth_f_0 {ETH_MODE_GUI} {400G-8} + set_instance_parameter_value eth_f_0 {PACKING_EN_GUI} {1} + set_instance_parameter_value eth_f_0 {RSFEC_TYPE_GUI} {3} + + set_interface_property reconfig_xcvr_slave_1 EXPORT_OF eth_f_0.reconfig_xcvr_slave_1 + set_interface_property reconfig_xcvr_slave_2 EXPORT_OF eth_f_0.reconfig_xcvr_slave_2 + set_interface_property reconfig_xcvr_slave_3 EXPORT_OF eth_f_0.reconfig_xcvr_slave_3 + set_interface_property reconfig_xcvr_slave_4 EXPORT_OF eth_f_0.reconfig_xcvr_slave_4 + set_interface_property reconfig_xcvr_slave_5 EXPORT_OF eth_f_0.reconfig_xcvr_slave_5 + set_interface_property reconfig_xcvr_slave_6 EXPORT_OF eth_f_0.reconfig_xcvr_slave_6 + set_interface_property reconfig_xcvr_slave_7 EXPORT_OF eth_f_0.reconfig_xcvr_slave_7 + + save_system $ipname +} + +do_adjust_ftile_eth_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] diff --git a/cards/terasic/a2700/src/ip/ftile_pll.ip.tcl b/cards/terasic/a2700/src/ip/ftile_pll.ip.tcl new file mode 100644 index 000000000..2d226b95e --- /dev/null +++ b/cards/terasic/a2700/src/ip/ftile_pll.ip.tcl @@ -0,0 +1,22 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +# adjust parameters in "ftile_pll_ip" system +proc do_adjust_ftile_pll_ip {device family ipname filename} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + set_instance_parameter_value systemclk_f_0 {refclk_fgt_output_enable_0} {1} + set_instance_parameter_value systemclk_f_0 {syspll_mod_0} {ETHERNET_FREQ_830_156} + + set_interface_property out_refclk_fgt_0 EXPORT_OF systemclk_f_0.out_refclk_fgt_0 + + save_system $ipname +} + +do_adjust_ftile_pll_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] diff --git a/cards/terasic/a2700/src/ip/iopll.ip.tcl b/cards/terasic/a2700/src/ip/iopll.ip.tcl new file mode 100644 index 000000000..9529110a2 --- /dev/null +++ b/cards/terasic/a2700/src/ip/iopll.ip.tcl @@ -0,0 +1,62 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +#100 MHz +proc do_adjust_iopll_ip_0 {} { +} + +# Adjust for 50 MHz sysclk +proc do_adjust_iopll_ip_1 {} { + set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {50.0} + set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {20000.0} + set_instance_parameter_value iopll_0 {gui_user_base_address} {0} +} + +proc do_adjust_iopll_ip {device family ipname filename adjust_proc} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {1} + set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {3} + set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {4} + set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1666.667} + set_instance_parameter_value iopll_0 {gui_multiply_factor} {12} + set_instance_parameter_value iopll_0 {gui_number_of_clocks} {4} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {400.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {300.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {200.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {2500.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {3333.333} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {5000.0} + set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {High} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_disabled} + set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_disabled} + + $adjust_proc + + set_instance_parameter_value iopll_0 {gui_vco_frequency} {1200.0} + set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0} + + # add the exports + set_interface_property outclk1 EXPORT_OF iopll_0.outclk1 + set_interface_property outclk2 EXPORT_OF iopll_0.outclk2 + set_interface_property outclk3 EXPORT_OF iopll_0.outclk3 + + save_system $ipname +} + +proc do_nothing {} {} + +set cb do_nothing +if {$PARAMS(IP_COMP_TYPE) == 0} { + set cb do_adjust_iopll_ip_0 +} elseif {$PARAMS(IP_COMP_TYPE) == 1} { + set cb do_adjust_iopll_ip_1 +} + +do_adjust_iopll_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb diff --git a/cards/terasic/a2700/src/ip/onboard_ddr4.ip.tcl b/cards/terasic/a2700/src/ip/onboard_ddr4.ip.tcl new file mode 100644 index 000000000..3412dbe61 --- /dev/null +++ b/cards/terasic/a2700/src/ip/onboard_ddr4.ip.tcl @@ -0,0 +1,79 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +proc do_adjust_onboard_ddr4_ip_0 {} { + set_instance_parameter_value emif_fm_0 {PHY_DDR4_MIMIC_HPS_EMIF} {0} +} + +proc do_adjust_onboard_ddr4_ip_1 {} { + set_instance_parameter_value emif_fm_0 {PHY_DDR4_MIMIC_HPS_EMIF} {1} +} + + +proc do_adjust_onboard_ddr4_ip {device family ipname filename adjust_proc} { + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ECC_AUTO_CORRECTION_EN} {1} + set_instance_parameter_value emif_fm_0 {CTRL_DDR4_ECC_EN} {1} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_SODIMM} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_ROW_ADDR_WIDTH} {16} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_3200} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TCCD_L_CYC} {7} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TCL} {22} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDIVW_TOTAL_UI} {0.23} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDQSCK_PS} {160} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TDQSQ_UI} {0.2} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIH_DC_MV} {65} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIH_PS} {65} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIS_AC_MV} {90} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TIS_PS} {40} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TQH_UI} {0.7} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TQSH_CYC} {0.4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRCD_NS} {13.75} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRFC_NS} {350.0} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRP_NS} {13.75} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TRRD_L_CYC} {7} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWTR_L_CYC} {10} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_TWTR_S_CYC} {4} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_VDIVW_TOTAL} {110} + set_instance_parameter_value emif_fm_0 {MEM_DDR4_WTCL} {18} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_ALLOW_72_DQ_WIDTH} {0} + set_instance_parameter_value emif_fm_0 {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1333.333} + + $adjust_proc + + set_instance_parameter_value emif_fm_0 {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {33.333} + set_instance_property emif_fm_0 AUTO_EXPORT true + + # add the exports + set_interface_property local_reset_req EXPORT_OF emif_fm_0.local_reset_req + set_interface_property local_reset_status EXPORT_OF emif_fm_0.local_reset_status + set_interface_property pll_ref_clk EXPORT_OF emif_fm_0.pll_ref_clk + set_interface_property oct EXPORT_OF emif_fm_0.oct + set_interface_property mem EXPORT_OF emif_fm_0.mem + set_interface_property status EXPORT_OF emif_fm_0.status + set_interface_property emif_usr_reset_n EXPORT_OF emif_fm_0.emif_usr_reset_n + set_interface_property emif_usr_clk EXPORT_OF emif_fm_0.emif_usr_clk + set_interface_property ctrl_amm_0 EXPORT_OF emif_fm_0.ctrl_amm_0 + set_interface_property emif_calbus EXPORT_OF emif_fm_0.emif_calbus + set_interface_property emif_calbus_clk EXPORT_OF emif_fm_0.emif_calbus_clk + + save_system $ipname + +} + +proc do_nothing {} {} + +set cb do_nothing +if {$PARAMS(IP_COMP_TYPE) == 0} { + set cb do_adjust_onboard_ddr4_ip_0 +} elseif {$PARAMS(IP_COMP_TYPE) == 1} { + set cb do_adjust_onboard_ddr4_ip_1 +} + +do_adjust_onboard_ddr4_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb diff --git a/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl b/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl new file mode 100644 index 000000000..5d1f392f0 --- /dev/null +++ b/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl @@ -0,0 +1,85 @@ +package require -exact qsys 21.3 + +array set PARAMS $IP_PARAMS_L +source $PARAMS(IP_COMMON_TCL) + +proc do_adjust_rtile_pcie_ip_1x16 {} { +} + +proc do_adjust_rtile_pcie_ip_2x8 {} { + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_0_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_1_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {49152} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_vendor_id_user_hwtcl} {6380} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {design_environment} {Unknown} + set_instance_parameter_value intel_rtile_pcie_ast_0 {standard_interface_selection_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit} + + set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0 + set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc + set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1 + set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc + set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0 + set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1 + set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp + set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n + set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n + set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status + set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt + set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp + set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii +} + +# adjust parameters in "rtile_pcie_ip" system +proc do_adjust_rtile_pcie_ip {device family ipname filename adjust_proc} { + + load_system $filename + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {true} + + # common IP core parameters + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {49152} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_vendor_id_user_hwtcl} {6380} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {g5_pld_clkfreq_user_hwtcl} {400MHz} + + # configuration-specific parameters + $adjust_proc + + set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii + + save_system $ipname +} + +proc do_nothing {} {} + +set cb do_nothing +if {$PARAMS(PCIE_ENDPOINT_MODE) == 0} { + set cb do_adjust_rtile_pcie_ip_1x16 +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1} { + set cb do_adjust_rtile_pcie_ip_2x8 +} + +do_adjust_rtile_pcie_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb diff --git a/doc/source/index.rst b/doc/source/index.rst index 97c525385..ce3c1637a 100644 --- a/doc/source/index.rst +++ b/doc/source/index.rst @@ -107,6 +107,7 @@ support a subset of these cards. A complete list of supported FPGA cards can be ndk_cards/amd/vcu118/readme extra/nfb-200g2ql/readme ndk_cards/prodesign/pd-falcon/readme + ndk_cards/terasic/a2700/readme --------