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Merge branch 'isa_dma_calypte' into 'devel'
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Change byte array to logic_vector_array

See merge request ndk/ndk-fpga!118
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@jakubcabal
jakubcabal committed Dec 5, 2024
2 parents 54f78c4 + c73b778 commit eb670c4
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Showing 13 changed files with 130 additions and 158 deletions.
1 change: 0 additions & 1 deletion comp/dma/dma_calypte/comp/rx/uvm/Modules.tcl
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Expand Up @@ -11,7 +11,6 @@ set SV_MVB_PIPE_UVM_BASE "$OFM_PATH/comp/mvb_tools/flow/pipe/uvm"

lappend COMPONENTS [ list "SV_COMMON" "$UVM_PATH/common" "FULL"]
lappend COMPONENTS [ list "SV_RESET" "$UVM_PATH/reset" "FULL"]
lappend COMPONENTS [ list "SV_BYTE_ARRAY_MFB" "$UVM_PATH/byte_array_mfb" "FULL"]
lappend COMPONENTS [ list "SV_LOGIC_VECTOR_ARRAY_MFB" "$UVM_PATH/logic_vector_array_mfb" "FULL"]
lappend COMPONENTS [ list "SV_MVB" "$UVM_PATH/mvb" "FULL"]
lappend COMPONENTS [ list "SV_MI" "$UVM_PATH/mi" "FULL"]
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12 changes: 6 additions & 6 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/env/env.sv
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Expand Up @@ -11,15 +11,15 @@ class env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, PC

localparam INPUT_META_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);

sequencer#(PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS) m_sequencer;
sequencer#(USER_ITEM_WIDTH, PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS) m_sequencer;

uvm_reset::agent m_reset;
uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, CHANNELS, PKT_SIZE_MAX) m_env_rx;
uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX) m_env_rx;
uvm_logic_vector_array_mfb::env_tx #(PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH) m_env_tx;
uvm_mvb::agent_rx#(1, 1) m_dma;
uvm_mi::regmodel#(regmodel#(CHANNELS), MI_WIDTH, MI_WIDTH) m_regmodel;

scoreboard #(CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE) sc;
scoreboard #(USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE) sc;

// Constructor of environment.
function new(string name, uvm_component parent);
Expand Down Expand Up @@ -51,7 +51,7 @@ class env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, PC
m_config_rx.active = UVM_ACTIVE;
m_config_rx.interface_name = "vif_rx";
uvm_config_db #(uvm_dma_ll_rx::config_item)::set(this, "m_env_rx", "m_config", m_config_rx);
m_env_rx = uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, CHANNELS, PKT_SIZE_MAX)::type_id::create("m_env_rx", this);
m_env_rx = uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX)::type_id::create("m_env_rx", this);

m_config_tx = new;
m_config_tx.active = UVM_ACTIVE;
Expand All @@ -73,9 +73,9 @@ class env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, PC
uvm_config_db#(uvm_mi::regmodel_config)::set(this, "m_regmodel", "m_config", m_mi_config);
m_regmodel = uvm_mi::regmodel#(regmodel#(CHANNELS), MI_WIDTH, MI_WIDTH)::type_id::create("m_regmodel", this);

sc = scoreboard #(CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE)::type_id::create("sc", this);
sc = scoreboard #(USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE)::type_id::create("sc", this);

m_sequencer = sequencer#(PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS)::type_id::create("m_sequencer", this);
m_sequencer = sequencer#(USER_ITEM_WIDTH, PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS)::type_id::create("m_sequencer", this);
endfunction

// Connect agent's ports with ports from scoreboard.
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18 changes: 9 additions & 9 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/env/model.sv
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Expand Up @@ -78,20 +78,20 @@ class disc_probe_cbs extends uvm_probe::cbs_simple #(1);
endfunction
endclass

class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
`uvm_component_param_utils(uvm_dma_ll::model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))
class model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
`uvm_component_param_utils(uvm_dma_ll::model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))

localparam USER_META_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);
localparam IS_INTEL_DEV = (DEVICE == "STRATIX10" || DEVICE == "AGILEX");

//UVM PROBE - model input
disc_probe_cbs uvm_probe_discard;

uvm_tlm_analysis_fifo #(uvm_byte_array::sequence_item) analysis_imp_rx;
uvm_tlm_analysis_fifo #(uvm_logic_vector::sequence_item#(USER_META_WIDTH)) analysis_imp_rx_meta;
model_accept#(CHANNELS) analysis_dma;
uvm_analysis_port #(uvm_logic_vector_array::sequence_item#(32)) analysis_port_tx;
uvm_analysis_port #(uvm_logic_vector::sequence_item#(META_WIDTH)) analysis_port_tx_meta;
uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) analysis_imp_rx;
uvm_tlm_analysis_fifo #(uvm_logic_vector::sequence_item#(USER_META_WIDTH)) analysis_imp_rx_meta;
model_accept#(CHANNELS) analysis_dma;
uvm_analysis_port #(uvm_logic_vector_array::sequence_item#(32)) analysis_port_tx;
uvm_analysis_port #(uvm_logic_vector::sequence_item#(META_WIDTH)) analysis_port_tx_meta;

typedef struct{
logic [$clog2(PKT_SIZE_MAX+1)-1:0] packet_size;
Expand Down Expand Up @@ -228,7 +228,7 @@ class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
end
endfunction

task packet_send(byte unsigned packet[], time start_time, int unsigned channel, logic [24-1:0] meta);
task packet_send(logic [ITEM_WIDTH-1:0] packet[], time start_time, int unsigned channel, logic [24-1:0] meta);
uvm_logic_vector::sequence_item#(META_WIDTH) packet_meta;

model_packet packet_output;
Expand Down Expand Up @@ -347,7 +347,7 @@ class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
endfunction

task run_phase(uvm_phase phase);
uvm_byte_array::sequence_item tr;
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) tr;
string msg;
int unsigned compare;
int unsigned soft_compare;
Expand Down
78 changes: 18 additions & 60 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/env/scoreboard.sv
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Expand Up @@ -4,63 +4,14 @@

//-- SPDX-License-Identifier: BSD-3-Clause

class stats;

local real min;
local real max;
local real sum;
local real sum2;

int unsigned values;

function new();
values = 0;
sum = 0;
sum2 = 0;
endfunction


function void count(output real min, real max, real avg, real std_dev);
real avg_local;

min = this.min;
max = this.max;

avg_local = sum/values;
avg = avg_local;

std_dev = (1.0/(values-1)*(sum2 - values*(avg_local**2)))**0.5;
endfunction

function void next_val(real val);
if (values == 0) begin
min = val;
max = val;
end else begin
if (min > val) begin
min = val;
end

if (max < val) begin
max = val;
end
end

sum += val;
sum2 += val**2;

values++;
endfunction
endclass

class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_scoreboard;
`uvm_component_param_utils(uvm_dma_ll::scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))
class scoreboard #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_scoreboard;
`uvm_component_param_utils(uvm_dma_ll::scoreboard #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))

localparam LOGIC_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);

//INPUT TO DUT
uvm_analysis_export #(uvm_byte_array::sequence_item) analysis_export_rx_packet;
uvm_analysis_export #(uvm_logic_vector::sequence_item#(LOGIC_WIDTH)) analysis_export_rx_meta;
uvm_analysis_export #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) analysis_export_rx_packet;
uvm_analysis_export #(uvm_logic_vector::sequence_item#(LOGIC_WIDTH)) analysis_export_rx_meta;

//DUT WATCH INTERFACE
uvm_analysis_export #(uvm_mvb::sequence_item#(1, 1)) analysis_export_dma;
Expand All @@ -74,13 +25,13 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
local uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item#(32)) model_output;
local uvm_tlm_analysis_fifo #(uvm_logic_vector::sequence_item#(META_WIDTH)) model_meta_output;

local model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) m_model;
local model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) m_model;
local regmodel#(CHANNELS) m_regmodel;

local stats m_input_speed;
local uvm_tlm_analysis_fifo #(uvm_byte_array::sequence_item) rx_speed_meter;
local stats m_delay;
local stats m_output_speed;
local uvm_common::stats m_input_speed;
local uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) rx_speed_meter;
local uvm_common::stats m_delay;
local uvm_common::stats m_output_speed;
local int unsigned compared = 0;
local int unsigned errors = 0;
typedef struct{
Expand Down Expand Up @@ -123,7 +74,7 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score

//build phase
function void build_phase(uvm_phase phase);
m_model = model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE)::type_id::create("m_model", this);
m_model = model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE)::type_id::create("m_model", this);
endfunction

function void connect_phase(uvm_phase phase);
Expand Down Expand Up @@ -179,7 +130,7 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
time speed_start_time = 0ns;

forever begin
uvm_byte_array::sequence_item tr;
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) tr;
time time_act;
time speed_metet_duration;
rx_speed_meter.get(tr);
Expand Down Expand Up @@ -275,6 +226,13 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
end
endtask

function void check_phase(uvm_phase phase);

if (dut_data_output.size() != 0 || dut_meta_output.size() != 0 || model_output.size() != 0 || model_meta_output.size() != 0) begin
`uvm_error(this.get_full_name(), $sformatf("\nExpected some data\n\tMODELs data Packets(%0d) meta(%0d)\n\tDUTs data packets(%0d) meta(%0d)", model_output.size(), model_meta_output.size(), dut_data_output.size(), dut_meta_output.size()));
end
endfunction

function void report_phase(uvm_phase phase);
real min;
real max;
Expand Down
8 changes: 4 additions & 4 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/env/sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@

//-- SPDX-License-Identifier: BSD-3-Clause

class sequencer#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH, CHANNELS) extends uvm_sequencer;
`uvm_component_param_utils(uvm_dma_ll::sequencer#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH, CHANNELS))
class sequencer#(USR_ITEM_WIDTH, PCIE_REGIONS, PCIE_REGION_SIZE, PCIE_BLOCK_SIZE, PCIE_ITEM_WIDTH, PCIE_META_WIDTH, CHANNELS) extends uvm_sequencer;
`uvm_component_param_utils(uvm_dma_ll::sequencer#(USR_ITEM_WIDTH, PCIE_REGIONS, PCIE_REGION_SIZE, PCIE_BLOCK_SIZE, PCIE_ITEM_WIDTH, PCIE_META_WIDTH, CHANNELS))

uvm_reset::sequencer m_reset;
uvm_dma_ll_rx::sequencer m_packet;
uvm_mfb::sequencer #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH) m_pcie;
uvm_dma_ll_rx::sequencer#(USR_ITEM_WIDTH) m_packet;
uvm_mfb::sequencer #(PCIE_REGIONS, PCIE_REGION_SIZE, PCIE_BLOCK_SIZE, PCIE_ITEM_WIDTH, PCIE_META_WIDTH) m_pcie;
uvm_dma_ll::regmodel #(CHANNELS) m_regmodel;

function new(string name = "virt_sequencer", uvm_component parent);
Expand Down
42 changes: 19 additions & 23 deletions comp/dma/dma_calypte/comp/rx/uvm/tbench/rx_env/driver.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -5,42 +5,40 @@
//-- SPDX-License-Identifier: BSD-3-Clause


class driver#(CHANNELS, PKT_SIZE_MAX) extends uvm_component;
`uvm_component_param_utils(uvm_dma_ll_rx::driver#(CHANNELS, PKT_SIZE_MAX))
class driver#(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX) extends uvm_component;
`uvm_component_param_utils(uvm_dma_ll_rx::driver#(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX))

localparam MFB_META_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);

uvm_seq_item_pull_port #(uvm_byte_array::sequence_item, uvm_byte_array::sequence_item) seq_item_port_byte_array;
uvm_seq_item_pull_port #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH), uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) seq_item_port_logic_vector_array;

mailbox#(uvm_byte_array::sequence_item) byte_array_export;
mailbox#(uvm_logic_vector::sequence_item#(MFB_META_WIDTH)) logic_vector_export;
local semaphore sem;
mailbox#(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) logic_vector_array_export;
mailbox#(uvm_logic_vector::sequence_item#(MFB_META_WIDTH)) logic_vector_export;

// ------------------------------------------------------------------------
// Constructor
function new(string name, uvm_component parent);
super.new(name, parent);

seq_item_port_byte_array = new("seq_item_port_byte_array", this);
seq_item_port_logic_vector_array = new("seq_item_port_logic_vector_array", this);

byte_array_export = new(1);
logic_vector_export = new(1);
sem = new(1);
logic_vector_array_export = new(1);
logic_vector_export = new(1);
endfunction

function int unsigned used();
int unsigned ret = 0;
ret |= (byte_array_export.num() != 0);
ret |= (logic_vector_array_export.num() != 0);
ret |= (logic_vector_export.num() != 0);
return ret;
endfunction

// ------------------------------------------------------------------------
// Starts driving signals to interface
task run_phase(uvm_phase phase);
uvm_byte_array::sequence_item byte_array_req;
uvm_byte_array::sequence_item byte_array_new;
uvm_logic_vector::sequence_item#(MFB_META_WIDTH) logic_vector_new;
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) logic_vector_array_req;
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) logic_vector_array_new;
uvm_logic_vector::sequence_item#(MFB_META_WIDTH) logic_vector_new;

logic [$clog2(PKT_SIZE_MAX+1)-1:0] packet_size;
int unsigned channel;
Expand All @@ -49,12 +47,12 @@ class driver#(CHANNELS, PKT_SIZE_MAX) extends uvm_component;

forever begin
// Get new sequence item to drive to interface
seq_item_port_byte_array.get_next_item(byte_array_req);
seq_item_port_logic_vector_array.get_next_item(logic_vector_array_req);

msg = {msg, $sformatf("-------------------------------------------------------\n")};
msg = {msg, $sformatf("DRIVER: Got new transaction:\n")};
msg = {msg, $sformatf("-------------------------------------------------------\n")};
msg = {msg, $sformatf("%s\n", byte_array_req.convert2string())};
msg = {msg, $sformatf("%s\n", logic_vector_array_req.convert2string())};


assert(std::randomize(channel) with {channel >= 0; channel < CHANNELS;});
Expand All @@ -63,21 +61,19 @@ class driver#(CHANNELS, PKT_SIZE_MAX) extends uvm_component;
msg = {msg, $sformatf("\nChannel: %0d\n", channel)};
msg = {msg, $sformatf("Meta: 0x%x\n", meta)};

$cast(byte_array_new, byte_array_req.clone());
$cast(logic_vector_array_new, logic_vector_array_req.clone());
logic_vector_new = uvm_logic_vector::sequence_item#(MFB_META_WIDTH)::type_id::create("logic_vector_new");
packet_size = byte_array_new.data.size();
packet_size = logic_vector_array_new.data.size();
logic_vector_new.data = {packet_size, channel, meta};
msg = {msg, $sformatf("Pkt size: %0d\n", packet_size)};

`uvm_info(this.get_full_name(), msg, UVM_HIGH);

wait(byte_array_export.num() == 0 || logic_vector_export.num() == 0);
sem.get(1);
byte_array_export.put(byte_array_new);
wait(logic_vector_array_export.num() == 0 || logic_vector_export.num() == 0);
logic_vector_array_export.put(logic_vector_array_new);
logic_vector_export.put(logic_vector_new);
sem.put(1);

seq_item_port_byte_array.item_done();
seq_item_port_logic_vector_array.item_done();
end
endtask

Expand Down
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