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jakubcabaljakubcabal
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Merge branch 'isa_dma_calypte' into 'devel'
Change byte array to logic_vector_array See merge request ndk/ndk-fpga!118
2 parents 54f78c4 + c73b778 commit eb670c4

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13 files changed

+130
-158
lines changed

13 files changed

+130
-158
lines changed

‎comp/dma/dma_calypte/comp/rx/uvm/Modules.tcl

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@ set SV_MVB_PIPE_UVM_BASE "$OFM_PATH/comp/mvb_tools/flow/pipe/uvm"
1111

1212
lappend COMPONENTS [ list "SV_COMMON" "$UVM_PATH/common" "FULL"]
1313
lappend COMPONENTS [ list "SV_RESET" "$UVM_PATH/reset" "FULL"]
14-
lappend COMPONENTS [ list "SV_BYTE_ARRAY_MFB" "$UVM_PATH/byte_array_mfb" "FULL"]
1514
lappend COMPONENTS [ list "SV_LOGIC_VECTOR_ARRAY_MFB" "$UVM_PATH/logic_vector_array_mfb" "FULL"]
1615
lappend COMPONENTS [ list "SV_MVB" "$UVM_PATH/mvb" "FULL"]
1716
lappend COMPONENTS [ list "SV_MI" "$UVM_PATH/mi" "FULL"]

‎comp/dma/dma_calypte/comp/rx/uvm/tbench/env/env.sv

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,15 @@ class env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, PC
1111

1212
localparam INPUT_META_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);
1313

14-
sequencer#(PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS) m_sequencer;
14+
sequencer#(USER_ITEM_WIDTH, PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS) m_sequencer;
1515

1616
uvm_reset::agent m_reset;
17-
uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, CHANNELS, PKT_SIZE_MAX) m_env_rx;
17+
uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX) m_env_rx;
1818
uvm_logic_vector_array_mfb::env_tx #(PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH) m_env_tx;
1919
uvm_mvb::agent_rx#(1, 1) m_dma;
2020
uvm_mi::regmodel#(regmodel#(CHANNELS), MI_WIDTH, MI_WIDTH) m_regmodel;
2121

22-
scoreboard #(CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE) sc;
22+
scoreboard #(USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE) sc;
2323

2424
// Constructor of environment.
2525
function new(string name, uvm_component parent);
@@ -51,7 +51,7 @@ class env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, PC
5151
m_config_rx.active = UVM_ACTIVE;
5252
m_config_rx.interface_name = "vif_rx";
5353
uvm_config_db #(uvm_dma_ll_rx::config_item)::set(this, "m_env_rx", "m_config", m_config_rx);
54-
m_env_rx = uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, CHANNELS, PKT_SIZE_MAX)::type_id::create("m_env_rx", this);
54+
m_env_rx = uvm_dma_ll_rx::env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX)::type_id::create("m_env_rx", this);
5555

5656
m_config_tx = new;
5757
m_config_tx.active = UVM_ACTIVE;
@@ -73,9 +73,9 @@ class env #(USER_REGIONS, USER_REGION_SIZE, USER_BLOCK_SIZE, USER_ITEM_WIDTH, PC
7373
uvm_config_db#(uvm_mi::regmodel_config)::set(this, "m_regmodel", "m_config", m_mi_config);
7474
m_regmodel = uvm_mi::regmodel#(regmodel#(CHANNELS), MI_WIDTH, MI_WIDTH)::type_id::create("m_regmodel", this);
7575

76-
sc = scoreboard #(CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE)::type_id::create("sc", this);
76+
sc = scoreboard #(USER_ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, PCIE_UP_META_WIDTH, DEVICE)::type_id::create("sc", this);
7777

78-
m_sequencer = sequencer#(PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS)::type_id::create("m_sequencer", this);
78+
m_sequencer = sequencer#(USER_ITEM_WIDTH, PCIE_UP_REGIONS, PCIE_UP_REGION_SIZE, PCIE_UP_BLOCK_SIZE, PCIE_UP_ITEM_WIDTH, PCIE_UP_META_WIDTH, CHANNELS)::type_id::create("m_sequencer", this);
7979
endfunction
8080

8181
// Connect agent's ports with ports from scoreboard.

‎comp/dma/dma_calypte/comp/rx/uvm/tbench/env/model.sv

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -78,20 +78,20 @@ class disc_probe_cbs extends uvm_probe::cbs_simple #(1);
7878
endfunction
7979
endclass
8080

81-
class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
82-
`uvm_component_param_utils(uvm_dma_ll::model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))
81+
class model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
82+
`uvm_component_param_utils(uvm_dma_ll::model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))
8383

8484
localparam USER_META_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);
8585
localparam IS_INTEL_DEV = (DEVICE == "STRATIX10" || DEVICE == "AGILEX");
8686

8787
//UVM PROBE - model input
8888
disc_probe_cbs uvm_probe_discard;
8989

90-
uvm_tlm_analysis_fifo #(uvm_byte_array::sequence_item) analysis_imp_rx;
91-
uvm_tlm_analysis_fifo #(uvm_logic_vector::sequence_item#(USER_META_WIDTH)) analysis_imp_rx_meta;
92-
model_accept#(CHANNELS) analysis_dma;
93-
uvm_analysis_port #(uvm_logic_vector_array::sequence_item#(32)) analysis_port_tx;
94-
uvm_analysis_port #(uvm_logic_vector::sequence_item#(META_WIDTH)) analysis_port_tx_meta;
90+
uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) analysis_imp_rx;
91+
uvm_tlm_analysis_fifo #(uvm_logic_vector::sequence_item#(USER_META_WIDTH)) analysis_imp_rx_meta;
92+
model_accept#(CHANNELS) analysis_dma;
93+
uvm_analysis_port #(uvm_logic_vector_array::sequence_item#(32)) analysis_port_tx;
94+
uvm_analysis_port #(uvm_logic_vector::sequence_item#(META_WIDTH)) analysis_port_tx_meta;
9595

9696
typedef struct{
9797
logic [$clog2(PKT_SIZE_MAX+1)-1:0] packet_size;
@@ -228,7 +228,7 @@ class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
228228
end
229229
endfunction
230230

231-
task packet_send(byte unsigned packet[], time start_time, int unsigned channel, logic [24-1:0] meta);
231+
task packet_send(logic [ITEM_WIDTH-1:0] packet[], time start_time, int unsigned channel, logic [24-1:0] meta);
232232
uvm_logic_vector::sequence_item#(META_WIDTH) packet_meta;
233233

234234
model_packet packet_output;
@@ -347,7 +347,7 @@ class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
347347
endfunction
348348

349349
task run_phase(uvm_phase phase);
350-
uvm_byte_array::sequence_item tr;
350+
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) tr;
351351
string msg;
352352
int unsigned compare;
353353
int unsigned soft_compare;

‎comp/dma/dma_calypte/comp/rx/uvm/tbench/env/scoreboard.sv

Lines changed: 18 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -4,63 +4,14 @@
44

55
//-- SPDX-License-Identifier: BSD-3-Clause
66

7-
class stats;
8-
9-
local real min;
10-
local real max;
11-
local real sum;
12-
local real sum2;
13-
14-
int unsigned values;
15-
16-
function new();
17-
values = 0;
18-
sum = 0;
19-
sum2 = 0;
20-
endfunction
21-
22-
23-
function void count(output real min, real max, real avg, real std_dev);
24-
real avg_local;
25-
26-
min = this.min;
27-
max = this.max;
28-
29-
avg_local = sum/values;
30-
avg = avg_local;
31-
32-
std_dev = (1.0/(values-1)*(sum2 - values*(avg_local**2)))**0.5;
33-
endfunction
34-
35-
function void next_val(real val);
36-
if (values == 0) begin
37-
min = val;
38-
max = val;
39-
end else begin
40-
if (min > val) begin
41-
min = val;
42-
end
43-
44-
if (max < val) begin
45-
max = val;
46-
end
47-
end
48-
49-
sum += val;
50-
sum2 += val**2;
51-
52-
values++;
53-
endfunction
54-
endclass
55-
56-
class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_scoreboard;
57-
`uvm_component_param_utils(uvm_dma_ll::scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))
7+
class scoreboard #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_scoreboard;
8+
`uvm_component_param_utils(uvm_dma_ll::scoreboard #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE))
589

5910
localparam LOGIC_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);
6011

6112
//INPUT TO DUT
62-
uvm_analysis_export #(uvm_byte_array::sequence_item) analysis_export_rx_packet;
63-
uvm_analysis_export #(uvm_logic_vector::sequence_item#(LOGIC_WIDTH)) analysis_export_rx_meta;
13+
uvm_analysis_export #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) analysis_export_rx_packet;
14+
uvm_analysis_export #(uvm_logic_vector::sequence_item#(LOGIC_WIDTH)) analysis_export_rx_meta;
6415

6516
//DUT WATCH INTERFACE
6617
uvm_analysis_export #(uvm_mvb::sequence_item#(1, 1)) analysis_export_dma;
@@ -74,13 +25,13 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
7425
local uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item#(32)) model_output;
7526
local uvm_tlm_analysis_fifo #(uvm_logic_vector::sequence_item#(META_WIDTH)) model_meta_output;
7627

77-
local model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) m_model;
28+
local model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) m_model;
7829
local regmodel#(CHANNELS) m_regmodel;
7930

80-
local stats m_input_speed;
81-
local uvm_tlm_analysis_fifo #(uvm_byte_array::sequence_item) rx_speed_meter;
82-
local stats m_delay;
83-
local stats m_output_speed;
31+
local uvm_common::stats m_input_speed;
32+
local uvm_tlm_analysis_fifo #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) rx_speed_meter;
33+
local uvm_common::stats m_delay;
34+
local uvm_common::stats m_output_speed;
8435
local int unsigned compared = 0;
8536
local int unsigned errors = 0;
8637
typedef struct{
@@ -123,7 +74,7 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
12374

12475
//build phase
12576
function void build_phase(uvm_phase phase);
126-
m_model = model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE)::type_id::create("m_model", this);
77+
m_model = model #(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE)::type_id::create("m_model", this);
12778
endfunction
12879

12980
function void connect_phase(uvm_phase phase);
@@ -179,7 +130,7 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
179130
time speed_start_time = 0ns;
180131

181132
forever begin
182-
uvm_byte_array::sequence_item tr;
133+
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) tr;
183134
time time_act;
184135
time speed_metet_duration;
185136
rx_speed_meter.get(tr);
@@ -275,6 +226,13 @@ class scoreboard #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_score
275226
end
276227
endtask
277228

229+
function void check_phase(uvm_phase phase);
230+
231+
if (dut_data_output.size() != 0 || dut_meta_output.size() != 0 || model_output.size() != 0 || model_meta_output.size() != 0) begin
232+
`uvm_error(this.get_full_name(), $sformatf("\nExpected some data\n\tMODELs data Packets(%0d) meta(%0d)\n\tDUTs data packets(%0d) meta(%0d)", model_output.size(), model_meta_output.size(), dut_data_output.size(), dut_meta_output.size()));
233+
end
234+
endfunction
235+
278236
function void report_phase(uvm_phase phase);
279237
real min;
280238
real max;

‎comp/dma/dma_calypte/comp/rx/uvm/tbench/env/sequencer.sv

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44

55
//-- SPDX-License-Identifier: BSD-3-Clause
66

7-
class sequencer#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH, CHANNELS) extends uvm_sequencer;
8-
`uvm_component_param_utils(uvm_dma_ll::sequencer#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH, CHANNELS))
7+
class sequencer#(USR_ITEM_WIDTH, PCIE_REGIONS, PCIE_REGION_SIZE, PCIE_BLOCK_SIZE, PCIE_ITEM_WIDTH, PCIE_META_WIDTH, CHANNELS) extends uvm_sequencer;
8+
`uvm_component_param_utils(uvm_dma_ll::sequencer#(USR_ITEM_WIDTH, PCIE_REGIONS, PCIE_REGION_SIZE, PCIE_BLOCK_SIZE, PCIE_ITEM_WIDTH, PCIE_META_WIDTH, CHANNELS))
99

1010
uvm_reset::sequencer m_reset;
11-
uvm_dma_ll_rx::sequencer m_packet;
12-
uvm_mfb::sequencer #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH) m_pcie;
11+
uvm_dma_ll_rx::sequencer#(USR_ITEM_WIDTH) m_packet;
12+
uvm_mfb::sequencer #(PCIE_REGIONS, PCIE_REGION_SIZE, PCIE_BLOCK_SIZE, PCIE_ITEM_WIDTH, PCIE_META_WIDTH) m_pcie;
1313
uvm_dma_ll::regmodel #(CHANNELS) m_regmodel;
1414

1515
function new(string name = "virt_sequencer", uvm_component parent);

‎comp/dma/dma_calypte/comp/rx/uvm/tbench/rx_env/driver.sv

Lines changed: 19 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -5,42 +5,40 @@
55
//-- SPDX-License-Identifier: BSD-3-Clause
66

77

8-
class driver#(CHANNELS, PKT_SIZE_MAX) extends uvm_component;
9-
`uvm_component_param_utils(uvm_dma_ll_rx::driver#(CHANNELS, PKT_SIZE_MAX))
8+
class driver#(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX) extends uvm_component;
9+
`uvm_component_param_utils(uvm_dma_ll_rx::driver#(ITEM_WIDTH, CHANNELS, PKT_SIZE_MAX))
1010

1111
localparam MFB_META_WIDTH = 24 + $clog2(PKT_SIZE_MAX+1) + $clog2(CHANNELS);
1212

13-
uvm_seq_item_pull_port #(uvm_byte_array::sequence_item, uvm_byte_array::sequence_item) seq_item_port_byte_array;
13+
uvm_seq_item_pull_port #(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH), uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) seq_item_port_logic_vector_array;
1414

15-
mailbox#(uvm_byte_array::sequence_item) byte_array_export;
16-
mailbox#(uvm_logic_vector::sequence_item#(MFB_META_WIDTH)) logic_vector_export;
17-
local semaphore sem;
15+
mailbox#(uvm_logic_vector_array::sequence_item#(ITEM_WIDTH)) logic_vector_array_export;
16+
mailbox#(uvm_logic_vector::sequence_item#(MFB_META_WIDTH)) logic_vector_export;
1817

1918
// ------------------------------------------------------------------------
2019
// Constructor
2120
function new(string name, uvm_component parent);
2221
super.new(name, parent);
2322

24-
seq_item_port_byte_array = new("seq_item_port_byte_array", this);
23+
seq_item_port_logic_vector_array = new("seq_item_port_logic_vector_array", this);
2524

26-
byte_array_export = new(1);
27-
logic_vector_export = new(1);
28-
sem = new(1);
25+
logic_vector_array_export = new(1);
26+
logic_vector_export = new(1);
2927
endfunction
3028

3129
function int unsigned used();
3230
int unsigned ret = 0;
33-
ret |= (byte_array_export.num() != 0);
31+
ret |= (logic_vector_array_export.num() != 0);
3432
ret |= (logic_vector_export.num() != 0);
3533
return ret;
3634
endfunction
3735

3836
// ------------------------------------------------------------------------
3937
// Starts driving signals to interface
4038
task run_phase(uvm_phase phase);
41-
uvm_byte_array::sequence_item byte_array_req;
42-
uvm_byte_array::sequence_item byte_array_new;
43-
uvm_logic_vector::sequence_item#(MFB_META_WIDTH) logic_vector_new;
39+
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) logic_vector_array_req;
40+
uvm_logic_vector_array::sequence_item#(ITEM_WIDTH) logic_vector_array_new;
41+
uvm_logic_vector::sequence_item#(MFB_META_WIDTH) logic_vector_new;
4442

4543
logic [$clog2(PKT_SIZE_MAX+1)-1:0] packet_size;
4644
int unsigned channel;
@@ -49,12 +47,12 @@ class driver#(CHANNELS, PKT_SIZE_MAX) extends uvm_component;
4947

5048
forever begin
5149
// Get new sequence item to drive to interface
52-
seq_item_port_byte_array.get_next_item(byte_array_req);
50+
seq_item_port_logic_vector_array.get_next_item(logic_vector_array_req);
5351

5452
msg = {msg, $sformatf("-------------------------------------------------------\n")};
5553
msg = {msg, $sformatf("DRIVER: Got new transaction:\n")};
5654
msg = {msg, $sformatf("-------------------------------------------------------\n")};
57-
msg = {msg, $sformatf("%s\n", byte_array_req.convert2string())};
55+
msg = {msg, $sformatf("%s\n", logic_vector_array_req.convert2string())};
5856

5957

6058
assert(std::randomize(channel) with {channel >= 0; channel < CHANNELS;});
@@ -63,21 +61,19 @@ class driver#(CHANNELS, PKT_SIZE_MAX) extends uvm_component;
6361
msg = {msg, $sformatf("\nChannel: %0d\n", channel)};
6462
msg = {msg, $sformatf("Meta: 0x%x\n", meta)};
6563

66-
$cast(byte_array_new, byte_array_req.clone());
64+
$cast(logic_vector_array_new, logic_vector_array_req.clone());
6765
logic_vector_new = uvm_logic_vector::sequence_item#(MFB_META_WIDTH)::type_id::create("logic_vector_new");
68-
packet_size = byte_array_new.data.size();
66+
packet_size = logic_vector_array_new.data.size();
6967
logic_vector_new.data = {packet_size, channel, meta};
7068
msg = {msg, $sformatf("Pkt size: %0d\n", packet_size)};
7169

7270
`uvm_info(this.get_full_name(), msg, UVM_HIGH);
7371

74-
wait(byte_array_export.num() == 0 || logic_vector_export.num() == 0);
75-
sem.get(1);
76-
byte_array_export.put(byte_array_new);
72+
wait(logic_vector_array_export.num() == 0 || logic_vector_export.num() == 0);
73+
logic_vector_array_export.put(logic_vector_array_new);
7774
logic_vector_export.put(logic_vector_new);
78-
sem.put(1);
7975

80-
seq_item_port_byte_array.item_done();
76+
seq_item_port_logic_vector_array.item_done();
8177
end
8278
endtask
8379

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