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‎devel/ndk_core/comp/eth/network_mod/readme.html‎

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@@ -269,12 +269,17 @@ <h2>Entity Docs<a class="headerlink" href="#entity-docs" title="Link to this hea
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<td><p>(others =&gt; 16383)</p></td>
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<td><p>Maximum allowed size of TX frame in bytes per Ethernet port.</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-eth_mac_bypass"><td><p>ETH_MAC_BYPASS</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-eth_chan_map"><td><p>ETH_CHAN_MAP</p></td>
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<td><p>integer_vector(7 downto 0)</p></td>
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<td><p>(7, 6, 5, 4, 3, 2, 1, 0)</p></td>
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<td><p>Optional remapping of physical QSFP(DD) lanes to Eth channel numbers</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-eth_mac_bypass"><td><p>ETH_MAC_BYPASS</p></td>
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<td><p>boolean</p></td>
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<td><p>False</p></td>
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<td><p>Optional option to disable MAC Lite modules. Dangerously!</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-lanes"><td><p>LANES</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-lanes"><td><p>LANES</p></td>
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<td><p>natural</p></td>
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<td><p>4</p></td>
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<td><p>Number of serial lanes.
@@ -284,27 +289,27 @@ <h2>Entity Docs<a class="headerlink" href="#entity-docs" title="Link to this hea
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</div></blockquote>
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</td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-qsfp_ports"><td><p>QSFP_PORTS</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-qsfp_ports"><td><p>QSFP_PORTS</p></td>
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<td><p>natural</p></td>
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<td><p>2</p></td>
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<td></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-qsfp_i2c_ports"><td><p>QSFP_I2C_PORTS</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-qsfp_i2c_ports"><td><p>QSFP_I2C_PORTS</p></td>
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<td><p>natural</p></td>
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<td><p>1</p></td>
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<td><p>max 2</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-qsfp_i2c_tristate"><td><p>QSFP_I2C_TRISTATE</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-qsfp_i2c_tristate"><td><p>QSFP_I2C_TRISTATE</p></td>
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<td><p>boolean</p></td>
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<td><p>true</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>=====</p></td>
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<tr class="row-odd"><td><p>=====</p></td>
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<td><p>MFB configuration:</p></td>
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<td><p>=====</p></td>
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<td><p>=====</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-regions"><td><p>REGIONS</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-regions"><td><p>REGIONS</p></td>
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<td><p>natural</p></td>
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<td><p>1</p></td>
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<td><dl class="simple">
@@ -314,52 +319,52 @@ <h2>Entity Docs<a class="headerlink" href="#entity-docs" title="Link to this hea
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</dl>
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</td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-region_size"><td><p>REGION_SIZE</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-region_size"><td><p>REGION_SIZE</p></td>
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<td><p>natural</p></td>
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<td><p>8</p></td>
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<td></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-block_size"><td><p>BLOCK_SIZE</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-block_size"><td><p>BLOCK_SIZE</p></td>
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<td><p>natural</p></td>
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<td><p>8</p></td>
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<td></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-item_width"><td><p>ITEM_WIDTH</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-item_width"><td><p>ITEM_WIDTH</p></td>
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<td><p>natural</p></td>
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<td><p>8</p></td>
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<td></td>
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</tr>
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<tr class="row-odd"><td><p>=====</p></td>
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<tr class="row-even"><td><p>=====</p></td>
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<td><p>MI configuration:</p></td>
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<td><p>=====</p></td>
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<td><p>=====</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-mi_data_width"><td><p>MI_DATA_WIDTH</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-mi_data_width"><td><p>MI_DATA_WIDTH</p></td>
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<td><p>natural</p></td>
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<td><p>32</p></td>
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<td></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-mi_addr_width"><td><p>MI_ADDR_WIDTH</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-mi_addr_width"><td><p>MI_ADDR_WIDTH</p></td>
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<td><p>natural</p></td>
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<td><p>32</p></td>
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<td></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-mi_data_width_phy"><td><p>MI_DATA_WIDTH_PHY</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-mi_data_width_phy"><td><p>MI_DATA_WIDTH_PHY</p></td>
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<td><p>natural</p></td>
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<td><p>32</p></td>
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<td></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-mi_addr_width_phy"><td><p>MI_ADDR_WIDTH_PHY</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-mi_addr_width_phy"><td><p>MI_ADDR_WIDTH_PHY</p></td>
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<td><p>natural</p></td>
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<td><p>32</p></td>
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<td></td>
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</tr>
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<tr class="row-even"><td><p>=====</p></td>
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<tr class="row-odd"><td><p>=====</p></td>
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<td><p>Other configuration:</p></td>
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<td><p>=====</p></td>
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<td><p>=====</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-ts_demo_en"><td><p>TS_DEMO_EN</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-ts_demo_en"><td><p>TS_DEMO_EN</p></td>
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<td><p>boolean</p></td>
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<td><p>false</p></td>
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<td><p>Enable timestamp-limiting demo/testing.
@@ -369,47 +374,47 @@ <h2>Entity Docs<a class="headerlink" href="#entity-docs" title="Link to this hea
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The measured data is presented to the user via a couple of dedicated registers.
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WARNING: works only for a single-channel (and single-Region) designs with E-Tile (Intel)!</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-tx_dma_channels"><td><p>TX_DMA_CHANNELS</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-tx_dma_channels"><td><p>TX_DMA_CHANNELS</p></td>
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<td><p>natural</p></td>
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<td><p>16</p></td>
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<td><p>TX_DMA_CHANNELS per Eth Stream!</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-ll_mode"><td><p>LL_MODE</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-ll_mode"><td><p>LL_MODE</p></td>
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<td><p>boolean</p></td>
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<td><p>false</p></td>
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<td><p>Enable low latency optimalization</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-lane_rx_polarity"><td><p>LANE_RX_POLARITY</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-lane_rx_polarity"><td><p>LANE_RX_POLARITY</p></td>
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<td><p>std_logic_vector(ETH_PORTS*LANES-1 downto 0)</p></td>
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<td><p>(others =&gt; ‘0’)</p></td>
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<td><p>Ethernet lanes polarity</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-lane_tx_polarity"><td><p>LANE_TX_POLARITY</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-lane_tx_polarity"><td><p>LANE_TX_POLARITY</p></td>
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<td><p>std_logic_vector(ETH_PORTS*LANES-1 downto 0)</p></td>
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<td><p>(others =&gt; ‘0’)</p></td>
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<td></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-reset_width"><td><p>RESET_WIDTH</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-reset_width"><td><p>RESET_WIDTH</p></td>
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<td><p>natural</p></td>
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<td><p>8</p></td>
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<td><p>Number of user resets.</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-misc_top2net_width"><td><p>MISC_TOP2NET_WIDTH</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-misc_top2net_width"><td><p>MISC_TOP2NET_WIDTH</p></td>
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<td><p>natural</p></td>
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<td><p>1</p></td>
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<td><p>Width of MISC signal between Top-Level FPGA design and NET_MOD core logic</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-misc_net2top_width"><td><p>MISC_NET2TOP_WIDTH</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-misc_net2top_width"><td><p>MISC_NET2TOP_WIDTH</p></td>
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<td><p>natural</p></td>
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<td><p>1</p></td>
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<td><p>Width of MISC signal between NET_MOD core logic and Top-Level FPGA design</p></td>
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</tr>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-device"><td><p>DEVICE</p></td>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-device"><td><p>DEVICE</p></td>
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<td><p>string</p></td>
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<td><p>“STRATIX10”</p></td>
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<td><p>Select correct FPGA device.</p></td>
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</tr>
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<tr class="row-even" id="vhdl-gengeneric-network_mod-board"><td><p>BOARD</p></td>
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<tr class="row-odd" id="vhdl-gengeneric-network_mod-board"><td><p>BOARD</p></td>
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<td><p>string</p></td>
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<td><p>“DK-DEV-1SDX-P”</p></td>
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<td><p>400G1, DK-DEV-AGI027RES, DK-DEV-1SDX-P</p></td>

‎devel/objects.inv‎

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‎devel/searchindex.js‎

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