MISC_TOP2NET_WIDTH
natural
1
Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
MISC_NET2TOP_WIDTH
natural
1
Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
DEVICE
string
βSTRATIX10β
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MISC SIGNALS (the clock signal is not defined)
=====
=====
MISC_TOP2NET
slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0)
in
Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
MISC_NET2TOP
slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0)
out
Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
MISC_TOP2APP_WIDTH
natural
1
Width of MISC signal between Top-Level FPGA design and APP core logic
MISC_APP2TOP_WIDTH
natural
1
Width of MISC signal between APP core logic and Top-Level FPGA design
BOARD
string
UNDEFINED
=====
MISC SIGNALS (the clock signal is not defined)
=====
=====
MISC_TOP2APP
std_logic_vector(MISC_TOP2APP_WIDTH-1 downto 0)
in
Optional signal for MISC connection from Top-Level FPGA design to APP core.
MISC_APP2TOP
std_logic_vector(MISC_APP2TOP_WIDTH-1 downto 0)
out
Optional signal for MISC connection from APP core to Top-Level FPGA design.