From e4adf6a8d6b244cdad76737840d379e18a872363 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Thu, 6 Feb 2025 13:20:15 +0100 Subject: [PATCH 1/7] feat(core): propagate the PCIE_GEN parameter to the PCIE_CORE module --- core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd | 2 ++ core/comp/pcie/pcie_mod/pcie_top.vhd | 3 +++ core/top/fpga_common.vhd | 1 + 3 files changed, 6 insertions(+) diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd index 9bb04a193..7e18ae2de 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd @@ -49,6 +49,8 @@ entity PCIE_CORE is PCIE_CONS : natural := 1; -- Number of PCIe lanes in each PCIe connector PCIE_LANES : natural := 16; + -- PCIe generation number + PCIE_GEN : natural := 4; -- ===================================================================== -- Other configuration diff --git a/core/comp/pcie/pcie_mod/pcie_top.vhd b/core/comp/pcie/pcie_mod/pcie_top.vhd index f2699cfb9..87ffb96d6 100644 --- a/core/comp/pcie/pcie_mod/pcie_top.vhd +++ b/core/comp/pcie/pcie_mod/pcie_top.vhd @@ -63,6 +63,8 @@ entity PCIE is PCIE_CONS : natural := 1; -- Number of PCIe lanes in each PCIe connector PCIE_LANES : natural := 16; + -- PCIe generation number + PCIE_GEN : natural := 4; -- Width of CARD/FPGA ID number CARD_ID_WIDTH : natural := 0; -- Disable PTC module and allows direct connection of the DMA module to @@ -386,6 +388,7 @@ begin PCIE_CLKS => PCIE_CLKS, PCIE_CONS => PCIE_CONS, PCIE_LANES => PCIE_LANES, + PCIE_GEN => PCIE_GEN, MI_WIDTH => 32, XVC_ENABLE => XVC_ENABLE, CARD_ID_WIDTH => CARD_ID_WIDTH, diff --git a/core/top/fpga_common.vhd b/core/top/fpga_common.vhd index c6851c62a..26e0a11c0 100644 --- a/core/top/fpga_common.vhd +++ b/core/top/fpga_common.vhd @@ -814,6 +814,7 @@ begin PCIE_CLKS => PCIE_CLKS, PCIE_CONS => PCIE_CONS, PCIE_LANES => PCIE_LANES, + PCIE_GEN => PCIE_GEN, PTC_DISABLE => not PTC_ENABLE, DMA_BAR_ENABLE => (DMA_TYPE = 4), From 462eaef3aca4c41f40ce94d55a6c8ef27c9ae427 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Thu, 6 Feb 2025 14:00:41 +0100 Subject: [PATCH 2/7] fix(core): fix multi-region support in DMA Calypte wrapper --- .../wrapper/dma_calypte_wrapper_arch.vhd | 81 +++++++++++++------ 1 file changed, 56 insertions(+), 25 deletions(-) diff --git a/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd b/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd index 9e3173b61..8327d7742 100644 --- a/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd +++ b/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd @@ -37,6 +37,9 @@ architecture CALYPTE of DMA_WRAPPER is 1 => X"00300000"); -- DMA Test Core constant MI_SPLIT_ADDR_MASK : std_logic_vector(MI_WIDTH -1 downto 0) := X"00300000"; + constant DMA_RX_META_SIZE : natural := log2(USR_RX_PKT_SIZE_MAX+1)+log2(RX_CHANNELS)+HDR_META_WIDTH; + constant DMA_TX_META_SIZE : natural := log2(USR_TX_PKT_SIZE_MAX+1)+log2(TX_CHANNELS)+HDR_META_WIDTH; + constant DMA_MFB_REGIONS : integer := 1; constant DMA_MFB_REGION_SIZE : integer := PCIE_RQ_MFB_REGIONS*4; constant DMA_MFB_BLOCK_SIZE : integer := 8; @@ -62,12 +65,17 @@ architecture CALYPTE of DMA_WRAPPER is signal mi_sync_ardy : std_logic_vector(PCIE_ENDPOINTS-1 downto 0); signal mi_sync_drdy : std_logic_vector(PCIE_ENDPOINTS-1 downto 0); + signal rx_usr_mvb_meta : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MVB_ITEMS*DMA_RX_META_SIZE-1 downto 0); + signal rx_usr_mvb_meta_arr : slv_array_2d_t(DMA_STREAMS-1 downto 0)(USR_MVB_ITEMS-1 downto 0)(DMA_RX_META_SIZE-1 downto 0); + signal rx_usr_mvb_len_arr : slv_array_2d_t(DMA_STREAMS -1 downto 0)(USR_MVB_ITEMS-1 downto 0)(log2(USR_RX_PKT_SIZE_MAX+1)-1 downto 0); + signal rx_usr_mvb_hdr_meta_arr : slv_array_2d_t(DMA_STREAMS -1 downto 0)(USR_MVB_ITEMS-1 downto 0)(HDR_META_WIDTH-1 downto 0); + signal rx_usr_mvb_channel_arr : slv_array_2d_t(DMA_STREAMS -1 downto 0)(USR_MVB_ITEMS-1 downto 0)(log2(RX_CHANNELS)-1 downto 0); --============================================================================================== -- Metadata insertor ---> FIFOX --============================================================================================== signal rx_usr_mfb_data_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS*USR_MFB_REGION_SIZE*USR_MFB_BLOCK_SIZE*USR_MFB_ITEM_WIDTH -1 downto 0); - signal rx_usr_mfb_meta_res : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_RX_PKT_SIZE_MAX +1)+log2(RX_CHANNELS)+HDR_META_WIDTH -1 downto 0); + signal rx_usr_mfb_meta_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS*DMA_RX_META_SIZE -1 downto 0); signal rx_usr_mfb_sof_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS -1 downto 0); signal rx_usr_mfb_eof_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS -1 downto 0); signal rx_usr_mfb_sof_pos_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS*max(1,log2(USR_MFB_REGION_SIZE)) -1 downto 0); @@ -76,7 +84,7 @@ architecture CALYPTE of DMA_WRAPPER is signal rx_usr_mfb_dst_rdy_res : std_logic_vector(DMA_STREAMS-1 downto 0); signal rx_usr_mfb_data_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_MFB_REGION_SIZE*DMA_MFB_BLOCK_SIZE*DMA_MFB_ITEM_WIDTH -1 downto 0); - signal rx_usr_mfb_meta_async : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_RX_PKT_SIZE_MAX +1)+log2(RX_CHANNELS)+HDR_META_WIDTH -1 downto 0); + signal rx_usr_mfb_meta_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_RX_META_SIZE -1 downto 0); signal rx_usr_mfb_sof_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal rx_usr_mfb_eof_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal rx_usr_mfb_sof_pos_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*max(1,log2(DMA_MFB_REGION_SIZE)) -1 downto 0); @@ -88,7 +96,7 @@ architecture CALYPTE of DMA_WRAPPER is -- FIFOX ---> Metadata extractor --============================================================================================== signal tx_usr_mfb_data_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS*USR_MFB_REGION_SIZE*USR_MFB_BLOCK_SIZE*USR_MFB_ITEM_WIDTH-1 downto 0); - signal tx_usr_mfb_meta_res : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_TX_PKT_SIZE_MAX+1)+HDR_META_WIDTH+log2(TX_CHANNELS) -1 downto 0); + signal tx_usr_mfb_meta_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS*DMA_TX_META_SIZE -1 downto 0); signal tx_usr_mfb_sof_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS -1 downto 0); signal tx_usr_mfb_eof_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS -1 downto 0); signal tx_usr_mfb_sof_pos_res : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MFB_REGIONS*max(1,log2(USR_MFB_REGION_SIZE)) -1 downto 0); @@ -97,7 +105,7 @@ architecture CALYPTE of DMA_WRAPPER is signal tx_usr_mfb_dst_rdy_res : std_logic_vector(DMA_STREAMS-1 downto 0); signal tx_usr_mfb_data_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_MFB_REGION_SIZE*DMA_MFB_BLOCK_SIZE*DMA_MFB_ITEM_WIDTH-1 downto 0); - signal tx_usr_mfb_meta_async : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_TX_PKT_SIZE_MAX+1)+HDR_META_WIDTH+log2(TX_CHANNELS) -1 downto 0); + signal tx_usr_mfb_meta_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_TX_META_SIZE -1 downto 0); signal tx_usr_mfb_sof_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal tx_usr_mfb_eof_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal tx_usr_mfb_sof_pos_async : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*max(1,log2(DMA_MFB_REGION_SIZE)) -1 downto 0); @@ -109,7 +117,7 @@ architecture CALYPTE of DMA_WRAPPER is -- MFB ASFIFOX ---> Testing Module interface --============================================================================================== signal rx_usr_mfb_data_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_MFB_REGION_SIZE*DMA_MFB_BLOCK_SIZE*DMA_MFB_ITEM_WIDTH-1 downto 0); - signal rx_usr_mfb_meta_sync : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_RX_PKT_SIZE_MAX+1)+HDR_META_WIDTH+log2(RX_CHANNELS) -1 downto 0); + signal rx_usr_mfb_meta_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_RX_META_SIZE -1 downto 0); signal rx_usr_mfb_sof_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal rx_usr_mfb_eof_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal rx_usr_mfb_sof_pos_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*max(1,log2(DMA_MFB_REGION_SIZE)) -1 downto 0); @@ -121,7 +129,7 @@ architecture CALYPTE of DMA_WRAPPER is -- Testing Module ---> MFB ASFIFOX interface --============================================================================================== signal tx_usr_mfb_data_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_MFB_REGION_SIZE*DMA_MFB_BLOCK_SIZE*DMA_MFB_ITEM_WIDTH-1 downto 0); - signal tx_usr_mfb_meta_sync : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_TX_PKT_SIZE_MAX+1)+HDR_META_WIDTH+log2(TX_CHANNELS) -1 downto 0); + signal tx_usr_mfb_meta_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_TX_META_SIZE -1 downto 0); signal tx_usr_mfb_sof_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal tx_usr_mfb_eof_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); signal tx_usr_mfb_sof_pos_sync : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*max(1,log2(DMA_MFB_REGION_SIZE)) -1 downto 0); @@ -132,8 +140,8 @@ architecture CALYPTE of DMA_WRAPPER is --============================================================================================== -- Testing Module ---> DMA Module interface --============================================================================================== - signal rx_usr_mfb_meta_hdr_meta_tst : slv_array_t(DMA_STREAMS-1 downto 0)(HDR_META_WIDTH -1 downto 0); - signal rx_usr_mfb_meta_channel_tst : slv_array_t(DMA_STREAMS-1 downto 0)(log2(RX_CHANNELS) -1 downto 0); + signal rx_usr_mfb_meta_hdr_meta_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*HDR_META_WIDTH -1 downto 0); + signal rx_usr_mfb_meta_channel_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*log2(RX_CHANNELS)-1 downto 0); signal rx_usr_mfb_data_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_MFB_REGION_SIZE*DMA_MFB_BLOCK_SIZE*DMA_MFB_ITEM_WIDTH-1 downto 0); signal rx_usr_mfb_sof_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); @@ -146,9 +154,9 @@ architecture CALYPTE of DMA_WRAPPER is --============================================================================================== -- DMA Module ---> Testing Module interface --============================================================================================== - signal tx_usr_mfb_meta_size_tst : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_TX_PKT_SIZE_MAX+1)-1 downto 0); - signal tx_usr_mfb_meta_hdr_meta_tst : slv_array_t(DMA_STREAMS-1 downto 0)(HDR_META_WIDTH -1 downto 0); - signal tx_usr_mfb_meta_channel_tst : slv_array_t(DMA_STREAMS-1 downto 0)(log2(TX_CHANNELS) -1 downto 0); + signal tx_usr_mfb_meta_size_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*log2(USR_TX_PKT_SIZE_MAX+1)-1 downto 0); + signal tx_usr_mfb_meta_hdr_meta_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*HDR_META_WIDTH -1 downto 0); + signal tx_usr_mfb_meta_channel_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*log2(TX_CHANNELS) -1 downto 0); signal tx_usr_mfb_data_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS*DMA_MFB_REGION_SIZE*DMA_MFB_BLOCK_SIZE*DMA_MFB_ITEM_WIDTH-1 downto 0); signal tx_usr_mfb_sof_tst : slv_array_t(DMA_STREAMS-1 downto 0)(DMA_MFB_REGIONS -1 downto 0); @@ -184,17 +192,22 @@ architecture CALYPTE of DMA_WRAPPER is --============================================================================================== -- concatenated metadata on the output of the metadata extractor to be split into output -- TX_USR_MVB_* signals - signal tx_usr_mvb_data_all : slv_array_t(DMA_STREAMS-1 downto 0)(log2(USR_TX_PKT_SIZE_MAX +1)+log2(TX_CHANNELS)+HDR_META_WIDTH -1 downto 0); + signal tx_usr_mvb_data_all : slv_array_t(DMA_STREAMS-1 downto 0)(USR_MVB_ITEMS*DMA_TX_META_SIZE-1 downto 0); + signal tx_usr_mvb_data_arr : slv_array_2d_t(DMA_STREAMS-1 downto 0)(USR_MVB_ITEMS-1 downto 0)(DMA_TX_META_SIZE-1 downto 0); + + signal tx_usr_mvb_len_arr : slv_array_2d_t(DMA_STREAMS -1 downto 0)(USR_MVB_ITEMS-1 downto 0)(log2(USR_TX_PKT_SIZE_MAX+1) -1 downto 0); + signal tx_usr_mvb_hdr_meta_arr : slv_array_2d_t(DMA_STREAMS -1 downto 0)(USR_MVB_ITEMS-1 downto 0)(HDR_META_WIDTH -1 downto 0); + signal tx_usr_mvb_channel_arr : slv_array_2d_t(DMA_STREAMS -1 downto 0)(USR_MVB_ITEMS-1 downto 0)(log2(TX_CHANNELS) -1 downto 0); -- ============================================================================================= -- Debugging signals -- ============================================================================================= - signal st_sp_dbg_chan : slv_array_t(DMA_STREAMS -1 downto 0)(log2(TX_CHANNELS) -1 downto 0); - signal st_sp_dbg_meta : slv_array_t(DMA_STREAMS -1 downto 0)(ST_SP_DBG_META_WIDTH -1 downto 0); + signal st_sp_dbg_chan : slv_array_t(DMA_STREAMS -1 downto 0)(DMA_MFB_REGIONS*log2(TX_CHANNELS) -1 downto 0); + signal st_sp_dbg_meta : slv_array_t(DMA_STREAMS -1 downto 0)(DMA_MFB_REGIONS*ST_SP_DBG_META_WIDTH -1 downto 0); signal force_reset_dbg : std_logic_vector(DMA_STREAMS-1 downto 0); begin - assert (DMA_STREAMS = DMA_ENDPOINTS and DMA_STREAMS = PCIE_ENDPOINTS) + assert (DMA_STREAMS = PCIE_ENDPOINTS) report "DMA_WRAPPER(CALYPTE): This DMA core does not support multiple DMA endpoints. Only one DMA Module is allowed per PCIE endpoint" severity FAILURE; @@ -278,10 +291,21 @@ begin --========================================================================================== -- Metadata Insertor/Extractor --========================================================================================== + + rx_usr_mvb_len_arr(i) <= slv_array_deser(RX_USR_MVB_LEN(i), USR_MVB_ITEMS); + rx_usr_mvb_hdr_meta_arr(i) <= slv_array_deser(RX_USR_MVB_HDR_META(i), USR_MVB_ITEMS); + rx_usr_mvb_channel_arr(i) <= slv_array_deser(RX_USR_MVB_CHANNEL(i), USR_MVB_ITEMS); + + rx_usr_meta_g: for rr in 0 to USR_MVB_ITEMS-1 generate + rx_usr_mvb_meta_arr(i)(rr) <= rx_usr_mvb_len_arr(i)(rr) & rx_usr_mvb_hdr_meta_arr(i)(rr) & rx_usr_mvb_channel_arr(i)(rr); + end generate; + + rx_usr_mvb_meta(i) <= slv_array_ser(rx_usr_mvb_meta_arr(i)); + usr_rx_dma_meta_insert_i : entity work.METADATA_INSERTOR generic map ( MVB_ITEMS => USR_MVB_ITEMS, - MVB_ITEM_WIDTH => log2(USR_RX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(RX_CHANNELS), + MVB_ITEM_WIDTH => DMA_RX_META_SIZE, MFB_REGIONS => USR_MFB_REGIONS, MFB_REGION_SIZE => USR_MFB_REGION_SIZE, MFB_BLOCK_SIZE => USR_MFB_BLOCK_SIZE, @@ -294,7 +318,7 @@ begin CLK => USR_CLK, RESET => USR_RESET, - RX_MVB_DATA => RX_USR_MVB_LEN(i) & RX_USR_MVB_HDR_META(i) & RX_USR_MVB_CHANNEL(i) , + RX_MVB_DATA => rx_usr_mvb_meta(i), RX_MVB_VLD => RX_USR_MVB_VLD(i), RX_MVB_SRC_RDY => RX_USR_MVB_SRC_RDY(i), RX_MVB_DST_RDY => RX_USR_MVB_DST_RDY(i), @@ -325,7 +349,7 @@ begin MFB_REGION_SIZE => USR_MFB_REGION_SIZE, MFB_BLOCK_SIZE => USR_MFB_BLOCK_SIZE, MFB_ITEM_WIDTH => USR_MFB_ITEM_WIDTH, - MFB_META_WIDTH => log2(USR_TX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(TX_CHANNELS), + MFB_META_WIDTH => DMA_TX_META_SIZE, EXTRACT_MODE => 0, OUT_MVB_PIPE_EN => FALSE, OUT_MFB_PIPE_EN => FALSE, @@ -357,9 +381,16 @@ begin TX_MFB_SRC_RDY => TX_USR_MFB_SRC_RDY(i), TX_MFB_DST_RDY => TX_USR_MFB_DST_RDY(i)); - TX_USR_MVB_LEN(i) <= tx_usr_mvb_data_all(i)(log2(USR_TX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(TX_CHANNELS) -1 downto HDR_META_WIDTH + log2(TX_CHANNELS)); - TX_USR_MVB_HDR_META(i) <= tx_usr_mvb_data_all(i)(HDR_META_WIDTH + log2(TX_CHANNELS) -1 downto log2(TX_CHANNELS)); - TX_USR_MVB_CHANNEL(i) <= tx_usr_mvb_data_all(i)(log2(TX_CHANNELS) -1 downto 0); + tx_usr_mvb_data_arr(i) <= slv_array_deser(tx_usr_mvb_data_all(i), USR_MVB_ITEMS); + tx_usr_meta_g: for rr in 0 to USR_MVB_ITEMS-1 generate + tx_usr_mvb_len_arr(i)(rr) <= tx_usr_mvb_data_arr(i)(rr)(log2(USR_TX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(TX_CHANNELS) -1 downto HDR_META_WIDTH + log2(TX_CHANNELS)); + tx_usr_mvb_hdr_meta_arr(i)(rr) <= tx_usr_mvb_data_arr(i)(rr)(HDR_META_WIDTH + log2(TX_CHANNELS) -1 downto log2(TX_CHANNELS)); + tx_usr_mvb_channel_arr(i)(rr) <= tx_usr_mvb_data_arr(i)(rr)(log2(TX_CHANNELS) -1 downto 0); + end generate; + + TX_USR_MVB_LEN(i) <= slv_array_ser(tx_usr_mvb_len_arr(i)); + TX_USR_MVB_HDR_META(i) <= slv_array_ser(tx_usr_mvb_hdr_meta_arr(i)); + TX_USR_MVB_CHANNEL(i) <= slv_array_ser(tx_usr_mvb_channel_arr(i)); --========================================================================================== -- Reconfig @@ -375,7 +406,7 @@ begin TX_REGION_SIZE => DMA_MFB_REGION_SIZE, TX_BLOCK_SIZE => DMA_MFB_BLOCK_SIZE, TX_ITEM_WIDTH => DMA_MFB_ITEM_WIDTH, - META_WIDTH => log2(USR_RX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(RX_CHANNELS), + META_WIDTH => DMA_RX_META_SIZE, META_MODE => 0, FIFO_SIZE => 32, FRAMES_OVER_TX_BLOCK => 0, @@ -414,7 +445,7 @@ begin TX_REGION_SIZE => USR_MFB_REGION_SIZE, TX_BLOCK_SIZE => USR_MFB_BLOCK_SIZE, TX_ITEM_WIDTH => USR_MFB_ITEM_WIDTH, - META_WIDTH => log2(USR_TX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(TX_CHANNELS), + META_WIDTH => DMA_TX_META_SIZE, META_MODE => 0, FIFO_SIZE => 32, FRAMES_OVER_TX_BLOCK => 0, @@ -458,7 +489,7 @@ begin RAM_TYPE => "BRAM", FWFT_MODE => TRUE, OUTPUT_REG => FALSE, - METADATA_WIDTH => log2(USR_RX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(RX_CHANNELS), + METADATA_WIDTH => DMA_RX_META_SIZE, DEVICE => DEVICE, ALMOST_FULL_OFFSET => 2, ALMOST_EMPTY_OFFSET => 2) @@ -512,7 +543,7 @@ begin RAM_TYPE => "BRAM", FWFT_MODE => TRUE, OUTPUT_REG => FALSE, - METADATA_WIDTH => log2(USR_TX_PKT_SIZE_MAX + 1) + HDR_META_WIDTH + log2(TX_CHANNELS), + METADATA_WIDTH => DMA_TX_META_SIZE, DEVICE => DEVICE, ALMOST_FULL_OFFSET => 2, ALMOST_EMPTY_OFFSET => 2) From 4ef6d5244bd39c75090b04b3e344f90d9f3136a1 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Thu, 6 Feb 2025 14:01:40 +0100 Subject: [PATCH 3/7] feat(pcie-core): revise R-Tile PCIe and add Gen4 x16 mode This modification reduces unnecessarily duplicated code. Improves R-Tile IP generation using a common library of modifications. Introduces Gen4 x16 mode support and easy IP parameterization. This change allows to use DMA Calypte on cards with R-Tile FPGA. --- cards/bittware/ia-440i/config/card_conf.tcl | 5 +- cards/bittware/ia-440i/config/card_const.tcl | 8 +- cards/bittware/ia-440i/src/Modules.tcl | 2 +- cards/bittware/ia-440i/src/Quartus.inc.tcl | 1 + .../bittware/ia-440i/src/ip/rtile_pcie.ip.tcl | 112 ++---- .../reflexces/agi-fh400g/config/card_conf.tcl | 8 +- .../agi-fh400g/config/card_const.tcl | 8 +- cards/reflexces/agi-fh400g/src/Modules.tcl | 2 +- .../reflexces/agi-fh400g/src/Quartus.inc.tcl | 1 + .../agi-fh400g/src/ip/rtile_pcie.ip.tcl | 107 ++---- cards/terasic/a2700/config/card_conf.tcl | 4 +- cards/terasic/a2700/config/card_const.tcl | 8 +- cards/terasic/a2700/src/Modules.tcl | 2 +- cards/terasic/a2700/src/Quartus.inc.tcl | 1 + cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl | 107 ++---- .../comp/pcie_core/pcie_core_rtile.vhd | 338 +++++++++++++++++- core/ip/intel/pcie/rtile_pcie_conf_lib.tcl | 72 ++++ core/top/fpga_common.vhd | 10 +- 18 files changed, 521 insertions(+), 275 deletions(-) create mode 100644 core/ip/intel/pcie/rtile_pcie_conf_lib.tcl diff --git a/cards/bittware/ia-440i/config/card_conf.tcl b/cards/bittware/ia-440i/config/card_conf.tcl index b5b1cf1f8..96437e963 100644 --- a/cards/bittware/ia-440i/config/card_conf.tcl +++ b/cards/bittware/ia-440i/config/card_conf.tcl @@ -37,8 +37,9 @@ set EHIP_PORT_TYPE(0) $env(EHIP_PORT_TYPE) # PCIe parameters (not all combinations work): # ------------------------------------------------------------------------------ # Supported combinations for this card: -# 1x PCIe Gen5 x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: default configuration) -# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 +# 1x PCIe Gen4 x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Calypte) +# 1x PCIe Gen5 x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Medusa) +# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa) # ------------------------------------------------------------------------------ # Set default PCIe configuration diff --git a/cards/bittware/ia-440i/config/card_const.tcl b/cards/bittware/ia-440i/config/card_const.tcl index f8db85b25..bd64366e2 100644 --- a/cards/bittware/ia-440i/config/card_const.tcl +++ b/cards/bittware/ia-440i/config/card_const.tcl @@ -32,12 +32,14 @@ set QSFP_I2C_ADDR(0) "0xA0" # Checking of parameter compatibility # ------------------------------------------------------------------------------ -if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) || +if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) || + ($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) || ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1)) } { error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE! Allowed PCIe configurations: -- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 -- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1" +- 1xGen4x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte) +- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Medusa) +- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa)" } # ------------------------------------------------------------------------------ diff --git a/cards/bittware/ia-440i/src/Modules.tcl b/cards/bittware/ia-440i/src/Modules.tcl index 9cda2052e..8e79afd10 100644 --- a/cards/bittware/ia-440i/src/Modules.tcl +++ b/cards/bittware/ia-440i/src/Modules.tcl @@ -27,7 +27,7 @@ set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex" set ARCHGRP_ARR(IP_DEVICE) $ARCHGRP_ARR(FPGA) set PCIE_CONF [dict create 0 "1x16" 1 "2x8"] -set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" +set RTILE_PCIE_IP_NAME "rtile_pcie_gen$ARCHGRP_ARR(PCIE_GEN)_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" set ETH_CONF [dict create 400 "1x400g" ] # TODO: 200 "2x200g" 100 [expr {$ARCHGRP_ARR(ETH_PORT_CHAN,0) == 2 ? "2x100g" : "4x100g"}] 50 "8x50g" 40 "2x40g" 25 "8x25g" 10 "8x10g" diff --git a/cards/bittware/ia-440i/src/Quartus.inc.tcl b/cards/bittware/ia-440i/src/Quartus.inc.tcl index 3d2b48182..d1231aadd 100644 --- a/cards/bittware/ia-440i/src/Quartus.inc.tcl +++ b/cards/bittware/ia-440i/src/Quartus.inc.tcl @@ -17,6 +17,7 @@ source $CORE_BASE/Quartus.inc.tcl set CARD_ARCHGRP(CORE_BASE) $CORE_BASE set CARD_ARCHGRP(IP_BUILD_DIR) $CARD_BASE/src/ip set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE +set CARD_ARCHGRP(PCIE_GEN) $PCIE_GEN set CARD_ARCHGRP(NET_MOD_ARCH) $NET_MOD_ARCH # Second dimension because of addition of an element of another array, just for clarity. set CARD_ARCHGRP(ETH_PORT_SPEED,0) $ETH_PORT_SPEED(0) diff --git a/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl b/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl index 827e5e9bb..e529f1d9c 100644 --- a/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl +++ b/cards/bittware/ia-440i/src/ip/rtile_pcie.ip.tcl @@ -1,90 +1,34 @@ +# rtile_pcie.ip.tcl: TCL script for generating R-Tile PCIe IP. +# Copyright (C) 2025 CESNET z.s.p.o. +# Author(s): Jakub Cabal +# +# SPDX-License-Identifier: BSD-3-Clause + package require -exact qsys 21.3 array set PARAMS $IP_PARAMS_L source $PARAMS(IP_COMMON_TCL) - -proc do_adjust_rtile_pcie_ip_1x16 {} { -} - -proc do_adjust_rtile_pcie_ip_2x8 {} { - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_0_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_1_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {0xc000} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_vendor_id_user_hwtcl} {6380} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {design_environment} {Unknown} - set_instance_parameter_value intel_rtile_pcie_ast_0 {standard_interface_selection_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit} - - set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0 - set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc - set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1 - set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc - set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0 - set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1 - set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp - set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n - set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n - set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status - set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt - set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp - set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii -} - -# adjust parameters in "rtile_pcie_ip" system -proc do_adjust_rtile_pcie_ip {device family ipname filename adjust_proc} { - - load_system $filename - set_project_property DEVICE $device - set_project_property DEVICE_FAMILY $family - set_project_property HIDE_FROM_IP_CATALOG {true} - - # common IP core parameters - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {0xc000} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_vendor_id_user_hwtcl} {6380} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {example_design_mode_hwtcl} {PIO/SRIOV} - set_instance_parameter_value intel_rtile_pcie_ast_0 {g5_pld_clkfreq_user_hwtcl} {400MHz} - set_instance_parameter_value intel_rtile_pcie_ast_0 {independent_perst_x16_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {independent_warmcold_perst_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {pipemode_sim_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {true_independent_support_mode_user_hwtcl} {0} - - # configuration-specific parameters - $adjust_proc - - set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii - - save_system $ipname -} - -proc do_nothing {} {} - -set cb do_nothing -if {$PARAMS(PCIE_ENDPOINT_MODE) == 0} { - set cb do_adjust_rtile_pcie_ip_1x16 -} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1} { - set cb do_adjust_rtile_pcie_ip_2x8 +source $PARAMS(IP_TEMPLATE_BASE)/pcie/rtile_pcie_conf_lib.tcl + +set PCI_VENDOR_ID 0x18EC +set PCI_DEVICE_ID 0xC000 +set USR_CLKFREQ 400MHz + +load_system $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] +set_project_property DEVICE $PARAMS(IP_DEVICE) +set_project_property DEVICE_FAMILY $PARAMS(IP_DEVICE_FAMILY) +set_project_property HIDE_FROM_IP_CATALOG {true} + +# common IP core parameters +do_rtile_pcie_common + +# configuration-specific parameters +if {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 4} { + do_rtile_pcie_gen4_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 5} { + do_rtile_pcie_gen5_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1 && $PARAMS(PCIE_GEN) == 5} { + do_rtile_pcie_gen5_2x8 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ } -do_adjust_rtile_pcie_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb +save_system $PARAMS(IP_COMP_NAME) diff --git a/cards/reflexces/agi-fh400g/config/card_conf.tcl b/cards/reflexces/agi-fh400g/config/card_conf.tcl index 0463c56b3..5ab69d6e7 100644 --- a/cards/reflexces/agi-fh400g/config/card_conf.tcl +++ b/cards/reflexces/agi-fh400g/config/card_conf.tcl @@ -38,13 +38,13 @@ set EHIP_PORT_TYPE(0) $env(EHIP_PORT_TYPE) # PCIe parameters (not all combinations work): # ------------------------------------------------------------------------------ # Supported combinations for this card: -# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 -# 2x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (Note: default configuration) -# 1x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: limited DMA performance) +# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa only) +# 2x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa only) +# 1x PCIe Gen4 x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Calypte only) # ------------------------------------------------------------------------------ # Set default PCIe configuration -set PCIE_CONF "2xGen4x8x8" +set PCIE_CONF "2xGen5x8x8" if { [info exist env(PCIE_CONF)] } { set PCIE_CONF $env(PCIE_CONF) } diff --git a/cards/reflexces/agi-fh400g/config/card_const.tcl b/cards/reflexces/agi-fh400g/config/card_const.tcl index 38eefc710..b141cae49 100755 --- a/cards/reflexces/agi-fh400g/config/card_const.tcl +++ b/cards/reflexces/agi-fh400g/config/card_const.tcl @@ -34,12 +34,14 @@ if { $BOARD_REV != 0 && $BOARD_REV != 1 && $BOARD_REV != 2} { error "Incompatible BOARD_REV value: $BOARD_REV" } -if {!(($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 1) || +if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) || + ($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) || ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} { error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE! Allowed PCIe configurations: -- 2xGen4x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 -- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1" +- 2xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only) +- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only) +- 1xGen4x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte only)" } # Enable/add PCIe Gen5 x16 for experiments only! diff --git a/cards/reflexces/agi-fh400g/src/Modules.tcl b/cards/reflexces/agi-fh400g/src/Modules.tcl index 0c860beb7..a6e371b77 100644 --- a/cards/reflexces/agi-fh400g/src/Modules.tcl +++ b/cards/reflexces/agi-fh400g/src/Modules.tcl @@ -27,7 +27,7 @@ set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex" set ARCHGRP_ARR(IP_DEVICE) $ARCHGRP_ARR(FPGA) set PCIE_CONF [dict create 0 "1x16" 1 "2x8"] -set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" +set RTILE_PCIE_IP_NAME "rtile_pcie_gen$ARCHGRP_ARR(PCIE_GEN)_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" set ETH_CONF [dict create 400 "1x400g" 200 "2x200g" 100 [expr {$ARCHGRP_ARR(ETH_PORT_CHAN,0) == 2 ? "2x100g" : "4x100g"}] 50 "8x50g" 40 "2x40g" 25 "8x25g" 10 "8x10g"] set FTILE_ETH_IP_NAME "ftile_eth_[dict get $ETH_CONF $ARCHGRP_ARR(ETH_PORT_SPEED,0)]" diff --git a/cards/reflexces/agi-fh400g/src/Quartus.inc.tcl b/cards/reflexces/agi-fh400g/src/Quartus.inc.tcl index 84eca885a..df17a952a 100644 --- a/cards/reflexces/agi-fh400g/src/Quartus.inc.tcl +++ b/cards/reflexces/agi-fh400g/src/Quartus.inc.tcl @@ -18,6 +18,7 @@ set CARD_ARCHGRP(CORE_BASE) $CORE_BASE set CARD_ARCHGRP(IP_BUILD_DIR) $CARD_BASE/src/ip set CARD_ARCHGRP(NET_MOD_ARCH) $NET_MOD_ARCH set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE +set CARD_ARCHGRP(PCIE_GEN) $PCIE_GEN # Second dimension because of addition of an element of another array, just for clarity. set CARD_ARCHGRP(ETH_PORT_SPEED,0) $ETH_PORT_SPEED(0) set CARD_ARCHGRP(ETH_PORT_CHAN,0) $ETH_PORT_CHAN(0) diff --git a/cards/reflexces/agi-fh400g/src/ip/rtile_pcie.ip.tcl b/cards/reflexces/agi-fh400g/src/ip/rtile_pcie.ip.tcl index 45bf9a303..93649fc1f 100644 --- a/cards/reflexces/agi-fh400g/src/ip/rtile_pcie.ip.tcl +++ b/cards/reflexces/agi-fh400g/src/ip/rtile_pcie.ip.tcl @@ -1,85 +1,34 @@ +# rtile_pcie.ip.tcl: TCL script for generating R-Tile PCIe IP. +# Copyright (C) 2025 CESNET z.s.p.o. +# Author(s): Jakub Cabal +# +# SPDX-License-Identifier: BSD-3-Clause + package require -exact qsys 21.3 array set PARAMS $IP_PARAMS_L source $PARAMS(IP_COMMON_TCL) - -proc do_adjust_rtile_pcie_ip_1x16 {} { -} - -proc do_adjust_rtile_pcie_ip_2x8 {} { - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_0_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_1_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {50176} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_vendor_id_user_hwtcl} {6380} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {design_environment} {Unknown} - set_instance_parameter_value intel_rtile_pcie_ast_0 {standard_interface_selection_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit} - - set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0 - set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc - set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1 - set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc - set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0 - set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1 - set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp - set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n - set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n - set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status - set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt - set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp - set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii -} - -# adjust parameters in "rtile_pcie_ip" system -proc do_adjust_rtile_pcie_ip {device family ipname filename adjust_proc} { - - load_system $filename - set_project_property DEVICE $device - set_project_property DEVICE_FAMILY $family - set_project_property HIDE_FROM_IP_CATALOG {true} - - # common IP core parameters - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {50176} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_vendor_id_user_hwtcl} {6380} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {g5_pld_clkfreq_user_hwtcl} {400MHz} - - # configuration-specific parameters - $adjust_proc - - set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii - - save_system $ipname -} - -proc do_nothing {} {} - -set cb do_nothing -if {$PARAMS(PCIE_ENDPOINT_MODE) == 0} { - set cb do_adjust_rtile_pcie_ip_1x16 -} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1} { - set cb do_adjust_rtile_pcie_ip_2x8 +source $PARAMS(IP_TEMPLATE_BASE)/pcie/rtile_pcie_conf_lib.tcl + +set PCI_VENDOR_ID 0x18EC +set PCI_DEVICE_ID 0xC400 +set USR_CLKFREQ 400MHz + +load_system $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] +set_project_property DEVICE $PARAMS(IP_DEVICE) +set_project_property DEVICE_FAMILY $PARAMS(IP_DEVICE_FAMILY) +set_project_property HIDE_FROM_IP_CATALOG {true} + +# common IP core parameters +do_rtile_pcie_common + +# configuration-specific parameters +if {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 4} { + do_rtile_pcie_gen4_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 5} { + do_rtile_pcie_gen5_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1 && $PARAMS(PCIE_GEN) == 5} { + do_rtile_pcie_gen5_2x8 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ } -do_adjust_rtile_pcie_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb +save_system $PARAMS(IP_COMP_NAME) diff --git a/cards/terasic/a2700/config/card_conf.tcl b/cards/terasic/a2700/config/card_conf.tcl index e425c73e1..f052d64a2 100644 --- a/cards/terasic/a2700/config/card_conf.tcl +++ b/cards/terasic/a2700/config/card_conf.tcl @@ -38,8 +38,8 @@ set EHIP_PORT_TYPE(0) $env(EHIP_PORT_TYPE) # PCIe parameters (not all combinations work): # ------------------------------------------------------------------------------ # Supported combinations for this card: -# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 -# 1x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: limited DMA performance) +# 1x PCIe Gen4 x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (Note: for DMA Calypte) +# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: for DMA Medusa) # ------------------------------------------------------------------------------ # Set default PCIe configuration diff --git a/cards/terasic/a2700/config/card_const.tcl b/cards/terasic/a2700/config/card_const.tcl index 68224a784..706023f0a 100644 --- a/cards/terasic/a2700/config/card_const.tcl +++ b/cards/terasic/a2700/config/card_const.tcl @@ -29,12 +29,12 @@ set QSFP_I2C_ADDR(0) "0xA0" # Checking of parameter compatibility # ------------------------------------------------------------------------------ -if {!(($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 1) || - ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} { +if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) || + ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1)) } { error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE! Allowed PCIe configurations: -- 2xGen4x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 -- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1" +- 1xGen4x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte) +- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa)" } #DDR4 diff --git a/cards/terasic/a2700/src/Modules.tcl b/cards/terasic/a2700/src/Modules.tcl index 8b08ebf7f..189e7c9b3 100644 --- a/cards/terasic/a2700/src/Modules.tcl +++ b/cards/terasic/a2700/src/Modules.tcl @@ -26,7 +26,7 @@ set ARCHGRP_ARR(IP_DEVICE_FAMILY) "Agilex" set ARCHGRP_ARR(IP_DEVICE) $ARCHGRP_ARR(FPGA) set PCIE_CONF [dict create 0 "1x16" 1 "2x8"] -set RTILE_PCIE_IP_NAME "rtile_pcie_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" +set RTILE_PCIE_IP_NAME "rtile_pcie_gen$ARCHGRP_ARR(PCIE_GEN)_[dict get $PCIE_CONF $ARCHGRP_ARR(PCIE_ENDPOINT_MODE)]" set ETH_CONF [dict create 400 "1x400g"] set FTILE_ETH_IP_NAME "ftile_eth_1x400g" diff --git a/cards/terasic/a2700/src/Quartus.inc.tcl b/cards/terasic/a2700/src/Quartus.inc.tcl index 66d68e4e2..f9d9a05c2 100644 --- a/cards/terasic/a2700/src/Quartus.inc.tcl +++ b/cards/terasic/a2700/src/Quartus.inc.tcl @@ -17,6 +17,7 @@ set CARD_ARCHGRP(CORE_BASE) $CORE_BASE set CARD_ARCHGRP(IP_BUILD_DIR) $CARD_BASE/src/ip set CARD_ARCHGRP(NET_MOD_ARCH) $NET_MOD_ARCH set CARD_ARCHGRP(PCIE_ENDPOINT_MODE) $PCIE_ENDPOINT_MODE +set CARD_ARCHGRP(PCIE_GEN) $PCIE_GEN # Second dimension because of addition of an element of another array, just for clarity. set CARD_ARCHGRP(ETH_PORT_SPEED,0) $ETH_PORT_SPEED(0) set CARD_ARCHGRP(ETH_PORT_CHAN,0) $ETH_PORT_CHAN(0) diff --git a/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl b/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl index 5d1f392f0..e529f1d9c 100644 --- a/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl +++ b/cards/terasic/a2700/src/ip/rtile_pcie.ip.tcl @@ -1,85 +1,34 @@ +# rtile_pcie.ip.tcl: TCL script for generating R-Tile PCIe IP. +# Copyright (C) 2025 CESNET z.s.p.o. +# Author(s): Jakub Cabal +# +# SPDX-License-Identifier: BSD-3-Clause + package require -exact qsys 21.3 array set PARAMS $IP_PARAMS_L source $PARAMS(IP_COMMON_TCL) - -proc do_adjust_rtile_pcie_ip_1x16 {} { -} - -proc do_adjust_rtile_pcie_ip_2x8 {} { - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_0_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core4_1_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_device_id_hwtcl} {49152} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_pci_type0_vendor_id_user_hwtcl} {6380} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {design_environment} {Unknown} - set_instance_parameter_value intel_rtile_pcie_ast_0 {standard_interface_selection_hwtcl} {0} - set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit} - - set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0 - set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc - set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1 - set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc - set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0 - set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1 - set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp - set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n - set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n - set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status - set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt - set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp - set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii -} - -# adjust parameters in "rtile_pcie_ip" system -proc do_adjust_rtile_pcie_ip {device family ipname filename adjust_proc} { - - load_system $filename - set_project_property DEVICE $device - set_project_property DEVICE_FAMILY $family - set_project_property HIDE_FROM_IP_CATALOG {true} - - # common IP core parameters - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_device_id_hwtcl} {49152} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_pci_type0_vendor_id_user_hwtcl} {6380} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1} - set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328} - set_instance_parameter_value intel_rtile_pcie_ast_0 {g5_pld_clkfreq_user_hwtcl} {400MHz} - - # configuration-specific parameters - $adjust_proc - - set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii - - save_system $ipname -} - -proc do_nothing {} {} - -set cb do_nothing -if {$PARAMS(PCIE_ENDPOINT_MODE) == 0} { - set cb do_adjust_rtile_pcie_ip_1x16 -} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1} { - set cb do_adjust_rtile_pcie_ip_2x8 +source $PARAMS(IP_TEMPLATE_BASE)/pcie/rtile_pcie_conf_lib.tcl + +set PCI_VENDOR_ID 0x18EC +set PCI_DEVICE_ID 0xC000 +set USR_CLKFREQ 400MHz + +load_system $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] +set_project_property DEVICE $PARAMS(IP_DEVICE) +set_project_property DEVICE_FAMILY $PARAMS(IP_DEVICE_FAMILY) +set_project_property HIDE_FROM_IP_CATALOG {true} + +# common IP core parameters +do_rtile_pcie_common + +# configuration-specific parameters +if {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 4} { + do_rtile_pcie_gen4_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 0 && $PARAMS(PCIE_GEN) == 5} { + do_rtile_pcie_gen5_1x16 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ +} elseif {$PARAMS(PCIE_ENDPOINT_MODE) == 1 && $PARAMS(PCIE_GEN) == 5} { + do_rtile_pcie_gen5_2x8 $PCI_VENDOR_ID $PCI_DEVICE_ID $USR_CLKFREQ } -do_adjust_rtile_pcie_ip $PARAMS(IP_DEVICE) $PARAMS(IP_DEVICE_FAMILY) $PARAMS(IP_COMP_NAME) $PARAMS(IP_BUILD_DIR)/[get_ip_filename $PARAMS(IP_COMP_NAME)] $cb +save_system $PARAMS(IP_COMP_NAME) diff --git a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd index 9234f60e7..00bad09b6 100644 --- a/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd +++ b/core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_rtile.vhd @@ -13,7 +13,7 @@ use work.type_pack.all; architecture RTILE of PCIE_CORE is - component rtile_pcie_2x8 is + component rtile_pcie_gen5_2x8 is port ( p0_rx_st_ready_i : in std_logic := 'X'; -- ready p0_rx_st0_data_o : out std_logic_vector(255 downto 0); -- data @@ -239,9 +239,9 @@ architecture RTILE of PCIE_CORE is tx_p_out14 : out std_logic; -- tx_p_out14 tx_p_out15 : out std_logic -- tx_p_out15 ); - end component rtile_pcie_2x8; + end component rtile_pcie_gen5_2x8; - component rtile_pcie_1x16 is + component rtile_pcie_gen5_1x16 is port ( p0_rx_st_ready_i : in std_logic := 'X'; -- ready p0_rx_st0_data_o : out std_logic_vector(255 downto 0); -- data @@ -431,7 +431,161 @@ architecture RTILE of PCIE_CORE is pin_perst_n : in std_logic := 'X'; -- reset_n pin_perst_n_o : out std_logic -- reset_n ); - end component rtile_pcie_1x16; + end component rtile_pcie_gen5_1x16; + + component rtile_pcie_gen4_1x16 is + port ( + p0_reset_status_n : out std_logic; -- reset_n + p0_slow_reset_status_n : out std_logic; -- reset_n + p0_link_up_o : out std_logic; -- link_up + p0_dl_up_o : out std_logic; -- dl_up + p0_surprise_down_err_o : out std_logic; -- surprise_down_err + p0_dl_timer_update_o : out std_logic; -- dl_timer_update + p0_ltssm_state_delay_o : out std_logic_vector(5 downto 0); -- ltssm_state_delay + p0_ltssm_st_hipfifo_ovrflw_o : out std_logic; -- ltssm_st_hipfifo_ovrflw + p0_app_xfer_pending_i : in std_logic := 'X'; -- app_xfer_pending + p0_pld_gp_status_i : in std_logic_vector(7 downto 0) := (others => 'X'); -- status + p0_pld_gp_ctrl_o : out std_logic_vector(7 downto 0); -- ctrl + p0_pld_gp_status_ready_o : out std_logic; -- status_ready + p0_cii_req_o : out std_logic; -- req + p0_cii_hdr_poisoned_o : out std_logic; -- hdr_poisoned + p0_cii_hdr_first_be_o : out std_logic_vector(3 downto 0); -- hdr_first_be + p0_cii_wr_o : out std_logic; -- wr + p0_cii_addr_o : out std_logic_vector(9 downto 0); -- addr + p0_cii_dout_o : out std_logic_vector(31 downto 0); -- dout + p0_cii_override_en_i : in std_logic := 'X'; -- override_en + p0_cii_override_din_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- override_din + p0_cii_halt_i : in std_logic := 'X'; -- halt + rx_n_in0 : in std_logic := 'X'; -- rx_n_in0 + rx_n_in1 : in std_logic := 'X'; -- rx_n_in1 + rx_n_in2 : in std_logic := 'X'; -- rx_n_in2 + rx_n_in3 : in std_logic := 'X'; -- rx_n_in3 + rx_n_in4 : in std_logic := 'X'; -- rx_n_in4 + rx_n_in5 : in std_logic := 'X'; -- rx_n_in5 + rx_n_in6 : in std_logic := 'X'; -- rx_n_in6 + rx_n_in7 : in std_logic := 'X'; -- rx_n_in7 + rx_n_in8 : in std_logic := 'X'; -- rx_n_in8 + rx_n_in9 : in std_logic := 'X'; -- rx_n_in9 + rx_n_in10 : in std_logic := 'X'; -- rx_n_in10 + rx_n_in11 : in std_logic := 'X'; -- rx_n_in11 + rx_n_in12 : in std_logic := 'X'; -- rx_n_in12 + rx_n_in13 : in std_logic := 'X'; -- rx_n_in13 + rx_n_in14 : in std_logic := 'X'; -- rx_n_in14 + rx_n_in15 : in std_logic := 'X'; -- rx_n_in15 + rx_p_in0 : in std_logic := 'X'; -- rx_p_in0 + rx_p_in1 : in std_logic := 'X'; -- rx_p_in1 + rx_p_in2 : in std_logic := 'X'; -- rx_p_in2 + rx_p_in3 : in std_logic := 'X'; -- rx_p_in3 + rx_p_in4 : in std_logic := 'X'; -- rx_p_in4 + rx_p_in5 : in std_logic := 'X'; -- rx_p_in5 + rx_p_in6 : in std_logic := 'X'; -- rx_p_in6 + rx_p_in7 : in std_logic := 'X'; -- rx_p_in7 + rx_p_in8 : in std_logic := 'X'; -- rx_p_in8 + rx_p_in9 : in std_logic := 'X'; -- rx_p_in9 + rx_p_in10 : in std_logic := 'X'; -- rx_p_in10 + rx_p_in11 : in std_logic := 'X'; -- rx_p_in11 + rx_p_in12 : in std_logic := 'X'; -- rx_p_in12 + rx_p_in13 : in std_logic := 'X'; -- rx_p_in13 + rx_p_in14 : in std_logic := 'X'; -- rx_p_in14 + rx_p_in15 : in std_logic := 'X'; -- rx_p_in15 + tx_n_out0 : out std_logic; -- tx_n_out0 + tx_n_out1 : out std_logic; -- tx_n_out1 + tx_n_out2 : out std_logic; -- tx_n_out2 + tx_n_out3 : out std_logic; -- tx_n_out3 + tx_n_out4 : out std_logic; -- tx_n_out4 + tx_n_out5 : out std_logic; -- tx_n_out5 + tx_n_out6 : out std_logic; -- tx_n_out6 + tx_n_out7 : out std_logic; -- tx_n_out7 + tx_n_out8 : out std_logic; -- tx_n_out8 + tx_n_out9 : out std_logic; -- tx_n_out9 + tx_n_out10 : out std_logic; -- tx_n_out10 + tx_n_out11 : out std_logic; -- tx_n_out11 + tx_n_out12 : out std_logic; -- tx_n_out12 + tx_n_out13 : out std_logic; -- tx_n_out13 + tx_n_out14 : out std_logic; -- tx_n_out14 + tx_n_out15 : out std_logic; -- tx_n_out15 + tx_p_out0 : out std_logic; -- tx_p_out0 + tx_p_out1 : out std_logic; -- tx_p_out1 + tx_p_out2 : out std_logic; -- tx_p_out2 + tx_p_out3 : out std_logic; -- tx_p_out3 + tx_p_out4 : out std_logic; -- tx_p_out4 + tx_p_out5 : out std_logic; -- tx_p_out5 + tx_p_out6 : out std_logic; -- tx_p_out6 + tx_p_out7 : out std_logic; -- tx_p_out7 + tx_p_out8 : out std_logic; -- tx_p_out8 + tx_p_out9 : out std_logic; -- tx_p_out9 + tx_p_out10 : out std_logic; -- tx_p_out10 + tx_p_out11 : out std_logic; -- tx_p_out11 + tx_p_out12 : out std_logic; -- tx_p_out12 + tx_p_out13 : out std_logic; -- tx_p_out13 + tx_p_out14 : out std_logic; -- tx_p_out14 + tx_p_out15 : out std_logic; -- tx_p_out15 + refclk0 : in std_logic := 'X'; -- clk + refclk1 : in std_logic := 'X'; -- clk + coreclkout_hip : out std_logic; -- clk + ninit_done : in std_logic := 'X'; -- reset + slow_clk : out std_logic; -- clk + p0_rx_st_ready_i : in std_logic := 'X'; -- ready + p0_rx_st0_data_o : out std_logic_vector(255 downto 0); -- data + p0_rx_st0_sop_o : out std_logic; -- startofpacket + p0_rx_st0_eop_o : out std_logic; -- endofpacket + p0_rx_st0_dvalid_o : out std_logic; -- valid + p0_rx_st0_empty_o : out std_logic_vector(2 downto 0); -- empty + p0_rx_st0_hdr_o : out std_logic_vector(127 downto 0); -- rx_st0_hdr + p0_rx_st0_prefix_o : out std_logic_vector(31 downto 0); -- rx_st0_prefix + p0_rx_st0_hvalid_o : out std_logic; -- rx_st0_hvalid + p0_rx_st0_pvalid_o : out std_logic; -- rx_st0_pvalid + p0_rx_st0_bar_o : out std_logic_vector(2 downto 0); -- rx_st0_bar + p0_rx_st0_pt_parity_o : out std_logic; -- rx_st0_pt_parity + p0_rx_st1_hdr_o : out std_logic_vector(127 downto 0); -- rx_st1_hdr + p0_rx_st1_prefix_o : out std_logic_vector(31 downto 0); -- rx_st1_prefix + p0_rx_st1_hvalid_o : out std_logic; -- rx_st1_hvalid + p0_rx_st1_pvalid_o : out std_logic; -- rx_st1_pvalid + p0_rx_st1_bar_o : out std_logic_vector(2 downto 0); -- rx_st1_bar + p0_rx_st1_pt_parity_o : out std_logic; -- rx_st1_pt_parity + p0_rx_st_hcrdt_init_i : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_st_Hcrdt_init + p0_rx_st_hcrdt_update_i : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_st_Hcrdt_update + p0_rx_st_hcrdt_update_cnt_i : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_st_Hcrdt_update_cnt + p0_rx_st_hcrdt_init_ack_o : out std_logic_vector(2 downto 0); -- rx_st_Hcrdt_init_ack + p0_rx_st_dcrdt_init_i : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_st_Dcrdt_init + p0_rx_st_dcrdt_update_i : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_st_Dcrdt_update + p0_rx_st_dcrdt_update_cnt_i : in std_logic_vector(11 downto 0) := (others => 'X'); -- rx_st_Dcrdt_update_cnt + p0_rx_st_dcrdt_init_ack_o : out std_logic_vector(2 downto 0); -- rx_st_Dcrdt_init_ack + p0_rx_st1_data_o : out std_logic_vector(255 downto 0); -- data + p0_rx_st1_sop_o : out std_logic; -- startofpacket + p0_rx_st1_eop_o : out std_logic; -- endofpacket + p0_rx_st1_dvalid_o : out std_logic; -- valid + p0_rx_st1_empty_o : out std_logic_vector(2 downto 0); -- empty + p0_tx_st_hcrdt_init_o : out std_logic_vector(2 downto 0); -- tx_st_Hcrdt_init + p0_tx_st_hcrdt_update_o : out std_logic_vector(2 downto 0); -- tx_st_Hcrdt_update + p0_tx_st_hcrdt_update_cnt_o : out std_logic_vector(5 downto 0); -- tx_st_Hcrdt_update_cnt + p0_tx_st_hcrdt_init_ack_i : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_st_Hcrdtt_init_ack + p0_tx_st_dcrdt_init_o : out std_logic_vector(2 downto 0); -- tx_st_Dcrdt_init + p0_tx_st_dcrdt_update_o : out std_logic_vector(2 downto 0); -- tx_st_Dcrdt_update + p0_tx_st_dcrdt_update_cnt_o : out std_logic_vector(11 downto 0); -- tx_st_Dcrdt_update_cnt + p0_tx_st_dcrdt_init_ack_i : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_st_Dcrdt_init_ack + p0_tx_st0_hdr_i : in std_logic_vector(127 downto 0) := (others => 'X'); -- tx_st0_hdr + p0_tx_st0_prefix_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- tx_st0_prefix + p0_tx_st0_hvalid_i : in std_logic := 'X'; -- tx_st0_hvalid + p0_tx_st0_pvalid_i : in std_logic := 'X'; -- tx_st0_pvalid + p0_tx_st1_hdr_i : in std_logic_vector(127 downto 0) := (others => 'X'); -- tx_st1_hdr + p0_tx_st1_prefix_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- tx_st1_prefix + p0_tx_st1_hvalid_i : in std_logic := 'X'; -- tx_st1_hvalid + p0_tx_st1_pvalid_i : in std_logic := 'X'; -- tx_st1_pvalid + p0_tx_st_ready_o : out std_logic; -- ready + p0_tx_st0_data_i : in std_logic_vector(255 downto 0) := (others => 'X'); -- data + p0_tx_st0_sop_i : in std_logic := 'X'; -- startofpacket + p0_tx_st0_eop_i : in std_logic := 'X'; -- endofpacket + p0_tx_st0_dvalid_i : in std_logic := 'X'; -- valid + p0_tx_st1_data_i : in std_logic_vector(255 downto 0) := (others => 'X'); -- data + p0_tx_st1_sop_i : in std_logic := 'X'; -- startofpacket + p0_tx_st1_eop_i : in std_logic := 'X'; -- endofpacket + p0_tx_st1_dvalid_i : in std_logic := 'X'; -- valid + p0_tx_ehp_deallocate_empty_o : out std_logic; -- tx_ehp_deallocate_empty + pin_perst_n : in std_logic := 'X'; -- reset_n + pin_perst_n_o : out std_logic -- reset_n + ); + end component rtile_pcie_gen4_1x16; constant VSEC_BASE_ADDRESS : integer := 16#D00#; constant PCIE_HIPS : natural := tsel(ENDPOINT_MODE=0,PCIE_ENDPOINTS,PCIE_ENDPOINTS/2); @@ -549,8 +703,8 @@ begin -- ========================================================================= pcie_core_g : for i in 0 to PCIE_HIPS-1 generate - pcie_core_2x8_g : if ENDPOINT_MODE = 1 generate - rtile_i : component rtile_pcie_2x8 + pcie_core_2x8_g : if (ENDPOINT_MODE = 1 and PCIE_GEN = 5) generate + rtile_i : component rtile_pcie_gen5_2x8 port map ( p0_rx_st_ready_i => pcie_avst_down_ready(i*2), -- p0_rx_st0.ready p0_rx_st0_data_o => pcie_avst_down_data(i*2)(256-1 downto 0), -- .data @@ -793,8 +947,9 @@ begin pcie_slow_clk(i*2+1) <= pcie_hip_slow_clk(i); pcie_init_done_n(i) <= INIT_DONE_N; end generate; - pcie_core_1x16_g : if ENDPOINT_MODE = 0 generate - rtile_i : component rtile_pcie_1x16 + + pcie_core_1x16_g : if (ENDPOINT_MODE = 0 and PCIE_GEN = 5) generate + rtile_i : component rtile_pcie_gen5_1x16 port map ( p0_rx_st_ready_i => pcie_avst_down_ready(i), @@ -999,6 +1154,173 @@ begin pcie_slow_clk(i) <= pcie_hip_slow_clk(i); pcie_init_done_n(i) <= INIT_DONE_N; end generate; + + pcie_core_gen4_1x16_g : if (ENDPOINT_MODE = 0 and PCIE_GEN = 4) generate + rtile_i : component rtile_pcie_gen4_1x16 + port map ( + p0_rx_st_ready_i => pcie_avst_down_ready(i), + + p0_rx_st0_data_o => pcie_avst_down_data(i)(256-1 downto 0), + p0_rx_st0_sop_o => pcie_avst_down_sop(i)(0), + p0_rx_st0_eop_o => pcie_avst_down_eop(i)(0), + p0_rx_st0_dvalid_o => pcie_avst_down_dvalid(i)(0), + p0_rx_st0_empty_o => pcie_avst_down_empty(i)(3-1 downto 0), + p0_rx_st0_hdr_o => pcie_avst_down_hdr(i)(128-1 downto 0), + p0_rx_st0_prefix_o => pcie_avst_down_prefix(i)(32-1 downto 0), + p0_rx_st0_hvalid_o => pcie_avst_down_hvalid(i)(0), + p0_rx_st0_pvalid_o => open, + p0_rx_st0_bar_o => pcie_avst_down_bar_range(i)(3-1 downto 0), + + p0_rx_st1_data_o => pcie_avst_down_data(i)(512-1 downto 256), + p0_rx_st1_sop_o => pcie_avst_down_sop(i)(1), + p0_rx_st1_eop_o => pcie_avst_down_eop(i)(1), + p0_rx_st1_dvalid_o => pcie_avst_down_dvalid(i)(1), + p0_rx_st1_empty_o => pcie_avst_down_empty(i)(6-1 downto 3), + p0_rx_st1_hdr_o => pcie_avst_down_hdr(i)(256-1 downto 128), + p0_rx_st1_prefix_o => pcie_avst_down_prefix(i)(64-1 downto 32), + p0_rx_st1_hvalid_o => pcie_avst_down_hvalid(i)(1), + p0_rx_st1_pvalid_o => open, + p0_rx_st1_bar_o => pcie_avst_down_bar_range(i)(6-1 downto 3), + + p0_rx_st_hcrdt_init_i => pcie_hcrdt_dw_init(i), -- .rx_st_Hcrdt_init + p0_rx_st_hcrdt_update_i => pcie_hcrdt_dw_update(i), -- .rx_st_Hcrdt_update + p0_rx_st_hcrdt_update_cnt_i => pcie_hcrdt_dw_update_cnt(i), -- .rx_st_Hcrdt_update_cnt + p0_rx_st_hcrdt_init_ack_o => pcie_hcrdt_dw_init_ack(i), -- .rx_st_Hcrdt_init_ack + p0_rx_st_dcrdt_init_i => pcie_dcrdt_dw_init(i), -- .rx_st_Dcrdt_init + p0_rx_st_dcrdt_update_i => pcie_dcrdt_dw_update(i), -- .rx_st_Dcrdt_update + p0_rx_st_dcrdt_update_cnt_i => pcie_dcrdt_dw_update_cnt(i), -- .rx_st_Dcrdt_update_cnt + p0_rx_st_dcrdt_init_ack_o => pcie_dcrdt_dw_init_ack(i), -- .rx_st_Dcrdt_init_ack + + p0_tx_st_ready_o => pcie_avst_up_ready(i), + p0_tx_ehp_deallocate_empty_o => open, + + p0_tx_st0_hdr_i => pcie_avst_up_hdr(i)(128-1 downto 0), + p0_tx_st0_prefix_i => pcie_avst_up_prefix(i)(32-1 downto 0), + p0_tx_st0_hvalid_i => pcie_avst_up_hvalid(i)(0), + p0_tx_st0_pvalid_i => '0', + p0_tx_st0_data_i => pcie_avst_up_data(i)(256-1 downto 0), + p0_tx_st0_sop_i => pcie_avst_up_sop(i)(0), + p0_tx_st0_eop_i => pcie_avst_up_eop(i)(0), + p0_tx_st0_dvalid_i => pcie_avst_up_dvalid(i)(0), + + p0_tx_st1_hdr_i => pcie_avst_up_hdr(i)(256-1 downto 128), + p0_tx_st1_prefix_i => pcie_avst_up_prefix(i)(64-1 downto 32), + p0_tx_st1_hvalid_i => pcie_avst_up_hvalid(i)(1), + p0_tx_st1_pvalid_i => '0', + p0_tx_st1_data_i => pcie_avst_up_data(i)(512-1 downto 256), + p0_tx_st1_sop_i => pcie_avst_up_sop(i)(1), + p0_tx_st1_eop_i => pcie_avst_up_eop(i)(1), + p0_tx_st1_dvalid_i => pcie_avst_up_dvalid(i)(1), + + p0_tx_st_hcrdt_init_o => pcie_hcrdt_up_init(i), -- p0_tx_st_misc.tx_st_Hcrdt_init + p0_tx_st_hcrdt_update_o => pcie_hcrdt_up_update(i), -- .tx_st_Hcrdt_update + p0_tx_st_hcrdt_update_cnt_o => pcie_hcrdt_up_update_cnt(i), -- .tx_st_Hcrdt_update_cnt + p0_tx_st_hcrdt_init_ack_i => pcie_hcrdt_up_init_ack(i), -- .tx_st_Hcrdtt_init_ack + p0_tx_st_dcrdt_init_o => pcie_dcrdt_up_init(i), -- .tx_st_Dcrdt_init + p0_tx_st_dcrdt_update_o => pcie_dcrdt_up_update(i), -- .tx_st_Dcrdt_update + p0_tx_st_dcrdt_update_cnt_o => pcie_dcrdt_up_update_cnt(i), -- .tx_st_Dcrdt_update_cnt + p0_tx_st_dcrdt_init_ack_i => pcie_dcrdt_up_init_ack(i), -- .tx_st_Dcrdt_init_ack + + p0_reset_status_n => pcie_reset_status_n(i), -- p0_reset_status_n.reset_n + p0_slow_reset_status_n => open, -- p0_slow_reset_status_n.reset_n + p0_link_up_o => pcie_link_up_comb(i), -- p0_hip_status.link_up + p0_dl_up_o => open, -- .dl_up + p0_surprise_down_err_o => open, -- .surprise_down_err + p0_dl_timer_update_o => open, -- .dl_timer_update + p0_ltssm_state_delay_o => open, -- .ltssm_state_delay + p0_ltssm_st_hipfifo_ovrflw_o => open, -- .ltssm_st_hipfifo_ovrflw + p0_app_xfer_pending_i => '0', -- p0_power_mgnt.app_xfer_pending + p0_pld_gp_status_i => (others => '0'), -- p0_pld_gp.status + p0_pld_gp_ctrl_o => open, -- .ctrl + p0_pld_gp_status_ready_o => open, -- .status_ready + p0_cii_req_o => pcie_cii_req(i), -- p0_cii.req + p0_cii_hdr_poisoned_o => pcie_cii_hdr_poisoned(i), -- .hdr_poisoned + p0_cii_hdr_first_be_o => pcie_cii_hdr_first_be(i), -- .hdr_first_be + p0_cii_wr_o => pcie_cii_wr(i), -- .wr + p0_cii_addr_o => pcie_cii_addr(i), -- .addr + p0_cii_dout_o => pcie_cii_dout(i), -- .dout + p0_cii_override_en_i => pcie_cii_override_en(i), -- .override_en + p0_cii_override_din_i => pcie_cii_override_din(i), -- .override_din + p0_cii_halt_i => pcie_cii_halt(i), -- .halt + + rx_n_in0 => PCIE_RX_N(i*PCIE_LANES+0), -- hip_serial.rx_n_in0 + rx_n_in1 => PCIE_RX_N(i*PCIE_LANES+1), -- .rx_n_in1 + rx_n_in2 => PCIE_RX_N(i*PCIE_LANES+2), -- .rx_n_in2 + rx_n_in3 => PCIE_RX_N(i*PCIE_LANES+3), -- .rx_n_in3 + rx_n_in4 => PCIE_RX_N(i*PCIE_LANES+4), -- .rx_n_in4 + rx_n_in5 => PCIE_RX_N(i*PCIE_LANES+5), -- .rx_n_in5 + rx_n_in6 => PCIE_RX_N(i*PCIE_LANES+6), -- .rx_n_in6 + rx_n_in7 => PCIE_RX_N(i*PCIE_LANES+7), -- .rx_n_in7 + rx_n_in8 => PCIE_RX_N(i*PCIE_LANES+8), -- .rx_n_in8 + rx_n_in9 => PCIE_RX_N(i*PCIE_LANES+9), -- .rx_n_in9 + rx_n_in10 => PCIE_RX_N(i*PCIE_LANES+10), -- .rx_n_in10 + rx_n_in11 => PCIE_RX_N(i*PCIE_LANES+11), -- .rx_n_in11 + rx_n_in12 => PCIE_RX_N(i*PCIE_LANES+12), -- .rx_n_in12 + rx_n_in13 => PCIE_RX_N(i*PCIE_LANES+13), -- .rx_n_in13 + rx_n_in14 => PCIE_RX_N(i*PCIE_LANES+14), -- .rx_n_in14 + rx_n_in15 => PCIE_RX_N(i*PCIE_LANES+15), -- .rx_n_in15 + rx_p_in0 => PCIE_RX_P(i*PCIE_LANES+0), -- .rx_p_in0 + rx_p_in1 => PCIE_RX_P(i*PCIE_LANES+1), -- .rx_p_in1 + rx_p_in2 => PCIE_RX_P(i*PCIE_LANES+2), -- .rx_p_in2 + rx_p_in3 => PCIE_RX_P(i*PCIE_LANES+3), -- .rx_p_in3 + rx_p_in4 => PCIE_RX_P(i*PCIE_LANES+4), -- .rx_p_in4 + rx_p_in5 => PCIE_RX_P(i*PCIE_LANES+5), -- .rx_p_in5 + rx_p_in6 => PCIE_RX_P(i*PCIE_LANES+6), -- .rx_p_in6 + rx_p_in7 => PCIE_RX_P(i*PCIE_LANES+7), -- .rx_p_in7 + rx_p_in8 => PCIE_RX_P(i*PCIE_LANES+8), -- .rx_p_in8 + rx_p_in9 => PCIE_RX_P(i*PCIE_LANES+9), -- .rx_p_in9 + rx_p_in10 => PCIE_RX_P(i*PCIE_LANES+10), -- .rx_p_in10 + rx_p_in11 => PCIE_RX_P(i*PCIE_LANES+11), -- .rx_p_in11 + rx_p_in12 => PCIE_RX_P(i*PCIE_LANES+12), -- .rx_p_in12 + rx_p_in13 => PCIE_RX_P(i*PCIE_LANES+13), -- .rx_p_in13 + rx_p_in14 => PCIE_RX_P(i*PCIE_LANES+14), -- .rx_p_in14 + rx_p_in15 => PCIE_RX_P(i*PCIE_LANES+15), -- .rx_p_in15 + tx_n_out0 => PCIE_TX_N(i*PCIE_LANES+0), -- .tx_n_out0 + tx_n_out1 => PCIE_TX_N(i*PCIE_LANES+1), -- .tx_n_out1 + tx_n_out2 => PCIE_TX_N(i*PCIE_LANES+2), -- .tx_n_out2 + tx_n_out3 => PCIE_TX_N(i*PCIE_LANES+3), -- .tx_n_out3 + tx_n_out4 => PCIE_TX_N(i*PCIE_LANES+4), -- .tx_n_out4 + tx_n_out5 => PCIE_TX_N(i*PCIE_LANES+5), -- .tx_n_out5 + tx_n_out6 => PCIE_TX_N(i*PCIE_LANES+6), -- .tx_n_out6 + tx_n_out7 => PCIE_TX_N(i*PCIE_LANES+7), -- .tx_n_out7 + tx_n_out8 => PCIE_TX_N(i*PCIE_LANES+8), -- .tx_n_out8 + tx_n_out9 => PCIE_TX_N(i*PCIE_LANES+9), -- .tx_n_out9 + tx_n_out10 => PCIE_TX_N(i*PCIE_LANES+10), -- .tx_n_out10 + tx_n_out11 => PCIE_TX_N(i*PCIE_LANES+11), -- .tx_n_out11 + tx_n_out12 => PCIE_TX_N(i*PCIE_LANES+12), -- .tx_n_out12 + tx_n_out13 => PCIE_TX_N(i*PCIE_LANES+13), -- .tx_n_out13 + tx_n_out14 => PCIE_TX_N(i*PCIE_LANES+14), -- .tx_n_out14 + tx_n_out15 => PCIE_TX_N(i*PCIE_LANES+15), -- .tx_n_out15 + tx_p_out0 => PCIE_TX_P(i*PCIE_LANES+0), -- .tx_p_out0 + tx_p_out1 => PCIE_TX_P(i*PCIE_LANES+1), -- .tx_p_out1 + tx_p_out2 => PCIE_TX_P(i*PCIE_LANES+2), -- .tx_p_out2 + tx_p_out3 => PCIE_TX_P(i*PCIE_LANES+3), -- .tx_p_out3 + tx_p_out4 => PCIE_TX_P(i*PCIE_LANES+4), -- .tx_p_out4 + tx_p_out5 => PCIE_TX_P(i*PCIE_LANES+5), -- .tx_p_out5 + tx_p_out6 => PCIE_TX_P(i*PCIE_LANES+6), -- .tx_p_out6 + tx_p_out7 => PCIE_TX_P(i*PCIE_LANES+7), -- .tx_p_out7 + tx_p_out8 => PCIE_TX_P(i*PCIE_LANES+8), -- .tx_p_out8 + tx_p_out9 => PCIE_TX_P(i*PCIE_LANES+9), -- .tx_p_out9 + tx_p_out10 => PCIE_TX_P(i*PCIE_LANES+10), -- .tx_p_out10 + tx_p_out11 => PCIE_TX_P(i*PCIE_LANES+11), -- .tx_p_out11 + tx_p_out12 => PCIE_TX_P(i*PCIE_LANES+12), -- .tx_p_out12 + tx_p_out13 => PCIE_TX_P(i*PCIE_LANES+13), -- .tx_p_out13 + tx_p_out14 => PCIE_TX_P(i*PCIE_LANES+14), -- .tx_p_out14 + tx_p_out15 => PCIE_TX_P(i*PCIE_LANES+15), -- .tx_p_out15 + + refclk0 => PCIE_SYSCLK_P(i*PCIE_CLKS), -- refclk0.clk + refclk1 => PCIE_SYSCLK_P(i*PCIE_CLKS+1), -- refclk1.clk + coreclkout_hip => pcie_hip_clk(i), -- coreclkout_hip.clk + ninit_done => pcie_init_done_n(i), -- ninit_done.ninit_done + slow_clk => pcie_hip_slow_clk(i), -- slow_clk.clk + pin_perst_n => PCIE_SYSRST_N(i), -- pin_perst.pin_perst + pin_perst_n_o => open + ); + + pcie_clk(i) <= pcie_hip_clk(i); + pcie_slow_clk(i) <= pcie_hip_slow_clk(i); + pcie_init_done_n(i) <= INIT_DONE_N; + end generate; end generate; -- ========================================================================= diff --git a/core/ip/intel/pcie/rtile_pcie_conf_lib.tcl b/core/ip/intel/pcie/rtile_pcie_conf_lib.tcl new file mode 100644 index 000000000..8423d62c0 --- /dev/null +++ b/core/ip/intel/pcie/rtile_pcie_conf_lib.tcl @@ -0,0 +1,72 @@ +# rtile_conf_lib.tcl: R-Tile PCIe IP configuration library. +# Copyright (C) 2025 CESNET z.s.p.o. +# Author(s): Jakub Cabal +# +# SPDX-License-Identifier: BSD-3-Clause + +proc do_rtile_pcie_gen5_2x8 {pci_vendor_id pci_device_id usr_clkfreq} { + set_instance_parameter_value intel_rtile_pcie_ast_0 core16_pf0_pci_type0_device_id_hwtcl $pci_device_id + set_instance_parameter_value intel_rtile_pcie_ast_0 core16_pf0_pci_type0_vendor_id_user_hwtcl $pci_vendor_id + set_instance_parameter_value intel_rtile_pcie_ast_0 core8_pf0_pci_type0_device_id_hwtcl $pci_device_id + set_instance_parameter_value intel_rtile_pcie_ast_0 core8_pf0_pci_type0_vendor_id_user_hwtcl $pci_vendor_id + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_enable_cii_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_address_width_user_hwtcl} {26} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar2_address_width_user_hwtcl} {24} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_bar2_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_class_code_hwtcl} {131072} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_pf0_gen2_ctrl_off_support_mod_ts_hwtcl} {0} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_user_vsec_cap_enable_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core8_virtual_pf0_user_vsec_offset_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 2x8, Interface - 512 bit} + set_instance_parameter_value intel_rtile_pcie_ast_0 g5_pld_clkfreq_user_hwtcl $usr_clkfreq + + set_interface_property p1_rx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st0 + set_interface_property p1_rx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st_misc + set_interface_property p1_rx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_rx_st1 + set_interface_property p1_tx_st_misc EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st_misc + set_interface_property p1_tx_st0 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st0 + set_interface_property p1_tx_st1 EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_st1 + set_interface_property p1_tx_ehp EXPORT_OF intel_rtile_pcie_ast_0.p1_tx_ehp + set_interface_property p1_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_reset_status_n + set_interface_property p1_slow_reset_status_n EXPORT_OF intel_rtile_pcie_ast_0.p1_slow_reset_status_n + set_interface_property p1_hip_status EXPORT_OF intel_rtile_pcie_ast_0.p1_hip_status + set_interface_property p1_power_mgnt EXPORT_OF intel_rtile_pcie_ast_0.p1_power_mgnt + set_interface_property p1_pld_gp EXPORT_OF intel_rtile_pcie_ast_0.p1_pld_gp + set_interface_property p1_cii EXPORT_OF intel_rtile_pcie_ast_0.p1_cii +} + +proc do_rtile_pcie_gen5_1x16 {pci_vendor_id pci_device_id usr_clkfreq} { + set_instance_parameter_value intel_rtile_pcie_ast_0 core16_pf0_pci_type0_device_id_hwtcl $pci_device_id + set_instance_parameter_value intel_rtile_pcie_ast_0 core16_pf0_pci_type0_vendor_id_user_hwtcl $pci_vendor_id + set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen5 1x16, Interface - 1024 bit} + set_instance_parameter_value intel_rtile_pcie_ast_0 g5_pld_clkfreq_user_hwtcl $usr_clkfreq +} + +proc do_rtile_pcie_gen4_1x16 {pci_vendor_id pci_device_id usr_clkfreq} { + set_instance_parameter_value intel_rtile_pcie_ast_0 core16_pf0_pci_type0_device_id_hwtcl $pci_device_id + set_instance_parameter_value intel_rtile_pcie_ast_0 core16_pf0_pci_type0_vendor_id_user_hwtcl $pci_vendor_id + set_instance_parameter_value intel_rtile_pcie_ast_0 {top_topology_hwtcl} {Gen4 1x16, Interface - 512 bit} + set_instance_parameter_value intel_rtile_pcie_ast_0 g4_pld_clkfreq_single_user_hwtcl $usr_clkfreq +} + +proc do_rtile_pcie_common {} { + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cap_slot_clk_config_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_addr_size0_attr_user_hwtcl} {767} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_pf_en0_attr_user_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_cii_range_0_k_cii_start_addr0_attr_user_hwtcl} {3328} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_enable_cii_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_address_width_user_hwtcl} {26} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar0_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar2_address_width_user_hwtcl} {24} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_bar2_type_user_hwtcl} {64-bit non-prefetchable memory} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_pf0_class_code_hwtcl} {131072} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_user_vsec_cap_enable_hwtcl} {1} + set_instance_parameter_value intel_rtile_pcie_ast_0 {core16_virtual_pf0_user_vsec_offset_hwtcl} {3328} + + set_interface_property p0_cii EXPORT_OF intel_rtile_pcie_ast_0.p0_cii +} diff --git a/core/top/fpga_common.vhd b/core/top/fpga_common.vhd index 26e0a11c0..65268415b 100644 --- a/core/top/fpga_common.vhd +++ b/core/top/fpga_common.vhd @@ -379,10 +379,12 @@ architecture FULL of FPGA_COMMON is end if; end if; - if (PCIE_ENDPOINT_TYPE="R_TILE") then -- Gen5 mode only - if (PCIE_ENDPOINT_MODE = 0) then -- x16 + if (PCIE_ENDPOINT_TYPE="R_TILE") then -- Gen4/Gen5 mode only + if (PCIE_ENDPOINT_MODE = 0 and PCIE_GEN = 4) then -- x16 + pcie_mfb_regions := 2; --2x256b AVST + elsif (PCIE_ENDPOINT_MODE = 0 and PCIE_GEN = 5) then -- x16 pcie_mfb_regions := 4; --4x256b AVST - elsif (PCIE_ENDPOINT_MODE = 1) then --x8x8 + elsif (PCIE_ENDPOINT_MODE = 1 and PCIE_GEN = 5) then --x8x8 pcie_mfb_regions := 2; --2x256b AVST end if; end if; @@ -412,7 +414,7 @@ architecture FULL of FPGA_COMMON is -- 256b@~500MHz PCIe stream to 512b@200MHz PTC-DMA stream pcie_mfb_regions := pcie_mfb_regions*2; end if; - if (PCIE_ENDPOINT_TYPE="R_TILE" and PCIE_ENDPOINT_MODE = 0) then --TODO + if (PCIE_ENDPOINT_TYPE="R_TILE" and PCIE_ENDPOINT_MODE = 0 and PCIE_GEN = 5) then --TODO -- 1024b@~250MHz PCIe stream to 512b@200MHz PTC-DMA stream pcie_mfb_regions := pcie_mfb_regions/2; end if; From 97a32c4503ca9e7ed76fb124d9707ca2b4c65724 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Fri, 7 Feb 2025 13:03:41 +0100 Subject: [PATCH 4/7] fix(cards): fix DMA_ENDPOINTS calculation on R-Tile cards --- cards/bittware/ia-440i/src/fpga.vhd | 2 +- cards/reflexces/agi-fh400g/src/fpga.vhd | 15 +-------------- cards/terasic/a2700/src/fpga.vhd | 15 +-------------- 3 files changed, 3 insertions(+), 29 deletions(-) diff --git a/cards/bittware/ia-440i/src/fpga.vhd b/cards/bittware/ia-440i/src/fpga.vhd index e771a1818..b24f4d354 100644 --- a/cards/bittware/ia-440i/src/fpga.vhd +++ b/cards/bittware/ia-440i/src/fpga.vhd @@ -74,7 +74,7 @@ architecture FULL of FPGA is constant MISC_IN_WIDTH : natural := 4; constant MISC_OUT_WIDTH : natural := 4; constant ETH_LANES : natural := 8; - constant DMA_ENDPOINTS : natural := tsel(PCIE_ENDPOINT_MODE=1,PCIE_ENDPOINTS,2*PCIE_ENDPOINTS); + constant DMA_ENDPOINTS : natural := tsel(DMA_TYPE=3, 4, 1); -- 400G DMA Medusa = 4x DMA_ENDPOINT constant STATUS_LEDS : natural := 2; -- fake, this board has only 1 status LED signal status_led_g : std_logic_vector(STATUS_LEDS-1 downto 0); diff --git a/cards/reflexces/agi-fh400g/src/fpga.vhd b/cards/reflexces/agi-fh400g/src/fpga.vhd index 530292eb7..7496068d9 100644 --- a/cards/reflexces/agi-fh400g/src/fpga.vhd +++ b/cards/reflexces/agi-fh400g/src/fpga.vhd @@ -362,26 +362,13 @@ architecture FULL of FPGA is ); end component emif_agi027_cal; - function f_dma_endpoints(PCIE_ENDPOINTS : natural; PCIE_EP_MODE : natural; PCIE_GEN : natural) return natural is - variable dma_ep_v : natural; - begin - dma_ep_v := PCIE_ENDPOINTS; - if (PCIE_EP_MODE = 0) then - dma_ep_v := 2*dma_ep_v; - end if; - if (PCIE_GEN = 5) then - dma_ep_v := 2*dma_ep_v; - end if; - return dma_ep_v; - end function; - constant PCIE_LANES : integer := 16; constant PCIE_CLKS : integer := 2; constant PCIE_CONS : integer := 2; constant MISC_IN_WIDTH : integer := 64; constant MISC_OUT_WIDTH : integer := 64 + 5; constant ETH_LANES : integer := 8; - constant DMA_ENDPOINTS : integer := f_dma_endpoints(PCIE_ENDPOINTS,PCIE_ENDPOINT_MODE,PCIE_GEN); + constant DMA_ENDPOINTS : integer := tsel(DMA_TYPE=3, 4, 1); -- 400G DMA Medusa = 4x DMA_ENDPOINT constant USE_SODIMM_MEM : boolean := not TEST_FW_PCIE1_ONBOARD_DDR4; constant MEM_PORTS : integer := tsel(USE_SODIMM_MEM,2,1); constant MEM_ADDR_WIDTH : integer := tsel(USE_SODIMM_MEM,29,26); --HPS:26, SODIMM:29; diff --git a/cards/terasic/a2700/src/fpga.vhd b/cards/terasic/a2700/src/fpga.vhd index a72fbb706..f51809432 100644 --- a/cards/terasic/a2700/src/fpga.vhd +++ b/cards/terasic/a2700/src/fpga.vhd @@ -293,26 +293,13 @@ architecture FULL of FPGA is ); end component sodimm_cal; - function f_dma_endpoints(PCIE_ENDPOINTS : natural; PCIE_EP_MODE : natural; PCIE_GEN : natural) return natural is - variable dma_ep_v : natural; - begin - dma_ep_v := PCIE_ENDPOINTS; - if (PCIE_EP_MODE = 0) then - dma_ep_v := 2*dma_ep_v; - end if; - if (PCIE_GEN = 5) then - dma_ep_v := 2*dma_ep_v; - end if; - return dma_ep_v; - end function; - constant PCIE_LANES : integer := 16; constant PCIE_CLKS : integer := 2; constant PCIE_CONS : integer := 1; constant MISC_IN_WIDTH : integer := 64; constant MISC_OUT_WIDTH : integer := 64 + 5; constant ETH_LANES : integer := 8; - constant DMA_ENDPOINTS : integer := f_dma_endpoints(PCIE_ENDPOINTS,PCIE_ENDPOINT_MODE,PCIE_GEN); + constant DMA_ENDPOINTS : integer := tsel(DMA_TYPE=3, 4, 1); -- 400G DMA Medusa = 4x DMA_ENDPOINT constant MEM_PORTS : integer := DDR4_PORTS; constant MEM_ADDR_WIDTH : integer := 27; constant MEM_DATA_WIDTH : integer := 512; From be7117b9ff2615ea9bf2bb153bcbda66c21aa621 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Fri, 7 Feb 2025 14:47:10 +0100 Subject: [PATCH 5/7] fix(minimal): set DMA channels to 32 on IA-440i card --- apps/minimal/build/ia-440i/app_conf.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/apps/minimal/build/ia-440i/app_conf.tcl b/apps/minimal/build/ia-440i/app_conf.tcl index e458289f4..8f87bedcd 100644 --- a/apps/minimal/build/ia-440i/app_conf.tcl +++ b/apps/minimal/build/ia-440i/app_conf.tcl @@ -14,8 +14,8 @@ # DMA parameters: # ------------------------------------------------------------------------------ # The minimum number of RX/TX DMA channels for this card is 16. -set DMA_RX_CHANNELS 16 -set DMA_TX_CHANNELS 16 +set DMA_RX_CHANNELS 32 +set DMA_TX_CHANNELS 32 # In blocking mode, packets are dropped only when the RX DMA channel is off. # In non-blocking mode, packets are dropped whenever they cannot be sent. set DMA_RX_BLOCKING_MODE true From fa26b3476545e9ba89b5b0f341de07463fc2f03d Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Fri, 7 Feb 2025 16:13:53 +0100 Subject: [PATCH 6/7] perf(dma-wrapper): register DMA Calypte reset for better timing --- core/comp/dma/dma_mod/wrapper/Modules.tcl | 2 +- .../wrapper/dma_calypte_wrapper_arch.vhd | 20 ++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/core/comp/dma/dma_mod/wrapper/Modules.tcl b/core/comp/dma/dma_mod/wrapper/Modules.tcl index 6a7c79b3f..b062dbc39 100644 --- a/core/comp/dma/dma_mod/wrapper/Modules.tcl +++ b/core/comp/dma/dma_mod/wrapper/Modules.tcl @@ -28,11 +28,11 @@ lappend PACKAGES "$OFM_PATH/comp/base/pkg/dma_bus_pack.vhd" lappend MOD "$ENTITY_BASE/dma_wrapper_ent.vhd" lappend COMPONENTS [ list "MI_ASYNC" $MI_ASYNC_BASE "FULL" ] +lappend COMPONENTS [ list "ASYNC_RESET" $ASYNC_RESET_BASE "FULL" ] if { $ARCHGRP == "MEDUSA" } { lappend COMPONENTS [ list "MI_SPLITTER_PLUS_GEN" $MI_SPLITTER_PLUS_GEN_BASE "FULL" ] - lappend COMPONENTS [ list "ASYNC_RESET" $ASYNC_RESET_BASE "FULL" ] lappend COMPONENTS [ list "DMA_MEDUSA" $DMA_MEDUSA_BASE "FULL" ] # Source files for implemented component diff --git a/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd b/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd index 8327d7742..b3e67e19b 100644 --- a/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd +++ b/core/comp/dma/dma_mod/wrapper/dma_calypte_wrapper_arch.vhd @@ -205,6 +205,10 @@ architecture CALYPTE of DMA_WRAPPER is signal st_sp_dbg_chan : slv_array_t(DMA_STREAMS -1 downto 0)(DMA_MFB_REGIONS*log2(TX_CHANNELS) -1 downto 0); signal st_sp_dbg_meta : slv_array_t(DMA_STREAMS -1 downto 0)(DMA_MFB_REGIONS*ST_SP_DBG_META_WIDTH -1 downto 0); signal force_reset_dbg : std_logic_vector(DMA_STREAMS-1 downto 0); + + signal s_dma_reset_async : std_logic_vector(DMA_STREAMS-1 downto 0); + signal s_dma_reset : std_logic_vector(DMA_STREAMS-1 downto 0); + begin assert (DMA_STREAMS = PCIE_ENDPOINTS) @@ -696,6 +700,20 @@ begin MI_DRDY => mi_dmagen_drdy(i)(1) ); + s_dma_reset_async(i) <= PCIE_USR_RESET(i) or force_reset_dbg(i); + + dma_rst_i : entity work.ASYNC_RESET + generic map ( + TWO_REG => false, + OUT_REG => true, + REPLICAS => 1 + ) + port map ( + CLK => PCIE_USR_CLK(i), + ASYNC_RST => s_dma_reset_async(i), + OUT_RST(0) => s_dma_reset(i) + ); + --============================================================================================== -- DMA Calypte Module --============================================================================================== @@ -740,7 +758,7 @@ begin ) port map( CLK => PCIE_USR_CLK(i), - RESET => PCIE_USR_RESET(i) or force_reset_dbg(i), + RESET => s_dma_reset(i), USR_RX_MFB_META_HDR_META => rx_usr_mfb_meta_hdr_meta_tst(i), USR_RX_MFB_META_CHAN => rx_usr_mfb_meta_channel_tst(i), From 550ff5ca77117cec99f328f1c3934d10491cf623 Mon Sep 17 00:00:00 2001 From: Jakub Cabal Date: Mon, 10 Feb 2025 10:07:53 +0100 Subject: [PATCH 7/7] build(minimal): use 16 channels for DMA Calypte on R-Tile FPGAs --- apps/minimal/build/a2700/app_conf.tcl | 14 +++++++++++--- apps/minimal/build/agi-fh400g/app_conf.tcl | 14 +++++++++++--- apps/minimal/build/ia-440i/app_conf.tcl | 14 +++++++++++--- 3 files changed, 33 insertions(+), 9 deletions(-) diff --git a/apps/minimal/build/a2700/app_conf.tcl b/apps/minimal/build/a2700/app_conf.tcl index d4d0cdbeb..dfa3bd3bb 100644 --- a/apps/minimal/build/a2700/app_conf.tcl +++ b/apps/minimal/build/a2700/app_conf.tcl @@ -9,9 +9,17 @@ # ------------------------------------------------------------------------------ # DMA parameters: # ------------------------------------------------------------------------------ -# The minimum number of RX/TX DMA channels for this card is 32. -set DMA_RX_CHANNELS 32 -set DMA_TX_CHANNELS 32 + +if {$env(DMA_TYPE) == 4} { + # DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels. + set DMA_RX_CHANNELS 16 + set DMA_TX_CHANNELS 16 +} else { + # 400G DMA Medusa requires at least 32 channels. + set DMA_RX_CHANNELS 32 + set DMA_TX_CHANNELS 32 +} + # In blocking mode, packets are dropped only when the RX DMA channel is off. # In non-blocking mode, packets are dropped whenever they cannot be sent. set DMA_RX_BLOCKING_MODE true diff --git a/apps/minimal/build/agi-fh400g/app_conf.tcl b/apps/minimal/build/agi-fh400g/app_conf.tcl index 77d95a2bc..7401bf0ff 100644 --- a/apps/minimal/build/agi-fh400g/app_conf.tcl +++ b/apps/minimal/build/agi-fh400g/app_conf.tcl @@ -10,9 +10,17 @@ # ------------------------------------------------------------------------------ # DMA parameters: # ------------------------------------------------------------------------------ -# The minimum number of RX/TX DMA channels for this card is 32. -set DMA_RX_CHANNELS 32 -set DMA_TX_CHANNELS 32 + +if {$env(DMA_TYPE) == 4} { + # DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels. + set DMA_RX_CHANNELS 16 + set DMA_TX_CHANNELS 16 +} else { + # 400G DMA Medusa requires at least 32 channels. + set DMA_RX_CHANNELS 32 + set DMA_TX_CHANNELS 32 +} + # In blocking mode, packets are dropped only when the RX DMA channel is off. # In non-blocking mode, packets are dropped whenever they cannot be sent. set DMA_RX_BLOCKING_MODE true diff --git a/apps/minimal/build/ia-440i/app_conf.tcl b/apps/minimal/build/ia-440i/app_conf.tcl index 8f87bedcd..04e969bf4 100644 --- a/apps/minimal/build/ia-440i/app_conf.tcl +++ b/apps/minimal/build/ia-440i/app_conf.tcl @@ -13,9 +13,17 @@ # ------------------------------------------------------------------------------ # DMA parameters: # ------------------------------------------------------------------------------ -# The minimum number of RX/TX DMA channels for this card is 16. -set DMA_RX_CHANNELS 32 -set DMA_TX_CHANNELS 32 + +if {$env(DMA_TYPE) == 4} { + # DMA Calypte not meet timing on R-Tile FPGAs with more than 16 channels. + set DMA_RX_CHANNELS 16 + set DMA_TX_CHANNELS 16 +} else { + # 400G DMA Medusa requires at least 32 channels. + set DMA_RX_CHANNELS 32 + set DMA_TX_CHANNELS 32 +} + # In blocking mode, packets are dropped only when the RX DMA channel is off. # In non-blocking mode, packets are dropped whenever they cannot be sent. set DMA_RX_BLOCKING_MODE true