diff --git a/core/comp/eth/network_mod/uvm/Modules.tcl b/core/comp/eth/network_mod/uvm/Modules.tcl index d34263bf9..06367e4a9 100644 --- a/core/comp/eth/network_mod/uvm/Modules.tcl +++ b/core/comp/eth/network_mod/uvm/Modules.tcl @@ -34,4 +34,10 @@ if {$ARCHGRP == "E_TILE"} { lappend MOD "$ENTITY_BASE/tbench/f-tile/env/pkg.sv" \ "$ENTITY_BASE/tbench/f-tile/dut.sv" \ "$ENTITY_BASE/tbench/f-tile/testbench.sv" +} elseif {$ARCHGRP == "CMAC"} { + lappend COMPONENTS [ list "SV_LOGIC_VECTOR_ARRAY_LBUS" "$SV_UVM_BASE/logic_vector_array_lbus" "FULL"] + lappend MOD "$ENTITY_BASE/tbench/cmac/env/pkg.sv" \ + "$ENTITY_BASE/tbench/cmac/dut.sv" \ + "$ENTITY_BASE/tbench/cmac/property.sv" \ + "$ENTITY_BASE/tbench/cmac/testbench.sv" } diff --git a/core/comp/eth/network_mod/uvm/signals_sig.fdo b/core/comp/eth/network_mod/uvm/signals_sig.fdo index 6d0aee04d..3cabab069 100644 --- a/core/comp/eth/network_mod/uvm/signals_sig.fdo +++ b/core/comp/eth/network_mod/uvm/signals_sig.fdo @@ -4,7 +4,7 @@ # SPDX-License-Identifier: BSD-3-Clause -set ETH_PORTS 2 +set ETH_PORTS 4 add wave -divider "CLK" add_wave "-noupdate -color yellow" /testbench/CLK_USR diff --git a/core/comp/eth/network_mod/uvm/tbench/base/env/env.sv b/core/comp/eth/network_mod/uvm/tbench/base/env/env.sv index 9609698a7..f09efca43 100644 --- a/core/comp/eth/network_mod/uvm/tbench/base/env/env.sv +++ b/core/comp/eth/network_mod/uvm/tbench/base/env/env.sv @@ -76,6 +76,10 @@ class env #( return m_scoreboard.used(); endfunction + virtual function void eth_full_speed_set(); + `uvm_fatal(this.get_full_name(), "\n\tIf you want to run full speed test you have to specified full speed sequece for ethernet"); + endfunction + // Create base components of environment. function void build_phase(uvm_phase phase); uvm_reset::config_item cfg_rst; diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv new file mode 100644 index 000000000..3faa2e320 --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv @@ -0,0 +1,180 @@ +// dut.sv: Xilinx CMAC DUT +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +module DUT #( + string ETH_CORE_ARCH, + int unsigned ETH_PORTS, + int unsigned ETH_PORT_SPEED[ETH_PORTS-1 : 0], + + int unsigned ETH_PORT_CHAN [ETH_PORTS-1 : 0], + int unsigned EHIP_PORT_TYPE [ETH_PORTS-1 : 0], + int unsigned ETH_PORT_RX_MTU[ETH_PORTS-1 : 0], + int unsigned ETH_PORT_TX_MTU[ETH_PORTS-1 : 0], + + int unsigned LANES, + + int unsigned QSFP_PORTS, + int unsigned QSFP_I2C_PORTS, + int unsigned QSFP_I2C_TRISTATE, + + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + int unsigned ITEM_WIDTH, + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH, + + int unsigned MI_DATA_WIDTH_PHY, + int unsigned MI_ADDR_WIDTH_PHY, + + int unsigned LANE_RX_POLARITY, + int unsigned LANE_TX_POLARITY, + + int unsigned RESET_WIDTH, + + string DEVICE, + string BOARD +)( + input wire logic CLK_ETH[ETH_PORTS], + input wire logic CLK_USR, + input wire logic CLK_MI, + input wire logic CLK_MI_PHY, + input wire logic CLK_MI_PMD, + input wire logic CLK_TSU, + + reset_if.dut rst_usr, + reset_if.dut rst_eth[ETH_PORTS], + reset_if.dut rst_mi, + reset_if.dut rst_mi_phy, + reset_if.dut rst_mi_pmd, + reset_if.dut rst_tsu, + + lbus_if.dut_tx eth_tx[ETH_PORTS], + lbus_if.dut_rx eth_rx[ETH_PORTS], + + mfb_if.dut_rx usr_rx [ETH_PORTS], + mfb_if.dut_tx usr_tx_data[ETH_PORTS], + mvb_if.dut_tx usr_tx_hdr [ETH_PORTS], + + mi_if.dut_slave mi, + mi_if.dut_slave mi_phy, + mi_if.dut_slave mi_pmd, + + mvb_if.dut_rx tsu +); + DUT_BASE #( + .ETH_CORE_ARCH (ETH_CORE_ARCH ), + .ETH_PORTS (ETH_PORTS ), + .ETH_PORT_SPEED (ETH_PORT_SPEED ), + .ETH_PORT_CHAN (ETH_PORT_CHAN ), + .EHIP_PORT_TYPE (EHIP_PORT_TYPE ), + .ETH_PORT_RX_MTU (ETH_PORT_RX_MTU ), + .ETH_PORT_TX_MTU (ETH_PORT_TX_MTU ), + .LANES (LANES ), + .QSFP_PORTS (QSFP_PORTS ), + .QSFP_I2C_PORTS (QSFP_I2C_PORTS ), + .QSFP_I2C_TRISTATE(QSFP_I2C_TRISTATE), + .ETH_TX_HDR_WIDTH (ETH_TX_HDR_WIDTH ), + .ETH_RX_HDR_WIDTH (ETH_RX_HDR_WIDTH ), + .REGIONS (REGIONS ), + .REGION_SIZE (REGION_SIZE ), + .BLOCK_SIZE (BLOCK_SIZE ), + .ITEM_WIDTH (ITEM_WIDTH ), + .MI_DATA_WIDTH (MI_DATA_WIDTH ), + .MI_ADDR_WIDTH (MI_ADDR_WIDTH ), + .MI_DATA_WIDTH_PHY(MI_DATA_WIDTH_PHY), + .MI_ADDR_WIDTH_PHY(MI_ADDR_WIDTH_PHY), + .LANE_RX_POLARITY (LANE_RX_POLARITY ), + .LANE_TX_POLARITY (LANE_TX_POLARITY ), + .RESET_WIDTH (RESET_WIDTH ), + .DEVICE (DEVICE ), + .BOARD (BOARD ) + ) DUT_BASE_U ( + .CLK_USR (CLK_USR ), + .CLK_MI (CLK_MI ), + .CLK_MI_PHY (CLK_MI_PHY), + .CLK_MI_PMD (CLK_MI_PMD), + .CLK_TSU (CLK_TSU ), + + .rst_usr (rst_usr ), + .rst_eth (rst_eth ), + .rst_mi (rst_mi ), + .rst_mi_phy (rst_mi_phy), + .rst_mi_pmd (rst_mi_pmd), + .rst_tsu (rst_tsu ), + + .usr_rx (usr_rx ), + .usr_tx_data (usr_tx_data), + .usr_tx_hdr (usr_tx_hdr ), + + .mi (mi ), + .mi_phy (mi_phy), + .mi_pmd (mi_pmd), + + .tsu (tsu) + ); + + generate; + for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin + localparam int unsigned ETH_PORT_CHAN_LOCAL = ETH_PORT_CHAN[eth_it]; + initial assert(ETH_PORT_CHAN_LOCAL == 1); + + wire logic [4*128-1 : 0] eth_rx_data; + + // ------- // + // TX side // + // ------- // + + for (genvar slice = 0; slice < 4; slice++) begin + initial begin + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_data[slice] = {<<8{eth_tx[eth_it].DATA[128*(slice+1)-1 -: 128]}}; // Byte reordering + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_mty [slice] = eth_tx[eth_it].MTY[4*(slice+1)-1 -: 4]; + end + end + + initial begin + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_ena = eth_tx[eth_it].ENA; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_sop = eth_tx[eth_it].SOP; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_eop = eth_tx[eth_it].EOP; + force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_err = eth_tx[eth_it].ERR; + end + + assign eth_tx[eth_it].RDY = 1'b1; // Always ready + + // ------- // + // RX side // + // ------- // + + assign eth_rx_data = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_data}}; + for (genvar segment = 0; segment < 4; segment++) begin + wire logic [128-1 : 0] segment_data; + + assign segment_data = eth_rx_data[128*(segment+1)-1 -: 128]; + assign eth_rx[eth_it].DATA[128*(segment+1)-1 -: 128] = {<<8{segment_data}}; // Byte reordering + end + + assign eth_rx[eth_it].ENA = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_ena; + assign eth_rx[eth_it].SOP = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_sop; + assign eth_rx[eth_it].EOP = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_eop; + assign eth_rx[eth_it].ERR = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_err; + assign eth_rx[eth_it].MTY = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_mty}}; + + initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_rdy = eth_rx[eth_it].RDY; + + // ----- // + // Other // + // ----- // + + // CLK connection + initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH[eth_it]; + end + endgenerate + +endmodule diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/env/env.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/env/env.sv new file mode 100644 index 000000000..89b0a649b --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/env/env.sv @@ -0,0 +1,154 @@ +// env.sv: Environment for the Xilinx CMAC device +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +class env #( + string ETH_CORE_ARCH, + int unsigned ETH_PORTS, + + int unsigned ETH_PORT_SPEED[ETH_PORTS-1:0], + int unsigned ETH_PORT_CHAN[ETH_PORTS-1 : 0], + + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + int unsigned ITEM_WIDTH, + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH +) extends uvm_network_mod_env::env #( + ETH_CORE_ARCH, + ETH_PORTS, + ETH_PORT_SPEED, + ETH_PORT_CHAN, + ETH_TX_HDR_WIDTH, + ETH_RX_HDR_WIDTH, + REGIONS, + REGION_SIZE, + BLOCK_SIZE, + ITEM_WIDTH, + MI_DATA_WIDTH, + MI_ADDR_WIDTH + ); + `uvm_component_param_utils(uvm_network_mod_cmac_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH)) + + // BYTE ARRAY LBUS environments + protected uvm_logic_vector_array_lbus::env_tx m_eth_tx[ETH_PORTS]; + protected uvm_logic_vector_array_lbus::env_rx m_eth_rx[ETH_PORTS]; + + tx_error_expander m_tx_error_expander[ETH_PORTS]; + + // Constructor + function new(string name = "env", uvm_component parent = null); + super.new(name, parent); + endfunction + + + virtual function void eth_full_speed_set(); + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + uvm_logic_vector_array_lbus::sequence_library_tx::type_id::set_inst_override( + uvm_logic_vector_array_lbus::sequence_library_tx_fullspeed::get_type(), + $sformatf("m_eth_tx_%0d.*", it), + this + ); + + uvm_lbus::sequence_library_rx::type_id::set_inst_override( + uvm_lbus::sequence_library_rx_fullspeed::get_type(), + $sformatf("m_eth_rx_%0d.*", it), + this + ); + end + endfunction + + function void build_phase(uvm_phase phase); + // -------------------------------------- // + // Overriding the base components/objects // + // -------------------------------------- // + + uvm_network_mod_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_inst_override( + uvm_network_mod_cmac_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type(), + "m_sequencer.*", + this + ); + + uvm_network_mod_env::virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_type_override( + uvm_network_mod_cmac_env::virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type() + ); + uvm_network_mod_env::virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_type_override( + uvm_network_mod_cmac_env::virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type() + ); + uvm_network_mod_env::virt_sequence_simple #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_type_override( + uvm_network_mod_cmac_env::virt_sequence_simple #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type() + ); + uvm_network_mod_env::virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_type_override( + uvm_network_mod_cmac_env::virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type() + ); + + // Build of base environment + super.build_phase(phase); + + // ------------------------- // + // Build of CMAC environment // + // ------------------------- // + + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + uvm_logic_vector_array_lbus::config_item cfg_eth_tx; + uvm_logic_vector_array_lbus::config_item cfg_eth_rx; + + cfg_eth_tx = new(); + cfg_eth_tx.active = UVM_ACTIVE; + cfg_eth_tx.interface_name = $sformatf("vif_eth_tx_%0d", it); + uvm_config_db #(uvm_logic_vector_array_lbus::config_item)::set(this, $sformatf("m_eth_tx_%0d", it), "m_config", cfg_eth_tx); + m_eth_tx[it] = uvm_logic_vector_array_lbus::env_tx::type_id::create($sformatf("m_eth_tx_%0d", it), this); + + cfg_eth_rx = new(); + cfg_eth_rx.active = UVM_ACTIVE; + cfg_eth_rx.interface_name = $sformatf("vif_eth_rx_%0d", it); + uvm_config_db #(uvm_logic_vector_array_lbus::config_item)::set(this, $sformatf("m_eth_rx_%0d", it), "m_config", cfg_eth_rx); + m_eth_rx[it] = uvm_logic_vector_array_lbus::env_rx::type_id::create($sformatf("m_eth_rx_%0d", it), this); + + m_tx_error_expander[it] = tx_error_expander::type_id::create($sformatf("m_tx_error_expander_%0d", it), this); + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + // Connection of resets + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + m_eth_rst[it].sync_connect(m_eth_tx[it].reset_sync); + m_eth_rst[it].sync_connect(m_eth_rx[it].reset_sync); + end + + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + // TX packet + m_eth_tx[it].analysis_port_packet.connect(m_scoreboard.eth_rx_data[it]); + // TX error + m_eth_tx[it].analysis_port_error.connect(m_tx_error_expander[it].analysis_export); + m_tx_error_expander[it].analysis_port.connect(m_scoreboard.eth_rx_hdr[it]); + + // RX packet + m_eth_rx[it].analysis_port_packet.connect(m_scoreboard.eth_tx_data[it]); + // RX error + m_eth_rx[it].analysis_port_error.connect(m_scoreboard.eth_tx_hdr[it]); + end + + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH) cast_sequencer_port; + assert($cast(cast_sequencer_port, m_sequencer.port[it])) + else begin + `uvm_fatal(this.get_full_name(), $sformatf("\n\tCast failed: %s", m_sequencer.port[it].get_full_name())) + end + + cast_sequencer_port.eth_tx_packet = m_eth_tx[it].m_sequencer.packet; + cast_sequencer_port.eth_tx_error = m_eth_tx[it].m_sequencer.error; + cast_sequencer_port.eth_rx = m_eth_rx[it].m_sequencer; + end + endfunction + +endclass diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/env/pkg.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/env/pkg.sv new file mode 100644 index 000000000..7d7aad03d --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/env/pkg.sv @@ -0,0 +1,22 @@ +// pkg.sv: Package for the Xilinx CMAC environment +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +`ifndef NETWORK_MOD_CMAC_ENV_SV +`define NETWORK_MOD_CMAC_ENV_SV + +package uvm_network_mod_cmac_env; + + `include "uvm_macros.svh" + import uvm_pkg::*; + + `include "sequencer_port.sv" + `include "sequence.sv" + `include "tx_error_expander.sv" + `include "env.sv" + +endpackage + +`endif diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/env/sequence.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/env/sequence.sv new file mode 100644 index 000000000..aa67656d3 --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/env/sequence.sv @@ -0,0 +1,533 @@ +// sequence.sv: Virtual sequences +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Radek Iša +// Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +class virt_sequence_port #( + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned ITEM_WIDTH, + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + + int unsigned ETH_PORT_CHAN, + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH +) extends uvm_network_mod_env::virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); + `uvm_object_param_utils(uvm_network_mod_cmac_env::virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)) + `uvm_declare_p_sequencer(uvm_network_mod_cmac_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)) + + uvm_sequence #(uvm_logic_vector_array::sequence_item #(8)) eth_tx_packet; + uvm_sequence #(uvm_logic_vector::sequence_item #(1)) eth_tx_error; + uvm_sequence #(uvm_lbus::sequence_item) eth_rx; + + protected uvm_common::sequences_cfg_sync #(2) seq_sync_eth_tx; + + protected uvm_logic_vector_array::config_sequence eth_tx_seq_cfg; + + // Constructor + function new(string name = "virt_sequence_port"); + super.new(name); + endfunction + + function int unsigned rx_transaction_count(); + return super.rx_transaction_count() + seq_sync_eth_tx.data.transactions[0]; + endfunction + + function void packet_size_set(uvm_logic_vector_array::config_sequence usr_rx_seq_cfg, uvm_logic_vector_array::config_sequence eth_tx_seq_cfg); + super.packet_size_set(usr_rx_seq_cfg); + this.eth_tx_seq_cfg = eth_tx_seq_cfg; + endfunction + + task pre_body(); + uvm_logic_vector_array::sequence_lib #(8) lib_eth_tx_packet; + uvm_lbus::sequence_library_rx seq_eth_rx; + + super.pre_body(); + + // TX eth packet sequence + seq_sync_eth_tx = uvm_common::sequences_cfg_sync#(2)::type_id::create("seq_sync_eth_tx", m_sequencer); + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.eth_tx_packet, "", "state", seq_sync_eth_tx.cfg[0]); + lib_eth_tx_packet = uvm_logic_vector_array::sequence_lib #(8)::type_id::create("eth_tx_packet", p_sequencer.eth_tx_packet); + lib_eth_tx_packet.max_random_count = 100; + lib_eth_tx_packet.min_random_count = 10; + lib_eth_tx_packet.init_sequence(); + + // TX eth error sequence + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.eth_tx_error, "", "state", seq_sync_eth_tx.cfg[1]); + eth_tx_error = uvm_network_mod_env::sequence_logic_vector#(1)::type_id::create("eth_tx_error", p_sequencer.eth_tx_error); + + // RX eth sequence + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.eth_rx, "", "state", seq_sync_end); + seq_eth_rx = uvm_lbus::sequence_library_rx::type_id::create("eth_rx", p_sequencer.eth_rx); + seq_eth_rx.init_sequence(); + + eth_tx_packet = lib_eth_tx_packet; + eth_rx = seq_eth_rx; + endtask + + task body(); + uvm_status_e status; + uvm_reg_data_t data; + uvm_common::sequence_cfg state; + + assert(uvm_config_db#(uvm_common::sequence_cfg)::get(m_sequencer, "", "state", state)); + assert(state != null); + + seq_sync_end.clear(); + + fork + do begin + assert(eth_rst.randomize()); + eth_rst.start(p_sequencer.eth_rst); + end while (!seq_sync_end.stopped()); + join_none + + #(400ns); + + for (int unsigned it = 0; it < ETH_PORT_CHAN; it++) begin + fork + p_sequencer.regmodel.channel[it].rx_mac.base.enable.write(status, 1'h1); + p_sequencer.regmodel.channel[it].tx_mac.enable.write(status, 1'h1); + join; + + fork + p_sequencer.regmodel.channel[it].rx_mac.base.enable.read(status, data); + p_sequencer.regmodel.channel[it].tx_mac.enable.read(status, data); + join; + end + + fork + do begin + assert(usr_rx_data.randomize()); + usr_rx_data.start(p_sequencer.usr_rx_data); + end while (!seq_sync_usr_rx.cfg[0].stopped()); + do begin + assert(usr_rx_meta.randomize()); + usr_rx_meta.start(p_sequencer.usr_rx_meta); + end while (!seq_sync_usr_rx.cfg[1].stopped()); + + do begin + assert(usr_tx_data.randomize()); + usr_tx_data.start(p_sequencer.usr_tx_data); + end while (!seq_sync_end.stopped()); + do begin + assert(usr_tx_hdr.randomize()); + usr_tx_hdr.start(p_sequencer.usr_tx_hdr); + end while (!seq_sync_end.stopped()); + + do begin + assert(eth_tx_packet.randomize()); + eth_tx_packet.start(p_sequencer.eth_tx_packet); + end while (!seq_sync_eth_tx.cfg[0].stopped()); + do begin + assert(eth_tx_error.randomize()); + eth_tx_error.start(p_sequencer.eth_tx_error); + end while (!seq_sync_eth_tx.cfg[1].stopped()); + + do begin + assert(eth_rx.randomize()); + eth_rx.start(p_sequencer.eth_rx); + end while (!seq_sync_end.stopped()); + join_none + + while ((state == null || !state.stopped()) && + (this.rx_transaction_count() < transactions_approx) + ) begin + #(300ns); + end + // Stop data sequences + seq_sync_usr_rx.send_stop(); + seq_sync_eth_tx.send_stop(); + + // Read statistics + for (int unsigned it = 0; it < ETH_PORT_CHAN; it++) begin + uvm_network_mod_env::read_rx_counters#(RX_MAC_COUNT) rx_stats; + uvm_network_mod_env::read_tx_counters tx_stats; + + rx_stats = uvm_network_mod_env::read_rx_counters#(RX_MAC_COUNT)::type_id::create("rx_stats", m_sequencer); + rx_stats.set_regmodel(p_sequencer.regmodel.channel[it].rx_mac); + tx_stats = uvm_network_mod_env::read_tx_counters::type_id::create("tx_stats", m_sequencer); + tx_stats.set_regmodel(p_sequencer.regmodel.channel[it].tx_mac); + + fork + rx_stats.start(null); + tx_stats.start(null); + join + + `uvm_info(this.get_full_name(), + $sformatf("RX channel %s base [%0d]\n\tSTATS trfc %0d cfc %0d dfc %0d bodfc %0d oroc %0d\n", m_sequencer.get_full_name(), it, rx_stats.trfc, rx_stats.cfc, rx_stats.dfc, rx_stats.bodfc, rx_stats.oroc), + UVM_LOW); + `uvm_info(this.get_full_name(), + $sformatf("RX channel %s rfc [%0d]\n\tcrc_err %0d\n\tover_mtu_addr %0d\n\t below_min_addr %0d\n\tbcast_frames_addr %0d\n\tmcast_frames_addr %0d\n\tfragment_frames_addr %0d\n\tjabber_frames_addr %0d\n\ttrans_octets_addr %0d\n\tframes_64_addr %0d\n\tframes_65_127_addr %0d\n\tframes_128_255_addr %0d\n\tframes_256_511_addr %0d\n\tframes_512_1023_addr %0d\n\tframes_1024_1518_addr %0d\n\tframes_over_1518_addr %0d\n\tframes_below_64_addr %0d\n\n", + m_sequencer.get_full_name(), it, rx_stats.crc_err, rx_stats.over_mtu_addr, rx_stats.below_min_addr, rx_stats.bcast_frames_addr, rx_stats.mcast_frames_addr, rx_stats.fragment_frames_addr, rx_stats.jabber_frames_addr, rx_stats.trans_octets_addr, + rx_stats.frames_64_addr, rx_stats.frames_65_127_addr, rx_stats.frames_128_255_addr, rx_stats.frames_256_511_addr, rx_stats.frames_512_1023_addr, rx_stats.frames_1024_1518_addr, rx_stats.frames_over_1518_addr, rx_stats.frames_below_64_addr), + UVM_LOW); + + `uvm_info(this.get_full_name(), + $sformatf("TX channel %s [%0d]\n\tSTATS tfc %0d soc %0d dfc %0d sfc %0d\n", m_sequencer.get_full_name(), it, tx_stats.tfc, tx_stats.soc, tx_stats.dfc, tx_stats.sfc), + UVM_LOW); + + fork + rx_stats.reset(); + tx_stats.reset(); + join + + fork + rx_stats.start(null); + tx_stats.start(null); + join + + `uvm_info(this.get_full_name(), + $sformatf("RX channel %s [%0d]\n\tAFTER RESET STATS trfc %0d cfc %0d dfc %0d bodfc %0d oroc %0d\n", m_sequencer.get_full_name(), it, rx_stats.trfc, rx_stats.cfc, rx_stats.dfc, rx_stats.bodfc, rx_stats.oroc), + UVM_LOW); + `uvm_info(this.get_full_name(), + $sformatf("RX channel %s rfc [%0d]\n\tcrc_err %0d\n\tover_mtu_addr %0d\n\t below_min_addr %0d\n\tbcast_frames_addr %0d\n\tmcast_frames_addr %0d\n\tfragment_frames_addr %0d\n\tjabber_frames_addr %0d\n\ttrans_octets_addr %0d\n\tframes_64_addr %0d\n\tframes_65_127_addr %0d\n\tframes_128_255_addr %0d\n\tframes_256_511_addr %0d\n\tframes_512_1023_addr %0d\n\tframes_1024_1518_addr %0d\n\tframes_over_1518_addr %0d\n\tframes_below_64_addr %0d\n\n", + m_sequencer.get_full_name(), it, rx_stats.crc_err, rx_stats.over_mtu_addr, rx_stats.below_min_addr, rx_stats.bcast_frames_addr, rx_stats.mcast_frames_addr, rx_stats.fragment_frames_addr, rx_stats.jabber_frames_addr, rx_stats.trans_octets_addr, + rx_stats.frames_64_addr, rx_stats.frames_65_127_addr, rx_stats.frames_128_255_addr, rx_stats.frames_256_511_addr, rx_stats.frames_512_1023_addr, rx_stats.frames_1024_1518_addr, rx_stats.frames_over_1518_addr, rx_stats.frames_below_64_addr), + UVM_LOW); + `uvm_info(this.get_full_name(), + $sformatf("TX channel %s [%0d]\n\tAFTER RESET STATS tfc %0d soc %0d dfc %0d sfc %0d\n", m_sequencer.get_full_name(), it, tx_stats.tfc, tx_stats.soc, tx_stats.dfc, tx_stats.sfc), + UVM_LOW); + + if (rx_stats.trfc != 0 || rx_stats.cfc != 0 || rx_stats.dfc != 0 || rx_stats.bodfc != 0 || /*rx_stats.oroc != 0 ||*/ + tx_stats.tfc != 0 || tx_stats.soc != 0 || tx_stats.dfc != 0 || tx_stats.sfc != 0) begin + `uvm_fatal(m_sequencer.get_full_name(), "Some statistic is not set to zero after reset!\n"); + end + end + + // Wait for the end of the data sequences + usr_rx_meta.wait_for_sequence_state(UVM_FINISHED); + usr_rx_data.wait_for_sequence_state(UVM_FINISHED); + eth_tx_packet.wait_for_sequence_state(UVM_FINISHED); + eth_tx_error.wait_for_sequence_state(UVM_FINISHED); + + // Stop other sequences + seq_sync_end.send_stop(); + // Wait for the end of the other sequences + eth_rst.wait_for_sequence_state(UVM_FINISHED); + usr_tx_data.wait_for_sequence_state(UVM_FINISHED); + usr_tx_hdr.wait_for_sequence_state(UVM_FINISHED); + eth_rx.wait_for_sequence_state(UVM_FINISHED); + endtask + +endclass + +class virt_sequence_port_stop #( + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned ITEM_WIDTH, + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + + int unsigned ETH_PORT_CHAN, + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH +) extends uvm_network_mod_env::virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); + `uvm_object_param_utils(uvm_network_mod_cmac_env::virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)); + `uvm_declare_p_sequencer(uvm_network_mod_cmac_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)) + + uvm_sequence #(uvm_logic_vector_array::sequence_item #(ITEM_WIDTH)) eth_tx_packet; + uvm_sequence #(uvm_logic_vector::sequence_item #(6)) eth_tx_error; + uvm_sequence #(uvm_lbus::sequence_item) eth_rx; + + protected uvm_common::sequences_cfg_sync#(2) seq_sync_eth_tx; + + protected uvm_logic_vector_array::config_sequence eth_tx_seq_cfg; + + // Constructor + function new(string name = "virt_sequence_port_stop"); + super.new(name); + endfunction + + function int unsigned rx_transaction_count(); + return super.rx_transaction_count() + seq_sync_eth_tx.data.transactions[0]; + endfunction + + function void packet_size_set(uvm_logic_vector_array::config_sequence usr_rx_seq_cfg, uvm_logic_vector_array::config_sequence eth_tx_seq_cfg); + super.packet_size_set(usr_rx_seq_cfg); + this.eth_tx_seq_cfg = eth_tx_seq_cfg; + endfunction + + task pre_body(); + uvm_logic_vector_array::sequence_lib#(ITEM_WIDTH) lib_eth_tx_packet; + uvm_lbus::sequence_library_rx seq_eth_rx; + + super.pre_body(); + + // TX eth packet sequence + seq_sync_eth_tx = uvm_common::sequences_cfg_sync#(2)::type_id::create("seq_sync_eth_tx", m_sequencer); + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.eth_tx_packet, "", "state", seq_sync_eth_tx.cfg[0]); + lib_eth_tx_packet = uvm_logic_vector_array::sequence_lib#(ITEM_WIDTH)::type_id::create("eth_tx_packet", p_sequencer.eth_tx_packet); + lib_eth_tx_packet.max_random_count = 100; + lib_eth_tx_packet.min_random_count = 10; + lib_eth_tx_packet.init_sequence(); + + // TX eth error sequence + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.eth_tx_error, "", "state", seq_sync_eth_tx.cfg[1]); + eth_tx_error = uvm_network_mod_env::sequence_logic_vector#(6)::type_id::create("eth_tx_error", p_sequencer.eth_tx_error); + + // RX eth sequence + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.eth_rx, "", "state", seq_sync_end); + seq_eth_rx = uvm_lbus::sequence_library_rx::type_id::create("eth_rx", p_sequencer.eth_rx); + seq_eth_rx.init_sequence(); + + eth_tx_packet = lib_eth_tx_packet; + eth_rx = seq_eth_rx; + endtask + + task body(); + uvm_common::sequence_cfg state; + + seq_sync_end.clear(); + + assert(uvm_config_db#(uvm_common::sequence_cfg)::get(m_sequencer, "", "state", state)) + else begin + `uvm_fatal(m_sequencer.get_full_name(), "\n\tCannot get a sequence port state object"); + end + + fork + do begin + assert(eth_rst.randomize()); + eth_rst.start(p_sequencer.eth_rst); + end while (!seq_sync_end.stopped()); + + do begin + assert(usr_tx_data.randomize()); + usr_tx_data.start(p_sequencer.usr_tx_data); + end while (!seq_sync_end.stopped()); + do begin + assert(usr_tx_hdr.randomize()); + usr_tx_hdr.start(p_sequencer.usr_tx_hdr); + end while (!seq_sync_end.stopped()); + + do begin + assert(eth_rx.randomize()); + eth_rx.start(p_sequencer.eth_rx); + end while (!seq_sync_end.stopped()); + join_none + + while(!state.stopped()) begin + #(300ns); + end + + // Stop the sequences + seq_sync_end.send_stop(); + // Wait for the end of the sequences + eth_rst.wait_for_sequence_state(UVM_FINISHED); + usr_tx_data.wait_for_sequence_state(UVM_FINISHED); + usr_tx_hdr.wait_for_sequence_state(UVM_FINISHED); + eth_rx.wait_for_sequence_state(UVM_FINISHED); + endtask + +endclass + +class virt_sequence_simple #( + int unsigned ETH_PORTS, + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned ITEM_WIDTH, + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + + int unsigned ETH_PORT_CHAN[ETH_PORTS], + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH +) extends uvm_network_mod_env::virt_sequence_simple #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); + `uvm_object_param_utils(uvm_network_mod_cmac_env::virt_sequence_simple #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)) + + protected uvm_logic_vector_array::config_sequence eth_tx_seq_cfg[ETH_PORTS]; + + // Constructor + function new(string name = "virt_sequence_simple"); + super.new(name); + endfunction + + task pre_body(); + super.pre_body(); + + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH) cast_virt_sequence_port; + assert($cast(cast_virt_sequence_port, port[it])) + else begin + `uvm_fatal(this.get_full_name(), "\n\tCast failed") + end + + cast_virt_sequence_port.packet_size_set(usr_rx_seq_cfg[it], eth_tx_seq_cfg[it]); + end + endtask + + function void packet_size_set(int unsigned min = 64, int unsigned max = 1500); + super.packet_size_set(min, max); + + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + eth_tx_seq_cfg[it] = new(); + eth_tx_seq_cfg[it].array_size_set(min, max); + end + endfunction + + task body(); + logic [ETH_PORTS-1:0] port_end = '0; + int unsigned transactions = 0; + + // Randomization + assert(usr_rst.randomize()); + assert(mi_rst.randomize()); + assert(mi_phy_rst.randomize()); + assert(mi_pmd_rst.randomize()); + assert(tsu_rst.randomize()); + + // Start of the reset sequences + fork + usr_rst.start(p_sequencer.usr_rst); + mi_rst.start(p_sequencer.mi_rst); + mi_phy_rst.start(p_sequencer.mi_phy_rst); + mi_pmd_rst.start(p_sequencer.mi_pmd_rst); + tsu_rst.start(p_sequencer.tsu_rst); + join_none + + // Run sequences + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + fork + int unsigned index = it; + begin + virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH) seq_end; + + port_end[index] = 0; + + while (!seq_sync_port_end.stopped()) begin + assert(port[index].randomize()); + // Run a data sequence + uvm_config_db#(uvm_common::sequence_cfg)::set(p_sequencer.port[index], "", "state", seq_sync_port_end); + port[index].start(p_sequencer.port[index]); + transactions += port[index].rx_transaction_count(); + #0; + end + + port_end[index] = 1; + // Run an end sequence + uvm_config_db#(uvm_common::sequence_cfg_signal)::set(p_sequencer.port[index], "", "state", seq_sync_end); + seq_end = virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN[0], MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::create($sformatf("seq_end_%0d", it), p_sequencer.port[index]); + assert(seq_end.randomize()); + seq_end.start(p_sequencer.port[index], this); + end + join_none + end + + // Stop the sequences + wait (transactions >= ETH_PORTS*30_000); + seq_sync_port_end.send_stop(); + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + wait(port_end[it] == 1); + end + seq_sync_end.send_stop(); + usr_rst.wait_for_sequence_state(UVM_FINISHED); + mi_rst.wait_for_sequence_state(UVM_FINISHED); + mi_phy_rst.wait_for_sequence_state(UVM_FINISHED); + mi_pmd_rst.wait_for_sequence_state(UVM_FINISHED); + tsu_rst.wait_for_sequence_state(UVM_FINISHED); + endtask + +endclass + +////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// END SEQUENCES +////////////////////////////////////////////////////////////////////////////////////////////////////////////// +class virt_sequence_stop #( + int unsigned ETH_PORTS, + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned ITEM_WIDTH, + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + + int unsigned ETH_PORT_CHAN[ETH_PORTS], + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH +) extends uvm_network_mod_env::virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); + `uvm_object_param_utils(uvm_network_mod_cmac_env::virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)) + + protected uvm_logic_vector_array::config_sequence eth_tx_seq_cfg[ETH_PORTS]; + + // Constructor + function new(string name = "virt_sequence_stop"); + super.new(name); + endfunction + + function void packet_size_set(int unsigned min = 64, int unsigned max = 1500); + super.packet_size_set(min, max); + + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + eth_tx_seq_cfg[it] = new(); + eth_tx_seq_cfg[it].array_size_set(min, max); + end + endfunction + + task body(); + // Randomization + assert(usr_rst.randomize()); + assert(mi_rst.randomize()); + assert(mi_phy_rst.randomize()); + assert(mi_pmd_rst.randomize()); + assert(tsu_rst.randomize()); + + // Start of the reset sequences + fork + do begin + usr_rst.start(p_sequencer.usr_rst, this); + end while (!seq_sync_end.stopped()); + do begin + mi_rst.start(p_sequencer.mi_rst, this); + end while (!seq_sync_end.stopped()); + do begin + mi_phy_rst.start(p_sequencer.mi_phy_rst, this); + end while (!seq_sync_end.stopped()); + do begin + mi_pmd_rst.start(p_sequencer.mi_pmd_rst, this); + end while (!seq_sync_end.stopped()); + do begin + tsu_rst.start(p_sequencer.tsu_rst, this); + end while (!seq_sync_end.stopped()); + join_none + + // Run the sequences + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + fork + automatic int unsigned index = it; + begin + assert(port[index].randomize()); + port[index].start(p_sequencer.port[index], this); + end + join_none + end + + while(!seq_sync_end.stopped()) begin + #(300ns); + end + // Stop the sequences + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + port[it].wait_for_sequence_state(UVM_FINISHED); + end + + usr_rst.wait_for_sequence_state(UVM_FINISHED); + mi_rst.wait_for_sequence_state(UVM_FINISHED); + mi_phy_rst.wait_for_sequence_state(UVM_FINISHED); + mi_pmd_rst.wait_for_sequence_state(UVM_FINISHED); + tsu_rst.wait_for_sequence_state(UVM_FINISHED); + endtask + +endclass diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/env/sequencer_port.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/env/sequencer_port.sv new file mode 100644 index 000000000..304bf0901 --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/env/sequencer_port.sv @@ -0,0 +1,32 @@ +// sequencer_port.sv: Virtual sequencer port +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +class sequencer_port #( + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned ITEM_WIDTH, + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + + int unsigned ETH_PORT_CHAN, + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH +) extends uvm_network_mod_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH); + `uvm_component_param_utils(uvm_network_mod_cmac_env::sequencer_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ETH_PORT_CHAN, MI_DATA_WIDTH, MI_ADDR_WIDTH)) + + uvm_logic_vector_array::sequencer #(8) eth_tx_packet; + uvm_logic_vector::sequencer #(1) eth_tx_error; + uvm_lbus::sequencer eth_rx; + + // Constructor + function new(string name = "sequencer_port", uvm_component parent = null); + super.new(name, parent); + endfunction + +endclass diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/env/tx_error_expander.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/env/tx_error_expander.sv new file mode 100644 index 000000000..90962a032 --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/env/tx_error_expander.sv @@ -0,0 +1,29 @@ +// tx_error_expander.sv: Expands error bit data on TX side +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +class tx_error_expander extends uvm_subscriber #(uvm_logic_vector::sequence_item #(1)); + `uvm_component_utils(uvm_network_mod_cmac_env::tx_error_expander) + + localparam int unsigned INPUT_ITEM_WIDTH = 1; + localparam int unsigned OUTPUT_ITEM_WIDTH = 6; + + uvm_analysis_port #(uvm_logic_vector::sequence_item #(OUTPUT_ITEM_WIDTH)) analysis_port; + + // Constructor + function new(string name = "tx_error_expander", uvm_component parent = null); + super.new(name, parent); + analysis_port = new("analysis_port", this); + endfunction + + function void write(uvm_logic_vector::sequence_item #(INPUT_ITEM_WIDTH) t); + uvm_logic_vector::sequence_item #(OUTPUT_ITEM_WIDTH) item = uvm_logic_vector::sequence_item #(OUTPUT_ITEM_WIDTH)::type_id::create("item"); + + item.data = {OUTPUT_ITEM_WIDTH{t.data}}; + + analysis_port.write(item); + endfunction + +endclass diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/property.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/property.sv new file mode 100644 index 000000000..e786ca68d --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/property.sv @@ -0,0 +1,142 @@ +// property.sv: Properties for the Xilinx CMAC interfaces +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +module PROPERTY_CMAC #( + string ETH_CORE_ARCH, + int unsigned ETH_PORTS, + int unsigned ETH_PORT_SPEED[ETH_PORTS-1 : 0], + + int unsigned ETH_PORT_CHAN [ETH_PORTS-1 : 0], + int unsigned EHIP_PORT_TYPE [ETH_PORTS-1 : 0], + int unsigned ETH_PORT_RX_MTU[ETH_PORTS-1 : 0], + int unsigned ETH_PORT_TX_MTU[ETH_PORTS-1 : 0], + + int unsigned LANES, + + int unsigned QSFP_PORTS, + int unsigned QSFP_I2C_PORTS, + int unsigned QSFP_I2C_TRISTATE, + + int unsigned ETH_TX_HDR_WIDTH, + int unsigned ETH_RX_HDR_WIDTH, + + int unsigned REGIONS, + int unsigned REGION_SIZE, + int unsigned BLOCK_SIZE, + int unsigned ITEM_WIDTH, + + int unsigned MI_DATA_WIDTH, + int unsigned MI_ADDR_WIDTH, + + int unsigned MI_DATA_WIDTH_PHY, + int unsigned MI_ADDR_WIDTH_PHY, + + int unsigned LANE_RX_POLARITY, + int unsigned LANE_TX_POLARITY, + + int unsigned RESET_WIDTH, + + string DEVICE, + string BOARD +)( + input wire logic CLK_USR, + input wire logic CLK_ETH[ETH_PORTS], + input wire logic CLK_MI, + input wire logic CLK_MI_PHY, + input wire logic CLK_MI_PMD, + input wire logic CLK_TSU, + + reset_if rst_usr, + reset_if rst_eth[ETH_PORTS], + reset_if rst_mi, + reset_if rst_mi_phy, + reset_if rst_mi_pmd, + reset_if rst_tsu, + + lbus_if eth_tx[ETH_PORTS], + lbus_if eth_rx[ETH_PORTS], + + mfb_if usr_rx [ETH_PORTS], + mfb_if usr_tx_data[ETH_PORTS], + mvb_if usr_tx_hdr [ETH_PORTS], + + mi_if mi, // TODO + mi_if mi_phy, // TODO + mi_if mi_pmd, // TODO + + mvb_if tsu +); + + // Shared property + PROPERTY #( + .ETH_CORE_ARCH (ETH_CORE_ARCH ), + .ETH_PORTS (ETH_PORTS ), + .ETH_PORT_SPEED (ETH_PORT_SPEED ), + .ETH_PORT_CHAN (ETH_PORT_CHAN ), + .EHIP_PORT_TYPE (EHIP_PORT_TYPE ), + .ETH_PORT_RX_MTU (ETH_PORT_RX_MTU ), + .ETH_PORT_TX_MTU (ETH_PORT_TX_MTU ), + .LANES (LANES ), + .QSFP_PORTS (QSFP_PORTS ), + .QSFP_I2C_PORTS (QSFP_I2C_PORTS ), + .QSFP_I2C_TRISTATE(QSFP_I2C_TRISTATE), + .ETH_TX_HDR_WIDTH (ETH_TX_HDR_WIDTH ), + .ETH_RX_HDR_WIDTH (ETH_RX_HDR_WIDTH ), + .REGIONS (REGIONS ), + .REGION_SIZE (REGION_SIZE ), + .BLOCK_SIZE (BLOCK_SIZE ), + .ITEM_WIDTH (ITEM_WIDTH ), + .MI_DATA_WIDTH (MI_DATA_WIDTH ), + .MI_ADDR_WIDTH (MI_ADDR_WIDTH ), + .MI_DATA_WIDTH_PHY(MI_DATA_WIDTH_PHY), + .MI_ADDR_WIDTH_PHY(MI_ADDR_WIDTH_PHY), + .LANE_RX_POLARITY (LANE_RX_POLARITY ), + .LANE_TX_POLARITY (LANE_TX_POLARITY ), + .RESET_WIDTH (RESET_WIDTH ), + .DEVICE (DEVICE ), + .BOARD (BOARD ) + ) + PROPERTY_BASE ( + .CLK_USR (CLK_USR ), + .CLK_ETH (CLK_ETH ), + .CLK_MI (CLK_MI ), + .CLK_MI_PHY (CLK_MI_PHY), + .CLK_MI_PMD (CLK_MI_PMD), + .CLK_TSU (CLK_TSU ), + + .rst_usr (rst_usr ), + .rst_eth (rst_eth ), + .rst_mi (rst_mi ), + .rst_mi_phy (rst_mi_phy), + .rst_mi_pmd (rst_mi_pmd), + .rst_tsu (rst_tsu ), + + .usr_rx (usr_rx ), + .usr_tx_data (usr_tx_data), + .usr_tx_hdr (usr_tx_hdr ), + + .mi (mi ), + .mi_phy (mi_phy), + .mi_pmd (mi_pmd), + + .tsu (tsu) + ); + + // LBUS properties + generate; + for (genvar i = 0; i < ETH_PORTS; i++) begin + lbus_property LBUS_TX_PROPERTY ( + .RESET(rst_eth[i].RESET), + .vif (eth_tx [i] ) + ); + lbus_property LBUS_RX_PROPERTY ( + .RESET(rst_eth[i].RESET), + .vif (eth_rx [i] ) + ); + end + endgenerate + +endmodule diff --git a/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv new file mode 100644 index 000000000..61fc2d973 --- /dev/null +++ b/core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv @@ -0,0 +1,262 @@ +// testbench.sv: Testbench for Xilinx CMAC +// Copyright (C) 2024 CESNET z. s. p. o. +// Author(s): Yaroslav Marushchenko + +// SPDX-License-Identifier: BSD-3-Clause + +import uvm_pkg::*; +`include "uvm_macros.svh" + +import test::*; + +module testbench; + + // --------------------- // + // Test type definitions // + // --------------------- // + + typedef test::base #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH) base; + typedef test::speed #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH) speed; + + // ------ // + // Clocks // + // ------ // + + logic CLK_USR = 0; + logic CLK_ETH[ETH_PORTS] = '{ETH_PORTS{1'b0}}; + logic CLK_MI = 0; + logic CLK_MI_PHY = 0; + logic CLK_MI_PMD = 0; + logic CLK_TSU = 0; + + // ------ // + // Resets // + // ------ // + + reset_if rst_usr (CLK_USR); + reset_if rst_eth[ETH_PORTS](CLK_ETH[0]); + reset_if rst_mi (CLK_MI); + reset_if rst_mi_phy (CLK_MI_PHY); + reset_if rst_mi_pmd (CLK_MI_PMD); + reset_if rst_tsu (CLK_TSU); + + // ---------- // + // Interfaces // + // ---------- // + + lbus_if eth_tx[ETH_PORTS](CLK_ETH); + lbus_if eth_rx[ETH_PORTS](CLK_ETH); + + mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH) usr_rx [ETH_PORTS](CLK_USR); + mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) usr_tx_data[ETH_PORTS](CLK_USR); + mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) usr_tx_hdr [ETH_PORTS](CLK_USR); + + mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH) mi (CLK_MI); + mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH) mi_phy(CLK_MI_PHY); + mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH) mi_pmd(CLK_MI_PMD); + + mvb_if #(1, 64) tsu(CLK_TSU); + + // Fix bind + fix_bind #( + .PORTS (ETH_PORTS), + .CHANNELS (ETH_PORT_CHAN[0]) + ) bind_i(); + + // ------------------------- // + // Clock ticking definitions // + // ------------------------- // + + always #(CLK_USR_PERIOD/2) CLK_USR = ~CLK_USR; + for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin + always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH[eth_it] = ~CLK_ETH[eth_it]; + end + always #(CLK_MI_PERIOD/2) CLK_MI = ~CLK_MI ; + always #(CLK_MI_PHY_PERIOD/2) CLK_MI_PHY = ~CLK_MI_PHY; + always #(CLK_MI_PMD_PERIOD/2) CLK_MI_PMD = ~CLK_MI_PMD; + always #(CLK_TSU_PERIOD/2) CLK_TSU = ~CLK_TSU ; + + initial begin + // --------- // + // Variables // + // --------- // + + automatic uvm_root m_root; + + automatic virtual reset_if vif_rst_eth[ETH_PORTS] = rst_eth; + automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH) vif_usr_rx [ETH_PORTS] = usr_rx; + automatic virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) vif_usr_tx_data[ETH_PORTS] = usr_tx_data; + automatic virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) vif_usr_tx_hdr [ETH_PORTS] = usr_tx_hdr; + automatic virtual lbus_if vif_eth_tx [ETH_PORTS] = eth_tx; + automatic virtual lbus_if vif_eth_rx [ETH_PORTS] = eth_rx; + + // ------------- // + // Configuration // + // ------------- // + + // Setting of interfaces + uvm_config_db#(virtual reset_if)::set(null, "", "vif_rst_usr", rst_usr); + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + uvm_config_db#(virtual reset_if)::set(null, "", $sformatf("vif_rst_eth_%0d", it), vif_rst_eth[it]); + end + uvm_config_db#(virtual reset_if)::set(null, "", "vif_rst_mi", rst_mi); + uvm_config_db#(virtual reset_if)::set(null, "", "vif_rst_mi_phy", rst_mi_phy); + uvm_config_db#(virtual reset_if)::set(null, "", "vif_rst_mi_pmd", rst_mi_pmd); + uvm_config_db#(virtual reset_if)::set(null, "", "vif_rst_tsu", rst_tsu); + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + uvm_config_db#(virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, ETH_TX_HDR_WIDTH))::set(null, "", $sformatf("vif_usr_rx_%0d", it) , vif_usr_rx[it]); + uvm_config_db#(virtual mfb_if #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, 0) )::set(null, "", $sformatf("vif_usr_tx_data_%0d", it), vif_usr_tx_data[it]); + uvm_config_db#(virtual mvb_if #(REGIONS, ETH_RX_HDR_WIDTH) )::set(null, "", $sformatf("vif_usr_tx_hdr_%0d", it) , vif_usr_tx_hdr[it]); + + uvm_config_db#(virtual lbus_if)::set(null, "", $sformatf("vif_eth_tx_%0d", it) , vif_eth_tx[it]); + uvm_config_db#(virtual lbus_if)::set(null, "", $sformatf("vif_eth_rx_%0d", it) , vif_eth_rx[it]); + end + uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi" , mi); + uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi_phy", mi_phy); + uvm_config_db#(virtual mi_if #(MI_DATA_WIDTH, MI_ADDR_WIDTH))::set(null, "", "vif_mi_pmd", mi_pmd); + uvm_config_db#(virtual mvb_if #(1, 64))::set(null, "", "vif_tsu", tsu); + + // Configuration of the database + m_root = uvm_root::get(); + m_root.finish_on_completion = 0; + m_root.set_report_id_action_hier("ILLEGALNAME", UVM_NO_ACTION); + + uvm_config_db#(int) ::set(null, "", "recording_detail", 0); + uvm_config_db#(uvm_bitstream_t)::set(null, "", "recording_detail", 0); + + // Instance override + uvm_network_mod_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_inst_override( + uvm_network_mod_cmac_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type(), + "uvm_test_top.m_env" + ); + + // -------- // + // Test run // + // -------- // + + run_test(); + $stop(2); + end + + // === // + // DUT // + // === // + + DUT #( + .ETH_CORE_ARCH (ETH_CORE_ARCH ), + .ETH_PORTS (ETH_PORTS ), + .ETH_PORT_SPEED (ETH_PORT_SPEED ), + .ETH_PORT_CHAN (ETH_PORT_CHAN ), + .EHIP_PORT_TYPE (EHIP_PORT_TYPE ), + .ETH_PORT_RX_MTU (ETH_PORT_RX_MTU ), + .ETH_PORT_TX_MTU (ETH_PORT_TX_MTU ), + .LANES (LANES ), + .QSFP_PORTS (QSFP_PORTS ), + .QSFP_I2C_PORTS (QSFP_I2C_PORTS ), + .QSFP_I2C_TRISTATE(QSFP_I2C_TRISTATE), + .ETH_TX_HDR_WIDTH (ETH_TX_HDR_WIDTH), + .ETH_RX_HDR_WIDTH (ETH_RX_HDR_WIDTH), + .REGIONS (REGIONS ), + .REGION_SIZE (REGION_SIZE ), + .BLOCK_SIZE (BLOCK_SIZE ), + .ITEM_WIDTH (ITEM_WIDTH ), + .MI_DATA_WIDTH (MI_DATA_WIDTH ), + .MI_ADDR_WIDTH (MI_ADDR_WIDTH ), + .MI_DATA_WIDTH_PHY(MI_DATA_WIDTH_PHY), + .MI_ADDR_WIDTH_PHY(MI_ADDR_WIDTH_PHY), + .LANE_RX_POLARITY (LANE_RX_POLARITY ), + .LANE_TX_POLARITY (LANE_TX_POLARITY ), + .RESET_WIDTH (RESET_WIDTH ), + .DEVICE (DEVICE ), + .BOARD (BOARD ) + ) DUT_U ( + .CLK_ETH (CLK_ETH ), + .CLK_USR (CLK_USR ), + .CLK_MI (CLK_MI ), + .CLK_MI_PHY (CLK_MI_PHY), + .CLK_MI_PMD (CLK_MI_PMD), + .CLK_TSU (CLK_TSU ), + + .rst_usr (rst_usr ), + .rst_eth (rst_eth ), + .rst_mi (rst_mi ), + .rst_mi_phy (rst_mi_phy), + .rst_mi_pmd (rst_mi_pmd), + .rst_tsu (rst_tsu ), + + .eth_tx (eth_tx), + .eth_rx (eth_rx), + + .usr_rx (usr_rx ), + .usr_tx_data (usr_tx_data), + .usr_tx_hdr (usr_tx_hdr ), + + .mi (mi ), + .mi_phy (mi_phy), + .mi_pmd (mi_pmd), + + .tsu (tsu) + ); + + // ========== // + // Properties // + // ========== // + + PROPERTY_CMAC #( + .ETH_CORE_ARCH (ETH_CORE_ARCH ), + .ETH_PORTS (ETH_PORTS ), + .ETH_PORT_SPEED (ETH_PORT_SPEED ), + .ETH_PORT_CHAN (ETH_PORT_CHAN ), + .EHIP_PORT_TYPE (EHIP_PORT_TYPE ), + .ETH_PORT_RX_MTU (ETH_PORT_RX_MTU ), + .ETH_PORT_TX_MTU (ETH_PORT_TX_MTU ), + .LANES (LANES ), + .QSFP_PORTS (QSFP_PORTS ), + .QSFP_I2C_PORTS (QSFP_I2C_PORTS ), + .QSFP_I2C_TRISTATE(QSFP_I2C_TRISTATE), + .ETH_TX_HDR_WIDTH (ETH_TX_HDR_WIDTH ), + .ETH_RX_HDR_WIDTH (ETH_RX_HDR_WIDTH ), + .REGIONS (REGIONS ), + .REGION_SIZE (REGION_SIZE ), + .BLOCK_SIZE (BLOCK_SIZE ), + .ITEM_WIDTH (ITEM_WIDTH ), + .MI_DATA_WIDTH (MI_DATA_WIDTH ), + .MI_ADDR_WIDTH (MI_ADDR_WIDTH ), + .MI_DATA_WIDTH_PHY(MI_DATA_WIDTH_PHY), + .MI_ADDR_WIDTH_PHY(MI_ADDR_WIDTH_PHY), + .LANE_RX_POLARITY (LANE_RX_POLARITY ), + .LANE_TX_POLARITY (LANE_TX_POLARITY ), + .RESET_WIDTH (RESET_WIDTH ), + .DEVICE (DEVICE ), + .BOARD (BOARD ) + ) + PROPERTY_U ( + .CLK_USR (CLK_USR ), + .CLK_ETH (CLK_ETH ), + .CLK_MI (CLK_MI ), + .CLK_MI_PHY (CLK_MI_PHY), + .CLK_MI_PMD (CLK_MI_PMD), + .CLK_TSU (CLK_TSU ), + + .rst_usr (rst_usr ), + .rst_eth (rst_eth ), + .rst_mi (rst_mi ), + .rst_mi_phy (rst_mi_phy), + .rst_mi_pmd (rst_mi_pmd), + .rst_tsu (rst_tsu ), + + .eth_tx (eth_tx ), + .eth_rx (eth_rx ), + + .usr_rx (usr_rx ), + .usr_tx_data (usr_tx_data), + .usr_tx_hdr (usr_tx_hdr ), + + .mi (mi ), + .mi_phy (mi_phy), + .mi_pmd (mi_pmd), + + .tsu (tsu) + ); + +endmodule diff --git a/core/comp/eth/network_mod/uvm/tbench/e-tile/env/env.sv b/core/comp/eth/network_mod/uvm/tbench/e-tile/env/env.sv index cc2065995..4402cd0c9 100644 --- a/core/comp/eth/network_mod/uvm/tbench/e-tile/env/env.sv +++ b/core/comp/eth/network_mod/uvm/tbench/e-tile/env/env.sv @@ -47,6 +47,17 @@ class env #( super.new(name, parent); endfunction + virtual function void eth_full_speed_set(); + for (int unsigned it = 0; it < ETH_PORTS; it++) begin + uvm_logic_vector_array_avst::sequence_lib_rx#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 6, 0) + ::type_id::set_inst_override(uvm_logic_vector_array_avst::sequence_lib_rx_speed#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 6, 0) + ::get_type(),{this.get_full_name(), $sformatf(".m_eth_rx_%0d.*", it)}); + + uvm_avst::sequence_lib_tx#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 1)::type_id::set_inst_override(uvm_avst::sequence_lib_tx_speed#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 1) + ::get_type(),{this.get_full_name(), $sformatf(".m_eth_tx_%0d.*", it)}); + end + endfunction + function void build_phase(uvm_phase phase); // -------------------------------------- // // Overriding the base components/objects // diff --git a/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv b/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv index 949eb6385..c3d38818c 100644 --- a/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv +++ b/core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv @@ -73,10 +73,10 @@ class virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIO seq_sync_end.clear(); fork - while (!seq_sync_end.stopped()) begin + do begin assert(eth_rst.randomize()); eth_rst.start(p_sequencer.eth_rst); - end + end while (!seq_sync_end.stopped()); join_none #(400ns); @@ -94,35 +94,37 @@ class virt_sequence_port #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, REGIO end fork - while (!seq_sync_usr_rx.cfg[0].stopped()) begin + do begin assert(usr_rx_data.randomize()); usr_rx_data.start(p_sequencer.usr_rx_data); - end - while (!seq_sync_usr_rx.cfg[1].stopped()) begin + end while (!seq_sync_usr_rx.cfg[0].stopped()); + do begin assert(usr_rx_meta.randomize()); usr_rx_meta.start(p_sequencer.usr_rx_meta); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_usr_rx.cfg[1].stopped()); + + do begin assert(usr_tx_data.randomize()); usr_tx_data.start(p_sequencer.usr_tx_data); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin assert(usr_tx_hdr.randomize()); usr_tx_hdr.start(p_sequencer.usr_tx_hdr); - end + end while (!seq_sync_end.stopped()); - while (!seq_sync_eth_rx.cfg[0].stopped()) begin + do begin assert(eth_rx_data.randomize()); eth_rx_data.start(p_sequencer.eth_rx_data); - end - while (!seq_sync_eth_rx.cfg[1].stopped()) begin + end while (!seq_sync_eth_rx.cfg[0].stopped()); + do begin assert(eth_rx_meta.randomize()); eth_rx_meta.start(p_sequencer.eth_rx_meta); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_eth_rx.cfg[1].stopped()); + + do begin assert(eth_tx.randomize()); eth_tx.start(p_sequencer.eth_tx); - end + end while (!seq_sync_end.stopped()); join_none while ((state == null || !state.stopped()) && @@ -274,24 +276,24 @@ class virt_sequence_port_stop #(ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_WIDTH, end fork - while (!seq_sync_end.stopped()) begin + do begin assert(eth_rst.randomize()); eth_rst.start(p_sequencer.eth_rst); - end + end while (!seq_sync_end.stopped()); - while (!seq_sync_end.stopped()) begin + do begin assert(usr_tx_data.randomize()); usr_tx_data.start(p_sequencer.usr_tx_data); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin assert(usr_tx_hdr.randomize()); usr_tx_hdr.start(p_sequencer.usr_tx_hdr); - end + end while (!seq_sync_end.stopped()); - while (!seq_sync_end.stopped()) begin + do begin assert(eth_tx.randomize()); eth_tx.start(p_sequencer.eth_tx); - end + end while (!seq_sync_end.stopped()); join_none while(!state.stopped()) begin @@ -431,21 +433,21 @@ class virt_sequence_stop #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM_W assert(tsu_rst.randomize()); fork - while (!seq_sync_end.stopped()) begin + do begin usr_rst.start(p_sequencer.usr_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin mi_rst.start(p_sequencer.mi_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin mi_phy_rst.start(p_sequencer.mi_phy_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin mi_pmd_rst.start(p_sequencer.mi_pmd_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin tsu_rst.start(p_sequencer.tsu_rst, this); - end + end while (!seq_sync_end.stopped()); join_none for (int unsigned it = 0; it < ETH_PORTS; it++) begin diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv index 355753d81..c221e89b1 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/dut.sv @@ -121,42 +121,11 @@ module DUT #( .tsu (tsu) ); - // localparam int unsigned DATA_WIDTH = 64; - // localparam int unsigned INFRAME_WIDTH = 1; - // localparam int unsigned EOP_EMPTY_WIDTH = 3; - // localparam int unsigned FCS_ERROR_WIDTH = 1; - // localparam int unsigned ERROR_WIDTH = 2; - // localparam int unsigned STATUS_DATA_WIDTH = 3; - // localparam int unsigned SEGMENTS = ((ETH_PORT_SPEED[0] == 400) ? 16 : - // (ETH_PORT_SPEED[0] == 200) ? 8 : - // (ETH_PORT_SPEED[0] == 100) ? 4 : - // (ETH_PORT_SPEED[0] == 50 ) ? 2 : - // (ETH_PORT_SPEED[0] == 40 ) ? 2 : - // (ETH_PORT_SPEED[0] == 25 ) ? 1 : - // (ETH_PORT_SPEED[0] == 10 ) ? 1 : - // 0 ); - generate; for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin localparam int unsigned ETH_PORT_CHAN_LOCAL = ETH_PORT_CHAN[eth_it]; initial assert(ETH_PORT_CHAN_LOCAL == 1); // TODO - // RX serialized signals - // wire logic [ETH_PORT_CHAN_LOCAL*SEGMENTS*DATA_WIDTH -1 : 0] rx_data; - // wire logic [ETH_PORT_CHAN_LOCAL*SEGMENTS*INFRAME_WIDTH -1 : 0] rx_inframe; - // wire logic [ETH_PORT_CHAN_LOCAL*SEGMENTS*EOP_EMPTY_WIDTH -1 : 0] rx_eop_empty; - // wire logic [ETH_PORT_CHAN_LOCAL*SEGMENTS*FCS_ERROR_WIDTH -1 : 0] rx_fcs_error; - // wire logic [ETH_PORT_CHAN_LOCAL*SEGMENTS*ERROR_WIDTH -1 : 0] rx_error; - // wire logic [ETH_PORT_CHAN_LOCAL*SEGMENTS*STATUS_DATA_WIDTH-1 : 0] rx_status_data; - // - // // RX connections - // assign rx_data = eth_rx[eth_it].DATA; - // assign rx_inframe = eth_rx[eth_it].INFRAME; - // assign rx_eop_empty = eth_rx[eth_it].EOP_EMPTY; - // assign rx_fcs_error = eth_rx[eth_it].FCS_ERROR; - // assign rx_error = eth_rx[eth_it].ERROR; - // assign rx_status_data = eth_rx[eth_it].STATUS_DATA; - // TX connections assign eth_tx[eth_it].DATA = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_data}}; assign eth_tx[eth_it].INFRAME = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.ftile_tx_adapt_inframe}}; diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv index 3425096be..023de2b44 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/env.sv @@ -48,6 +48,10 @@ class env #( super.new(name, parent); endfunction + virtual function void eth_full_speed_set(); + `uvm_warning(this.get_full_name(), "\n\tSpeed test for Intel F-Tile IP Core connection is not supported.") + endfunction + function void build_phase(uvm_phase phase); // -------------------------------------- // // Overriding the base components/objects // diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv index e3210d39f..a5344d539 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv @@ -84,10 +84,10 @@ class virt_sequence_port #( seq_sync_end.clear(); fork - while (!seq_sync_end.stopped()) begin + do begin assert(eth_rst.randomize()); eth_rst.start(p_sequencer.eth_rst); - end + end while (!seq_sync_end.stopped()); join_none #(400ns); @@ -105,35 +105,37 @@ class virt_sequence_port #( end fork - while (!seq_sync_usr_rx.cfg[0].stopped()) begin + do begin assert(usr_rx_data.randomize()); usr_rx_data.start(p_sequencer.usr_rx_data); - end - while (!seq_sync_usr_rx.cfg[1].stopped()) begin + end while (!seq_sync_usr_rx.cfg[0].stopped()); + do begin assert(usr_rx_meta.randomize()); usr_rx_meta.start(p_sequencer.usr_rx_meta); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_usr_rx.cfg[1].stopped()); + + do begin assert(usr_tx_data.randomize()); usr_tx_data.start(p_sequencer.usr_tx_data); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin assert(usr_tx_hdr.randomize()); usr_tx_hdr.start(p_sequencer.usr_tx_hdr); - end + end while (!seq_sync_end.stopped()); - while (!seq_sync_eth_rx.cfg[0].stopped()) begin + do begin assert(eth_rx_data.randomize()); eth_rx_data.start(p_sequencer.eth_rx_data); - end - while (!seq_sync_eth_rx.cfg[1].stopped()) begin + end while (!seq_sync_eth_rx.cfg[0].stopped()); + do begin assert(eth_rx_meta.randomize()); eth_rx_meta.start(p_sequencer.eth_rx_meta); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_eth_rx.cfg[1].stopped()); + + do begin assert(eth_tx.randomize()); eth_tx.start(p_sequencer.eth_tx); - end + end while (!seq_sync_end.stopped()); join_none while ((state == null || !state.stopped()) && @@ -295,24 +297,24 @@ class virt_sequence_port_stop #( end fork - while (!seq_sync_end.stopped()) begin + do begin assert(eth_rst.randomize()); eth_rst.start(p_sequencer.eth_rst); - end + end while (!seq_sync_end.stopped()); - while (!seq_sync_end.stopped()) begin + do begin assert(usr_tx_data.randomize()); usr_tx_data.start(p_sequencer.usr_tx_data); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin assert(usr_tx_hdr.randomize()); usr_tx_hdr.start(p_sequencer.usr_tx_hdr); - end + end while (!seq_sync_end.stopped()); - while (!seq_sync_end.stopped()) begin + do begin assert(eth_tx.randomize()); eth_tx.start(p_sequencer.eth_tx); - end + end while (!seq_sync_end.stopped()); join_none while(!state.stopped()) begin @@ -480,21 +482,21 @@ class virt_sequence_stop #( assert(tsu_rst.randomize()); fork - while (!seq_sync_end.stopped()) begin + do begin usr_rst.start(p_sequencer.usr_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin mi_rst.start(p_sequencer.mi_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin mi_phy_rst.start(p_sequencer.mi_phy_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin mi_pmd_rst.start(p_sequencer.mi_pmd_rst, this); - end - while (!seq_sync_end.stopped()) begin + end while (!seq_sync_end.stopped()); + do begin tsu_rst.start(p_sequencer.tsu_rst, this); - end + end while (!seq_sync_end.stopped()); join_none for (int unsigned it = 0; it < ETH_PORTS; it++) begin diff --git a/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv b/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv index 00d3bac30..3a67c73ea 100644 --- a/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv +++ b/core/comp/eth/network_mod/uvm/tbench/f-tile/testbench.sv @@ -117,7 +117,6 @@ module testbench; uvm_config_db#(int) ::set(null, "", "recording_detail", 0); uvm_config_db#(uvm_bitstream_t)::set(null, "", "recording_detail", 0); - `uvm_info("", $sformatf("\n\nDEBUG\n%0d\n\n", ETH_PORT_CHAN[0]), UVM_NONE) uvm_network_mod_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::set_inst_override( uvm_network_mod_f_tile_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH)::get_type(), "uvm_test_top.m_env" diff --git a/core/comp/eth/network_mod/uvm/tbench/fix_bind.sv b/core/comp/eth/network_mod/uvm/tbench/fix_bind.sv index 05c2f7535..9e4250e60 100644 --- a/core/comp/eth/network_mod/uvm/tbench/fix_bind.sv +++ b/core/comp/eth/network_mod/uvm/tbench/fix_bind.sv @@ -5,13 +5,16 @@ // SPDX-License-Identifier: BSD-3-Clause +import uvm_pkg::*; +`include "uvm_macros.svh" + // It only supports single channel combinations with 1, 2 or 4 ports module fix_bind #(int unsigned PORTS, int unsigned CHANNELS); initial begin assert(CHANNELS == 1) else begin - $error("%m UNSUPORTED COMBINATION: CHANNELS(%0d)!!!\n", CHANNELS); + `uvm_fatal($sformatf("%m"), $sformatf("AN UNSUPPORTED COMBINATION: CHANNELS(%0d)!!!", CHANNELS)); end end @@ -36,7 +39,7 @@ module fix_bind #(int unsigned PORTS, int unsigned CHANNELS); probe_inf #(2*REGIONS) probe_drop(s_rx_src_rdy_orig_reg, {s_rx_eof_orig_reg, s_rx_force_drop_reg}, RX_CLK); end else begin - $error("%m UNSUPORTED COMBINATION: PORTS(%0d)!!!\n", PORTS); + initial `uvm_fatal($sformatf("%m"), $sformatf("AN UNSUPPORTED COMBINATION: PORTS(%0d)!!!\n", PORTS)); end endmodule diff --git a/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv b/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv index d7ecf55ba..6f035a24c 100644 --- a/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv +++ b/core/comp/eth/network_mod/uvm/tbench/tests/speed.sv @@ -57,22 +57,9 @@ class speed #( end // ETH - if (ETH_CORE_ARCH == "E_TILE") begin - for (int unsigned it = 0; it < ETH_PORTS; it++) begin - uvm_logic_vector_array_avst::sequence_lib_rx#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 6, 0) - ::type_id::set_inst_override(uvm_logic_vector_array_avst::sequence_lib_rx_speed#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 6, 0) - ::get_type(),{this.get_full_name(), $sformatf(".m_env.m_eth_rx_%0d.*", it)}); - - uvm_avst::sequence_lib_tx#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 1)::type_id::set_inst_override(uvm_avst::sequence_lib_tx_speed#(ETH_PORT_CHAN[0], 1, REGION_SIZE * BLOCK_SIZE, ITEM_WIDTH, 1) - ::get_type(),{this.get_full_name(), $sformatf(".m_env.m_eth_tx_%0d.*", it)}); - end - end - else if (ETH_CORE_ARCH == "F_TILE") begin - `uvm_warning(this.get_full_name(), "\n\tSpeed test for Intel F-Tile IP Core connection is not supported.") - end - m_env = uvm_network_mod_env::env #(ETH_CORE_ARCH, ETH_PORTS, ETH_PORT_SPEED, ETH_PORT_CHAN, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH)::type_id::create("m_env", this); + m_env.eth_full_speed_set(); endfunction // ------------------------------------------------------------------------ diff --git a/core/comp/eth/network_mod/uvm/ver_settings.py b/core/comp/eth/network_mod/uvm/ver_settings.py index baf6bae16..f904381d3 100644 --- a/core/comp/eth/network_mod/uvm/ver_settings.py +++ b/core/comp/eth/network_mod/uvm/ver_settings.py @@ -98,7 +98,10 @@ "BLOCK_SIZE" : "8", "ITEM_WIDTH" : "8", "DEVICE" : "\\\"ULTRASCALE\\\"", - "__core_params__": {"NETWORK_ARCH": "CMAC"}, + "__core_params__": { + "UVM_TEST": "test::base", + "NETWORK_ARCH": "CMAC" + }, }, @@ -128,6 +131,13 @@ }, }, + "cmac_test_speed" : { + "__core_params__": { + "UVM_TEST": "test::speed", + "NETWORK_ARCH": "CMAC" + }, + }, + "large_packets" : { "PACKET_SIZE_MIN" : "12000", "PACKET_SIZE_MAX" : "16384", @@ -168,16 +178,15 @@ "1p_ftile_1x100g4_normal_speed" : ("ftile_1x100g4", "ports_1", "small_packets", "ftile_test_speed",), "1p_ftile_1x100g4_small_speed" : ("ftile_1x100g4", "ports_1", "large_packets", "ftile_test_speed",), - # TODO UNSUPPORTED: CMAC IS NOT IMPLEMENTED # 2x CMAC 100G - #"2p_cmac_1x100g4_normal" : ("cmac_1x100g4", "ports_2",), - #"2p_cmac_1x100g4_small" : ("cmac_1x100g4", "ports_2", "small_packets",), - #"2p_cmac_1x100g4_large" : ("cmac_1x100g4", "ports_2", "large_packets",), - #"2p_cmac_1x100g4_normal_speed" : ("cmac_1x100g4", "ports_2", "small_packets", "test_speed",), - #"2p_cmac_1x100g4_small_speed" : ("cmac_1x100g4", "ports_2", "large_packets", "test_speed",), + "2p_cmac_1x100g4_normal" : ("cmac_1x100g4", "ports_2",), + "2p_cmac_1x100g4_small" : ("cmac_1x100g4", "ports_2", "small_packets",), + "2p_cmac_1x100g4_large" : ("cmac_1x100g4", "ports_2", "large_packets",), + "2p_cmac_1x100g4_normal_speed" : ("cmac_1x100g4", "ports_2", "small_packets", "cmac_test_speed",), + "2p_cmac_1x100g4_small_speed" : ("cmac_1x100g4", "ports_2", "large_packets", "cmac_test_speed",), # 4x CMAC 100G - #"4p_cmac_1x100g4_normal" : ("cmac_1x100g4", "ports_4",), - #"4p_cmac_1x100g4_small" : ("cmac_1x100g4", "ports_4", "small_packets",), + "4p_cmac_1x100g4_normal" : ("cmac_1x100g4", "ports_4",), + "4p_cmac_1x100g4_small" : ("cmac_1x100g4", "ports_4", "small_packets",), }, } diff --git a/tests/jenkins/ver_core_comp.jenkins b/tests/jenkins/ver_core_comp.jenkins index b252d3bff..4f9424e80 100644 --- a/tests/jenkins/ver_core_comp.jenkins +++ b/tests/jenkins/ver_core_comp.jenkins @@ -31,7 +31,7 @@ def COMPONENTS_MULTIVER = [\ ['DMA_TRANS_ACCU' ,'extra/dma-medusa/rx/comp/dma_endpoint/comp/trans_accu/ver' ,'top_level.fdo' ,'tbench/test_pkg.sv' ,'ver_settings.py'],\ ['PCIE_ADAPTERS' ,'core/comp/pcie/pcie_mod/comp/pcie_adapter/uvm' ,'top_level.fdo' ,'tbench/tests/pkg.sv' ,'ver_settings.py'],\ ['PCIE_TOP' ,'core/comp/pcie/pcie_mod/uvm' ,'top_level.fdo' ,'tbench/tests/pkg.sv' ,'ver_settings.py'],\ - ['NETWORK_MOD' ,'core/comp/eth/network_mod/uvm' ,'top_level.fdo' ,'tbench/pkg.sv' ,'ver_settings.py'],\ + ['NETWORK_MOD' ,'core/comp/eth/network_mod/uvm' ,'top_level.fdo' ,'tbench/tests/pkg.sv' ,'ver_settings.py'],\ ] /////////////////////////////////////////////////////////////////////////////