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Commit 9e3950d

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author
Stepan Friedl
committed
Merge branch 'xkosar02-fix-ftile-clocks' into 'devel'
fix(network-mod): fix F-TILE clock connections See merge request ndk/ndk-fpga!363
2 parents b8dcd37 + e5cc387 commit 9e3950d

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11 files changed

+100
-80
lines changed

11 files changed

+100
-80
lines changed

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ entity FTILE_1X400G8 is
6666
-- Netvork_MOD_CONE_ENT interface
6767
-- ===================================================================
6868
-- different for each ftile (vector)
69+
CLK_ETH_IN : in std_logic;
6970
CLK_ETH_OUT : out std_logic;
7071
RESET_ETH : in std_logic;
7172
-- ===================================================================
@@ -443,9 +444,9 @@ begin
443444
reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0'));
444445

445446
-- monitoring RX link state
446-
process (ftile_clk_out)
447+
process (CLK_ETH_IN)
447448
begin
448-
if rising_edge(ftile_clk_out) then
449+
if rising_edge(CLK_ETH_IN) then
449450
if ((ftile_rx_pcs_ready = '1') or (rx_link_rst = '1')) then
450451
-- link is up, clear the counter
451452
rx_link_cnt <= (others => '0');
@@ -540,8 +541,8 @@ begin
540541
-- can't have more than 8 400g lines devided into 1 channel
541542
ftile_eth_ip_i : component ftile_eth_1x400g
542543
port map (
543-
i_clk_tx => ftile_clk_out,
544-
i_clk_rx => ftile_clk_out,
544+
i_clk_tx => CLK_ETH_IN,
545+
i_clk_rx => CLK_ETH_IN,
545546
o_clk_pll => ftile_clk_out,
546547
i_reconfig_clk => MI_CLK_PHY,
547548
i_reconfig_reset => MI_RESET_PHY,
@@ -685,9 +686,9 @@ begin
685686
RX_MACSI_MAC_ERROR <= ftile_rx_mac_error;
686687
RX_MACSI_MAC_STATUS <= ftile_rx_mac_status;
687688

688-
process (ftile_clk_out)
689+
process (CLK_ETH_IN)
689690
begin
690-
if rising_edge(ftile_clk_out) then
691+
if rising_edge(CLK_ETH_IN) then
691692
if (MI_RESET_PHY = '1') then
692693
RX_LINK_UP <= '0';
693694
TX_LINK_UP <= '0';
@@ -708,7 +709,7 @@ begin
708709
ADATAIN(0) => mgmt_mac_loop,
709710
ASEND => '1',
710711
AREADY => open,
711-
BCLK => ftile_clk_out,
712+
BCLK => CLK_ETH_IN,
712713
BRST => '0',
713714
BDATAOUT(0) => sync_repeater_ctrl,
714715
BLOAD => '1',
@@ -721,7 +722,7 @@ begin
721722
)
722723
port map (
723724
RST => RESET_ETH,
724-
CLK => ftile_clk_out,
725+
CLK => CLK_ETH_IN,
725726

726727
IN_MAC_DATA => ftile_rx_mac_data,
727728
IN_MAC_INFRAME => ftile_rx_mac_inframe,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ entity FTILE_2X100G4 is
6666
-- Netvork_MOD_CONE_ENT interface
6767
-- ===================================================================
6868
-- different for each ftile (vector)
69+
CLK_ETH_IN : in std_logic;
6970
CLK_ETH_OUT : out std_logic;
7071
RESET_ETH : in std_logic;
7172
-- ===================================================================
@@ -414,9 +415,9 @@ begin
414415
reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0'));
415416

416417
-- monitoring RX link state
417-
process (ftile_clk_out)
418+
process (CLK_ETH_IN)
418419
begin
419-
if rising_edge(ftile_clk_out) then
420+
if rising_edge(CLK_ETH_IN) then
420421
if ((ftile_rx_pcs_ready = '1') or (rx_link_rst = '1')) then
421422
-- link is up, clear the counter
422423
rx_link_cnt <= (others => '0');
@@ -512,8 +513,8 @@ begin
512513
-- can't have more than 8 100g lines devided into 2 channels
513514
ftile_eth_ip_i : component ftile_eth_2x100g
514515
port map (
515-
i_clk_tx => ftile_clk_out,
516-
i_clk_rx => ftile_clk_out,
516+
i_clk_tx => CLK_ETH_IN,
517+
i_clk_rx => CLK_ETH_IN,
517518
o_clk_pll => ftile_clk_out,
518519
o_clk_tx_div => open,
519520
o_clk_rec_div64 => open,
@@ -619,9 +620,9 @@ begin
619620
RX_MACSI_MAC_ERROR <= ftile_rx_mac_error;
620621
RX_MACSI_MAC_STATUS <= ftile_rx_mac_status;
621622

622-
process (ftile_clk_out)
623+
process (CLK_ETH_IN)
623624
begin
624-
if rising_edge(ftile_clk_out) then
625+
if rising_edge(CLK_ETH_IN) then
625626
if (MI_RESET_PHY = '1') then
626627
RX_LINK_UP <= '0';
627628
TX_LINK_UP <= '0';
@@ -642,7 +643,7 @@ begin
642643
ADATAIN(0) => mgmt_mac_loop,
643644
ASEND => '1',
644645
AREADY => open,
645-
BCLK => ftile_clk_out,
646+
BCLK => CLK_ETH_IN,
646647
BRST => '0',
647648
BDATAOUT(0) => sync_repeater_ctrl,
648649
BLOAD => '1',
@@ -655,7 +656,7 @@ begin
655656
)
656657
port map (
657658
RST => RESET_ETH,
658-
CLK => ftile_clk_out,
659+
CLK => CLK_ETH_IN,
659660

660661
IN_MAC_DATA => ftile_rx_mac_data,
661662
IN_MAC_INFRAME => ftile_rx_mac_inframe,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ entity FTILE_2X200G4 is
6666
-- Netvork_MOD_CONE_ENT interface
6767
-- ===================================================================
6868
-- different for each ftile (vector)
69+
CLK_ETH_IN : in std_logic;
6970
CLK_ETH_OUT : out std_logic;
7071
RESET_ETH : in std_logic;
7172
-- ===================================================================
@@ -411,9 +412,9 @@ begin
411412
reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0'));
412413

413414
-- monitoring RX link state
414-
process (ftile_clk_out)
415+
process (CLK_ETH_IN)
415416
begin
416-
if rising_edge(ftile_clk_out) then
417+
if rising_edge(CLK_ETH_IN) then
417418
if ((ftile_rx_pcs_ready = '1') or (rx_link_rst = '1')) then
418419
-- link is up, clear the counter
419420
rx_link_cnt <= (others => '0');
@@ -508,8 +509,8 @@ begin
508509
-- can't have more than 8 200g lines devided into 2 channels
509510
ftile_eth_ip_i : component ftile_eth_2x200g
510511
port map (
511-
i_clk_tx => ftile_clk_out,
512-
i_clk_rx => ftile_clk_out,
512+
i_clk_tx => CLK_ETH_IN,
513+
i_clk_rx => CLK_ETH_IN,
513514
o_clk_pll => ftile_clk_out,
514515
o_clk_tx_div => open,
515516
o_clk_rec_div64 => open,
@@ -615,9 +616,9 @@ begin
615616
RX_MACSI_MAC_ERROR <= ftile_rx_mac_error;
616617
RX_MACSI_MAC_STATUS <= ftile_rx_mac_status;
617618

618-
process (ftile_clk_out)
619+
process (CLK_ETH_IN)
619620
begin
620-
if rising_edge(ftile_clk_out) then
621+
if rising_edge(CLK_ETH_IN) then
621622
if (MI_RESET_PHY = '1') then
622623
RX_LINK_UP <= '0';
623624
TX_LINK_UP <= '0';
@@ -638,7 +639,7 @@ begin
638639
ADATAIN(0) => mgmt_mac_loop,
639640
ASEND => '1',
640641
AREADY => open,
641-
BCLK => ftile_clk_out,
642+
BCLK => CLK_ETH_IN,
642643
BRST => '0',
643644
BDATAOUT(0) => sync_repeater_ctrl,
644645
BLOAD => '1',
@@ -651,7 +652,7 @@ begin
651652
)
652653
port map (
653654
RST => RESET_ETH,
654-
CLK => ftile_clk_out,
655+
CLK => CLK_ETH_IN,
655656

656657
IN_MAC_DATA => ftile_rx_mac_data,
657658
IN_MAC_INFRAME => ftile_rx_mac_inframe,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ entity FTILE_2X40G4 is
6666
-- Netvork_MOD_CONE_ENT interface
6767
-- ===================================================================
6868
-- different for each ftile (vector)
69+
CLK_ETH_IN : in std_logic;
6970
CLK_ETH_OUT : out std_logic;
7071
RESET_ETH : in std_logic;
7172
-- ===================================================================
@@ -411,9 +412,9 @@ begin
411412
reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0'));
412413

413414
-- monitoring RX link state
414-
process (ftile_clk_out)
415+
process (CLK_ETH_IN)
415416
begin
416-
if rising_edge(ftile_clk_out) then
417+
if rising_edge(CLK_ETH_IN) then
417418
if ((ftile_rx_pcs_ready = '1') or (rx_link_rst = '1')) then
418419
-- link is up, clear the counter
419420
rx_link_cnt <= (others => '0');
@@ -509,8 +510,8 @@ begin
509510
-- can't have more than 2 40g lines devided into 2 channels
510511
ftile_eth_ip_i : component ftile_eth_2x40g
511512
port map (
512-
i_clk_tx => ftile_clk_out,
513-
i_clk_rx => ftile_clk_out,
513+
i_clk_tx => CLK_ETH_IN,
514+
i_clk_rx => CLK_ETH_IN,
514515
o_clk_pll => ftile_clk_out,
515516
o_clk_tx_div => open,
516517
o_clk_rec_div64 => open,
@@ -616,9 +617,9 @@ begin
616617
RX_MACSI_MAC_ERROR <= ftile_rx_mac_error;
617618
RX_MACSI_MAC_STATUS <= ftile_rx_mac_status;
618619

619-
process (ftile_clk_out)
620+
process (CLK_ETH_IN)
620621
begin
621-
if rising_edge(ftile_clk_out) then
622+
if rising_edge(CLK_ETH_IN) then
622623
if (MI_RESET_PHY = '1') then
623624
RX_LINK_UP <= '0';
624625
TX_LINK_UP <= '0';
@@ -639,7 +640,7 @@ begin
639640
ADATAIN(0) => mgmt_mac_loop,
640641
ASEND => '1',
641642
AREADY => open,
642-
BCLK => ftile_clk_out,
643+
BCLK => CLK_ETH_IN,
643644
BRST => '0',
644645
BDATAOUT(0) => sync_repeater_ctrl,
645646
BLOAD => '1',
@@ -652,7 +653,7 @@ begin
652653
)
653654
port map (
654655
RST => RESET_ETH,
655-
CLK => ftile_clk_out,
656+
CLK => CLK_ETH_IN,
656657

657658
IN_MAC_DATA => ftile_rx_mac_data,
658659
IN_MAC_INFRAME => ftile_rx_mac_inframe,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ entity FTILE_4X100G2 is
6666
-- Netvork_MOD_CONE_ENT interface
6767
-- ===================================================================
6868
-- different for each ftile (vector)
69+
CLK_ETH_IN : in std_logic;
6970
CLK_ETH_OUT : out std_logic;
7071
RESET_ETH : in std_logic;
7172
-- ===================================================================
@@ -395,9 +396,9 @@ begin
395396
reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0'));
396397

397398
-- monitoring RX link state
398-
process (ftile_clk_out)
399+
process (CLK_ETH_IN)
399400
begin
400-
if rising_edge(ftile_clk_out) then
401+
if rising_edge(CLK_ETH_IN) then
401402
if ((ftile_rx_pcs_ready = '1') or (rx_link_rst = '1')) then
402403
-- link is up, clear the counter
403404
rx_link_cnt <= (others => '0');
@@ -492,8 +493,8 @@ begin
492493
-- can't have more than 8 100g lines devided into 4 channels
493494
ftile_eth_ip_i : component ftile_eth_4x100g
494495
port map (
495-
i_clk_tx => ftile_clk_out,
496-
i_clk_rx => ftile_clk_out,
496+
i_clk_tx => CLK_ETH_IN,
497+
i_clk_rx => CLK_ETH_IN,
497498
o_clk_pll => ftile_clk_out,
498499
o_clk_tx_div => open,
499500
o_clk_rec_div64 => open,
@@ -581,9 +582,9 @@ begin
581582
RX_MACSI_MAC_ERROR <= ftile_rx_mac_error;
582583
RX_MACSI_MAC_STATUS <= ftile_rx_mac_status;
583584

584-
process (ftile_clk_out)
585+
process (CLK_ETH_IN)
585586
begin
586-
if rising_edge(ftile_clk_out) then
587+
if rising_edge(CLK_ETH_IN) then
587588
if (MI_RESET_PHY = '1') then
588589
RX_LINK_UP <= '0';
589590
TX_LINK_UP <= '0';
@@ -604,7 +605,7 @@ begin
604605
ADATAIN(0) => mgmt_mac_loop,
605606
ASEND => '1',
606607
AREADY => open,
607-
BCLK => ftile_clk_out,
608+
BCLK => CLK_ETH_IN,
608609
BRST => '0',
609610
BDATAOUT(0) => sync_repeater_ctrl,
610611
BLOAD => '1',
@@ -617,7 +618,7 @@ begin
617618
)
618619
port map (
619620
RST => RESET_ETH,
620-
CLK => ftile_clk_out,
621+
CLK => CLK_ETH_IN,
621622

622623
IN_MAC_DATA => ftile_rx_mac_data,
623624
IN_MAC_INFRAME => ftile_rx_mac_inframe,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ entity FTILE_8X10G1 is
6666
-- Netvork_MOD_CONE_ENT interface
6767
-- ===================================================================
6868
-- different for each ftile (vector)
69+
CLK_ETH_IN : in std_logic;
6970
CLK_ETH_OUT : out std_logic;
7071
RESET_ETH : in std_logic;
7172
-- ===================================================================
@@ -384,9 +385,9 @@ begin
384385
reconfig_readdata (MI_SEL_RANGE-1 downto PMA_LANES+1) <= (others => (others => '0'));
385386

386387
-- monitoring RX link state
387-
process (ftile_clk_out)
388+
process (CLK_ETH_IN)
388389
begin
389-
if rising_edge(ftile_clk_out) then
390+
if rising_edge(CLK_ETH_IN) then
390391
if ((ftile_rx_pcs_ready = '1') or (rx_link_rst = '1')) then
391392
-- link is up, clear the counter
392393
rx_link_cnt <= (others => '0');
@@ -481,8 +482,8 @@ begin
481482
-- can't have more than 8 10g lines devided into 8 channels
482483
ftile_eth_ip_i : component ftile_eth_8x10g
483484
port map (
484-
i_clk_tx => ftile_clk_out,
485-
i_clk_rx => ftile_clk_out,
485+
i_clk_tx => CLK_ETH_IN,
486+
i_clk_rx => CLK_ETH_IN,
486487
o_clk_pll => ftile_clk_out,
487488
o_clk_tx_div => open,
488489
o_clk_rec_div64 => open,
@@ -560,9 +561,9 @@ begin
560561
RX_MACSI_MAC_ERROR <= ftile_rx_mac_error;
561562
RX_MACSI_MAC_STATUS <= ftile_rx_mac_status;
562563

563-
process (ftile_clk_out)
564+
process (CLK_ETH_IN)
564565
begin
565-
if rising_edge(ftile_clk_out) then
566+
if rising_edge(CLK_ETH_IN) then
566567
if (MI_RESET_PHY = '1') then
567568
RX_LINK_UP <= '0';
568569
TX_LINK_UP <= '0';
@@ -583,7 +584,7 @@ begin
583584
ADATAIN(0) => mgmt_mac_loop,
584585
ASEND => '1',
585586
AREADY => open,
586-
BCLK => ftile_clk_out,
587+
BCLK => CLK_ETH_IN,
587588
BRST => '0',
588589
BDATAOUT(0) => sync_repeater_ctrl,
589590
BLOAD => '1',
@@ -596,7 +597,7 @@ begin
596597
)
597598
port map (
598599
RST => RESET_ETH,
599-
CLK => ftile_clk_out,
600+
CLK => CLK_ETH_IN,
600601

601602
IN_MAC_DATA => ftile_rx_mac_data,
602603
IN_MAC_INFRAME(0) => ftile_rx_mac_inframe,

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