diff --git a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
index c6719f90b..e8249bbbd 100644
--- a/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
+++ b/cards/amd/alveo-u200/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties
diff --git a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
index c6719f90b..e8249bbbd 100644
--- a/cards/amd/vcu118/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
+++ b/cards/amd/vcu118/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties
diff --git a/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
index 8ab9078f8..3e11f18e9 100644
--- a/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
+++ b/cards/iwave/g35p/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -65,6 +65,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties
diff --git a/cards/silicom/fb2cghh/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/silicom/fb2cghh/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
index 8e5cd676f..352aab364 100644
--- a/cards/silicom/fb2cghh/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
+++ b/cards/silicom/fb2cghh/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties
diff --git a/cards/silicom/fb4cgg3/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl b/cards/silicom/fb4cgg3/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
index 9fcf67415..4ccc579bf 100644
--- a/cards/silicom/fb4cgg3/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
+++ b/cards/silicom/fb4cgg3/src/ip/pcie4_uscale_plus/pcie4_uscale_plus.ip.tcl
@@ -61,6 +61,7 @@ if {$PARAMS(PCIE_ENDPOINT_MODE) == 2} {
     set_property -dict [list \
         CONFIG.axisten_if_width {256_bit} \
         CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
+        CONFIG.coreclk_freq {500} \
     ] $IP
 } else {
     # x16 properties