diff --git a/comp/dma/dma_calypte/comp/tx/comp/software_manager/tx_dma_sw_manager.vhd b/comp/dma/dma_calypte/comp/tx/comp/software_manager/tx_dma_sw_manager.vhd
index 0e2422f1f..2fa8f50ae 100644
--- a/comp/dma/dma_calypte/comp/tx/comp/software_manager/tx_dma_sw_manager.vhd
+++ b/comp/dma/dma_calypte/comp/tx/comp/software_manager/tx_dma_sw_manager.vhd
@@ -82,7 +82,7 @@ port (
 
     STOP_REQ_CHAN        : out std_logic_vector(log2(CHANNELS)-1 downto 0);
     STOP_REQ_VLD         : out std_logic;
-    STOP_REQ_ACK         : in  std_logic;
+    STOP_REQ_ACK         : in  std_logic; --logic request one CLK delay between VLD request and ACK reponse
 
     -- general vector of all channels with their activity
     ENABLED_CHAN         : out std_logic_vector(CHANNELS-1 downto 0);
@@ -594,7 +594,7 @@ architecture FULL of TX_DMA_SW_MANAGER is
     -- =====================================================================
     --  Stop request logic
     -- =====================================================================
-    type stop_fsm_type is (IDLE, WAIT_FOR_REQ_ACK, WAIT_FOR_POINTERS);
+    type stop_fsm_type is (IDLE, WAIT_FOR_REQ_ACK, DELAY_FOR_DSP_1, DELAY_FOR_DSP_2, WAIT_FOR_POINTERS, WAIT_FOR_STATUS_UPDATE);
     signal stop_fsm_pst : stop_fsm_type;
     signal stop_fsm_nst : stop_fsm_type;
 
@@ -1115,9 +1115,23 @@ begin
             when IDLE =>
 
                 if (reg_dob_opt(R_CONTROL)(1)(0) = '0' and reg_dob_opt(R_STATUS)(1)(0) = '1') then
-                    stop_fsm_nst     <= WAIT_FOR_REQ_ACK;
+                    stop_fsm_nst     <= DELAY_FOR_DSP_1;
                     stop_fsm_channel <= active_chan_reg;
-                    STOP_REQ_CHAN    <= active_chan_reg;
+                end if;
+
+
+            when DELAY_FOR_DSP_1 =>
+
+                stop_fsm_nst     <= DELAY_FOR_DSP_2;
+
+            when DELAY_FOR_DSP_2 =>
+
+                stop_fsm_nst     <= WAIT_FOR_POINTERS;
+
+            when WAIT_FOR_POINTERS =>
+
+                if (stop_chan_ok = '1' and stop_ptr_ok = '1') then
+                    stop_fsm_nst     <= WAIT_FOR_REQ_ACK;
                     STOP_REQ_VLD     <= '1';
                 end if;
 
@@ -1125,13 +1139,13 @@ begin
             when WAIT_FOR_REQ_ACK =>
 
                 if (STOP_REQ_ACK = '1') then
-                    stop_fsm_nst <= WAIT_FOR_POINTERS;
+                    stop_fsm_nst <= WAIT_FOR_STATUS_UPDATE;
                 end if;
 
-            when WAIT_FOR_POINTERS =>
+            when WAIT_FOR_STATUS_UPDATE =>
 
-                if (stop_chan_ok = '1' and stop_ptr_ok = '1') then
-                    stop_fsm_nst                                                 <= IDLE;
+                if (stop_chan_ok = '1') then
+                    stop_fsm_nst <= IDLE;
                     stop_acked                                                   <= '1';
                     enabled_chan_rst(to_integer(unsigned(stop_fsm_channel_reg))) <= '1';
                 end if;
diff --git a/comp/dma/dma_calypte/comp/tx/uvm/tbench/dma_regs/reg_sequence.sv b/comp/dma/dma_calypte/comp/tx/uvm/tbench/dma_regs/reg_sequence.sv
index 10fdf7f43..ca68f844e 100644
--- a/comp/dma/dma_calypte/comp/tx/uvm/tbench/dma_regs/reg_sequence.sv
+++ b/comp/dma/dma_calypte/comp/tx/uvm/tbench/dma_regs/reg_sequence.sv
@@ -65,11 +65,6 @@ class stop_channel_seq extends uvm_sequence;
         m_regmodel_channel.control_reg.write(status,  32'h0,  .parent(this));
 
         do begin
-            m_regmodel_channel.hw_data_pointer_reg.read (status, data, .parent(this));
-            m_regmodel_channel.sw_data_pointer_reg.write(status, data, .parent(this));
-            m_regmodel_channel.hw_hdr_pointer_reg .read (status, data, .parent(this));
-            m_regmodel_channel.sw_hdr_pointer_reg .write(status, data, .parent(this));
-
             #(500ns);
 
             m_regmodel_channel.sw_data_pointer_reg.read(status, data, .parent(this));
@@ -85,7 +80,7 @@ class stop_channel_seq extends uvm_sequence;
             stop_attempts++;
 
             assert (stop_attempts < 500) else
-                `uvm_warning(this.get_type_name(), "\n\nThe stop of a channel takes suspiciously long time!\n")
+                `uvm_warning(m_regmodel_channel.get_full_name(), $sformatf("\nThe stop of a channel takes suspiciously long time!\n\tDATA SW(%0d) HW(%0d)\n\tHDR SW(%0d) HW(%0d)\n\tSTATUS %0d\n-----------------------\n", sw_data, hw_data, sw_hdr, hw_hdr, (data & 32'h1)));
 
         end while (sw_data != hw_data || sw_hdr != hw_hdr || (data & 32'h1) != 0);
     endtask