feat: Add MISC signals between Top-Level and NET_MOD core

Author: jakubcabal

core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd

@@ -66,6 +66,10 @@ generic(
     -- Ethernet lanes polarity
     LANE_RX_POLARITY  : std_logic_vector(LANES-1 downto 0) := (others => '0');
     LANE_TX_POLARITY  : std_logic_vector(LANES-1 downto 0) := (others => '0');
+    -- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
+    MISC_TOP2NET_WIDTH : natural := 1;
+    -- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
+    MISC_NET2TOP_WIDTH : natural := 1;
     -- Select correct FPGA device.
     -- "AGILEX", "STRATIX10", "ULTRASCALE", ...
     DEVICE            : string  := "STRATIX10"
@@ -138,6 +142,14 @@ port(
     MI_BE_PHY       : in  std_logic_vector(MI_DATA_WIDTH_PHY/8-1 downto 0);
     MI_DRD_PHY      : out std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0);
     MI_ARDY_PHY     : out std_logic;
-    MI_DRDY_PHY     : out std_logic
+    MI_DRDY_PHY     : out std_logic;
+
+    -- =========================================================================
+    -- MISC SIGNALS (the clock signal is not defined)
+    -- =========================================================================
+    -- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
+    MISC_TOP2NET    : in  std_logic_vector(MISC_TOP2NET_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
+    MISC_NET2TOP    : out std_logic_vector(MISC_NET2TOP_WIDTH-1 downto 0) := (others => '0')
 );
 end entity;

core/comp/eth/network_mod/network_mod.vhd

@@ -445,6 +445,8 @@ begin
             TX_DMA_CHANNELS   => TX_DMA_CHANNELS  ,
             LANE_RX_POLARITY  => LANE_RX_POLARITY(p*LANES+LANES-1 downto p*LANES),
             LANE_TX_POLARITY  => LANE_TX_POLARITY(p*LANES+LANES-1 downto p*LANES),
+            MISC_TOP2NET_WIDTH => MISC_TOP2NET_WIDTH,
+            MISC_NET2TOP_WIDTH => MISC_NET2TOP_WIDTH,
             DEVICE            => DEVICE
         )
         port map (
@@ -499,7 +501,10 @@ begin
             MI_WR_PHY       => mi_split_wr_phy  (p),
             MI_DRD_PHY      => mi_split_drd_phy (p),
             MI_ARDY_PHY     => mi_split_ardy_phy(p),
-            MI_DRDY_PHY     => mi_split_drdy_phy(p)
+            MI_DRDY_PHY     => mi_split_drdy_phy(p),
+
+            MISC_TOP2NET    => MISC_TOP2NET(p),
+            MISC_NET2TOP    => MISC_NET2TOP(p)
         );
 
         -- =====================================================================

core/comp/eth/network_mod/network_mod_ent.vhd

@@ -86,6 +86,10 @@ generic(
     LANE_TX_POLARITY  : std_logic_vector(ETH_PORTS*LANES-1 downto 0) := (others => '0');
     -- Number of user resets.
     RESET_WIDTH       : natural := 8;
+    -- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
+    MISC_TOP2NET_WIDTH : natural := 1;
+    -- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
+    MISC_NET2TOP_WIDTH : natural := 1;
     -- Select correct FPGA device.
     DEVICE            : string := "STRATIX10"; -- AGILEX, STRATIX10, ULTRASCALE
     BOARD             : string := "DK-DEV-1SDX-P" -- 400G1, DK-DEV-AGI027RES, DK-DEV-1SDX-P
@@ -220,6 +224,14 @@ port(
     TSU_CLK         : out std_logic;
     TSU_RST         : out std_logic;
     TSU_TS_NS       : in  std_logic_vector(64-1 downto 0);
-    TSU_TS_DV       : in  std_logic
+    TSU_TS_DV       : in  std_logic;
+
+    -- =========================================================================
+    -- MISC SIGNALS (the clock signal is not defined)
+    -- =========================================================================
+    -- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
+    MISC_TOP2NET    : in  slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0) := (others => (others => '0'));
+    -- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
+    MISC_NET2TOP    : out slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0)
 );
 end entity;

core/top/fpga_common.vhd

@@ -118,6 +118,10 @@ generic (
     MISC_TOP2PCIE_WIDTH     : natural := 1;
     -- Width of MISC signal between PCIE core logic and Top-Level FPGA design
     MISC_PCIE2TOP_WIDTH     : natural := 1;
+    -- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
+    MISC_TOP2NET_WIDTH      : natural := 1;
+    -- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
+    MISC_NET2TOP_WIDTH      : natural := 1;
 
     DEVICE                  : string := "AGILEX";
     BOARD                   : string := "400G1"
@@ -263,6 +267,10 @@ port (
     MISC_TOP2PCIE           : in    slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0) := (others => (others => '0'));
     -- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
     MISC_PCIE2TOP           : out   slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
+    MISC_TOP2NET            : in    slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0) := (others => (others => '0'));
+    -- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
+    MISC_NET2TOP            : out   slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0);
     MISC_IN                 : in    std_logic_vector(MISC_IN_WIDTH-1 downto 0) := (others => '0');
     MISC_OUT                : out   std_logic_vector(MISC_OUT_WIDTH-1 downto 0)
 );
@@ -1533,6 +1541,8 @@ begin
         LANE_RX_POLARITY  => ETH_LANE_RXPOLARITY,
         LANE_TX_POLARITY  => ETH_LANE_TXPOLARITY,
         RESET_WIDTH       => 1              ,
+        MISC_TOP2NET_WIDTH => MISC_TOP2NET_WIDTH,
+        MISC_NET2TOP_WIDTH => MISC_NET2TOP_WIDTH,
         DEVICE            => DEVICE         ,
         BOARD             => BOARD          ,
 
@@ -1634,7 +1644,10 @@ begin
         TSU_CLK         => tsu_clk,
         TSU_RST         => tsu_rst,
         TSU_TS_NS       => tsu_ns,
-        TSU_TS_DV       => tsu_dv
+        TSU_TS_DV       => tsu_dv,
+
+        MISC_TOP2NET    => MISC_TOP2NET,
+        MISC_NET2TOP    => MISC_NET2TOP
     );
 
     eth_led_ctrl_i: entity work.ETH_LED_CTRL_TOP