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‎devel/_sources/comp/base/mem/mem_clear/readme.rst.txt

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.. _mem_clear:
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Memory clear
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------------
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Simple component that will generate addresses for memory clearing when RST is asserted.
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Component port and generics description
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. vhdl:autoentity:: MEM_CLEAR
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:noautogenerics:
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Instance template
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^^^^^^^^^^^^^^^^^
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.. code-block::
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data_clear_i : entity work.MEM_CLEAR
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generic map (
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DATA_WIDTH => BOX_WIDTH,
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ITEMS => BOX_CNT,
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CLEAR_EN => CLEAR_BY_RST
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)
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port map (
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CLK => CLK,
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RST => RST,
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CLEAR_DONE => RST_DONE,
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CLEAR_WR => wr_clear,
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CLEAR_ADDR => wr_addr_clear
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);

‎devel/_sources/comp/debug/data_logger/readme.rst.txt

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Control SW
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^^^^^^^^^^
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Folder ``data_logger/sw/`` contains ``Python3`` package that provides:
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Folder ``data_logger/sw/`` contains following ``Python3`` packages:
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* Module for basic interaction with ``DATA_LOGGER``
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* Modules for ``DATA_LOGGER`` wraps like ``MEM_LOGGER``
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* Simple graph generator based on `matplotlib` library
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* Simple PDF / Markdown report generator
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* Common tools
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* ``data_logger`` ... basic interaction with ``DATA_LOGGER``
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* ``mem_logger`` ... basic interaction with ``MEM_LOGGER``
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* ``logger_stats`` ... loading firmware statistics (multiple ``DATA_LOGGERS`` can be organized in tree hierarchy)
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* ``graph_tools`` ... simple plot functions for statistics from ``logger_stats``
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Package can be installed using this command:
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* You also need to install ``python nfb`` package
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.. code-block::
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python3 -m pip install --upgrade pip
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# Install nfb:
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cd swbase/pynfb
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python3 -m pip install Cython
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python3 -m pip install .
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cd -
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# Install this package:
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cd data_logger/sw
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python3 setup.py install --user
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python3 -m pip install .
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Example usage of ``logger_stats`` (for more usage see `mem_logger/mem_logger.py`):
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.. code-block::
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import logger_stats as Stats
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from data_logger.data_logger import DataLogger
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def create_stats():
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# Create DataLoggers
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logger_0 = DataLogger(index=0, dev='/dev/nfb0')
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logger_1 = DataLogger(index=1, dev='/dev/nfb0')
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# Create Stats hierarchy
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stats = Stats.LoggerStats('Example stats')
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stats_0 = Stats.LoggerStats('Logger 0 stats', logger=logger_0)
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stats_1 = Stats.LoggerStats('Logger 1 stats', logger=logger_1)
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stats.add_stat(stats_0)
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stats.add_stat(stats_1)
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# Add basic statistics
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stats_0.add_stat(Stats.Constant(index=7, name='X'))
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stats_0.add_stat(Stats.Counter(index=7, name='Y'))
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stats_0.add_stat(Stats.Value(index=7, name='Z'))
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# FSM state statistic
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def fms_convert(v):
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states = [
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'IDLE',
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...
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]
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if v >= len(states):
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return "???"
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else:
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return states[int(v)]
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fsm_format = Stats.FormatDefaultValue(format=Stats.FormatNone)
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stats_1.add_stat(Stats.Value(2, 'FSM states', convert=fms_convert, format=fsm_format))
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# Latency statistic
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FREQ = 200 * 10**6
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time_conv = Stats.ConvertTime(FREQ)
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time_form = Stats.FormatDefaultValue(units='ns')
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stats_1.add_stat(Stats.Value(9, 'Latency', convert=time_conv, format=time_form))
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# Add value statistic which includes multiple commands
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CMDS = [
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'CMD_A',
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...
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]
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stats_1.add_stat(Stats.ValueCMD(7, 'Latency of CMDs', cmd_width=2, cmds=CMDS, convert=time_conv, format=time_form))
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# Add multiple counters
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counters = [
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'Counter A',
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...
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]
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stats_1.add_stats(
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name='Counters',
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names=counters,
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indexes=list(range(len(counters))),
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constructor=lambda i, n: Stats.Counter(i, n)
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)
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return stats
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stats = create_stats()
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stats.load()
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print(stats.to_str())
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stats.save('stats.npz')
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Example usage of ``graph_tools``:
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from graph_tools.graph_tools import load_data, plot_counter, plot_value, plot_value_2d
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stats = load_data('stats.npz')
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node = pd.DataFrame.from_dict(stats['Stats A']['Counters'])
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selected = ['Counter A', 'Counter B']
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# Plot single counter
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plot_counter(node['Counter X'], 'Time', 'Requests', 'Plot title')
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# Plot multiple counters
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plot_counter(node[selected], 'Time', 'Requests', 'Plot title')
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# Plot histogram of the value interface
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plot_value(node['Value A'], 'Time', 'Blocks', 'Title' log=True)
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# Plot 2D histogram of the value interface history
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plot_value_2d(node['Value A'], 'Time', 'Blocks', 'Title' log=True)
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MI address space

‎devel/_sources/memory.rst.txt

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**SP_URAM_XILINX** - Structural implementation of single clock URAM memory based on Xilinx specific primitives with one read/write port. Only for Xilinx UltraScale+ FPGAs.
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**<MEMORY>_CLEAR** - Wrap around **<MEMORY>** with additional clear logic.
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Detailed :ref:`documentation can be found here<mem_clear>`.
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comp/base/mem/mem_clear/readme
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References

‎devel/app-minimal.html

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<li class="toctree-l3"><a class="reference internal" href="comp/base/mem/sdp_bram/readme.html#simple-dual-port-bram-with-byte-enable">Simple dual-port BRAM with Byte Enable</a></li>
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‎devel/async.html

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<li class="toctree-l3"><a class="reference internal" href="comp/base/mem/sdp_bram/readme.html#simple-dual-port-bram-with-byte-enable">Simple dual-port BRAM with Byte Enable</a></li>
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‎devel/base.html

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<li class="toctree-l3"><a class="reference internal" href="comp/base/mem/sdp_bram/readme.html#simple-dual-port-bram-with-byte-enable">Simple dual-port BRAM with Byte Enable</a></li>
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‎devel/comp/base/dsp/dsp_comparator/readme.html

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‎devel/comp/base/fifo/asfifox/readme.html

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‎devel/comp/base/fifo/fifox/readme.html

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‎devel/comp/base/fifo/fifox_multi/readme.html

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