diff --git a/app/uvm/tests/base.sv b/app/uvm/tests/base.sv
index e519b1607..bb99ae0e8 100644
--- a/app/uvm/tests/base.sv
+++ b/app/uvm/tests/base.sv
@@ -109,6 +109,7 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
         uvm_app_core::sequence_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH,  MFB_ITEM_WIDTH,
                         ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH) stop_seq;
         time end_time;
+        int rdy2end;
 
         main_seq = uvm_app_core::sequence_main#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH,  MFB_ITEM_WIDTH,
                        ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH)::type_id::create("main_seq", m_env.m_sequencer);
@@ -150,9 +151,16 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
                 stop_seq.start(m_env.m_sequencer);
             join_none;
 
-            end_time = $time() + 400us;
-            while (end_time > $time() && m_env.used() != 0) begin
-                #(500ns);
+            end_time = $time() + 1ms; // Prevents verification from freezing after a very long time!
+            rdy2end = 0;
+            while (end_time > $time() && rdy2end < 5) begin
+                // The check of the number of incomplete packets in the verification must pass repeatedly!
+                if (m_env.used() == 0) begin
+                    rdy2end++;
+                end else begin
+                    rdy2end = 0;
+                end
+                #(1us);
             end
             if (m_env.used() != 0) begin
                 `uvm_warning(this.get_full_name(), $sformatf("\n\tUSED(%0d) sould be zero.\n\tDuring reconfiguration, There is some data in design", m_env.used()));
diff --git a/app/uvm/tests/fifo.sv b/app/uvm/tests/fifo.sv
index 77eb8c4ab..27d092c41 100644
--- a/app/uvm/tests/fifo.sv
+++ b/app/uvm/tests/fifo.sv
@@ -368,6 +368,7 @@ class fifo#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
         test::sequence_fifo_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH,  MFB_ITEM_WIDTH,
                             ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH) stop_seq;
         time end_time;
+        int rdy2end;
 
         main_seq = test::sequence_fifo#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH,  MFB_ITEM_WIDTH,
                             ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH)::type_id::create("main_seq", m_env.m_sequencer);
@@ -404,9 +405,16 @@ class fifo#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
                 stop_seq.start(m_env.m_sequencer);
             join_none;
 
-            end_time = $time() + 400us;
-            while (end_time > $time() && m_env.used() != 0) begin
-                #(500ns);
+            end_time = $time() + 1ms; // Prevents verification from freezing after a very long time!
+            rdy2end = 0;
+            while (end_time > $time() && rdy2end < 5) begin
+                // The check of the number of incomplete packets in the verification must pass repeatedly!
+                if (m_env.used() == 0) begin
+                    rdy2end++;
+                end else begin
+                    rdy2end = 0;
+                end
+                #(1us);
             end
             if (m_env.used() != 0) begin
                 `uvm_warning(this.get_full_name(), $sformatf("\n\tUSED(%0d) sould be zero.\n\tDuring reconfiguration, There is some data in design", m_env.used()));
diff --git a/app/uvm/tests/full_speed.sv b/app/uvm/tests/full_speed.sv
index ac456a460..49405adf4 100644
--- a/app/uvm/tests/full_speed.sv
+++ b/app/uvm/tests/full_speed.sv
@@ -146,6 +146,7 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_
         uvm_app_core::sequence_stop#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH,  MFB_ITEM_WIDTH,
                     ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH) stop_seq;
         time end_time;
+        int rdy2end;
 
         main_seq = test::sequence_speed#(DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_PKT_MTU, DMA_HDR_META_WIDTH, DMA_STREAMS, ETH_TX_HDR_WIDTH,  MFB_ITEM_WIDTH,
                     ETH_STREAMS, REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MEM_PORTS, MEM_ADDR_WIDTH, MEM_DATA_WIDTH, MEM_BURST_WIDTH)::type_id::create("main_seq", m_env.m_sequencer);
@@ -187,11 +188,17 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_
                 stop_seq.start(m_env.m_sequencer);
             join_none;
 
-            end_time = $time() + 200us;
-            while (end_time > $time() && m_env.used() != 0) begin
-                #(500ns);
+            end_time = $time() + 1ms; // Prevents verification from freezing after a very long time!
+            rdy2end = 0;
+            while (end_time > $time() && rdy2end < 5) begin
+                // The check of the number of incomplete packets in the verification must pass repeatedly!
+                if (m_env.used() == 0) begin
+                    rdy2end++;
+                end else begin
+                    rdy2end = 0;
+                end
+                #(1us);
             end
-
             if (m_env.used() != 0) begin
                 `uvm_warning(this.get_full_name(), $sformatf("\n\tUSED(%0d) sould be zero.\n\tDuring reconfiguration, There is some data in design", m_env.used()));
             end