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6 | 6 |
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7 | 7 | #include <peripheral_clk_config.h> |
8 | 8 |
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| 9 | +#ifndef CONF_SERCOM_0_USART_ENABLE |
| 10 | +#define CONF_SERCOM_0_USART_ENABLE 1 |
| 11 | +#endif |
| 12 | + |
| 13 | +// <h> Basic Configuration |
| 14 | + |
| 15 | +// <q> Receive buffer enable |
| 16 | +// <i> Enable input buffer in SERCOM module |
| 17 | +// <id> usart_rx_enable |
| 18 | +#ifndef CONF_SERCOM_0_USART_RXEN |
| 19 | +#define CONF_SERCOM_0_USART_RXEN 1 |
| 20 | +#endif |
| 21 | + |
| 22 | +// <q> Transmitt buffer enable |
| 23 | +// <i> Enable output buffer in SERCOM module |
| 24 | +// <id> usart_tx_enable |
| 25 | +#ifndef CONF_SERCOM_0_USART_TXEN |
| 26 | +#define CONF_SERCOM_0_USART_TXEN 1 |
| 27 | +#endif |
| 28 | + |
| 29 | +// <o> Frame parity |
| 30 | +// <0x0=>No parity |
| 31 | +// <0x1=>Even parity |
| 32 | +// <0x2=>Odd parity |
| 33 | +// <i> Parity bit mode for USART frame |
| 34 | +// <id> usart_parity |
| 35 | +#ifndef CONF_SERCOM_0_USART_PARITY |
| 36 | +#define CONF_SERCOM_0_USART_PARITY 0x0 |
| 37 | +#endif |
| 38 | + |
| 39 | +// <o> Character Size |
| 40 | +// <0x0=>8 bits |
| 41 | +// <0x1=>9 bits |
| 42 | +// <0x5=>5 bits |
| 43 | +// <0x6=>6 bits |
| 44 | +// <0x7=>7 bits |
| 45 | +// <i> Data character size in USART frame |
| 46 | +// <id> usart_character_size |
| 47 | +#ifndef CONF_SERCOM_0_USART_CHSIZE |
| 48 | +#define CONF_SERCOM_0_USART_CHSIZE 0x0 |
| 49 | +#endif |
| 50 | + |
| 51 | +// <o> Stop Bit |
| 52 | +// <0=>One stop bit |
| 53 | +// <1=>Two stop bits |
| 54 | +// <i> Number of stop bits in USART frame |
| 55 | +// <id> usart_stop_bit |
| 56 | +#ifndef CONF_SERCOM_0_USART_SBMODE |
| 57 | +#define CONF_SERCOM_0_USART_SBMODE 0 |
| 58 | +#endif |
| 59 | + |
| 60 | +// <o> Baud rate <1-6250000> |
| 61 | +// <i> USART baud rate setting |
| 62 | +// <id> usart_baud_rate |
| 63 | +#ifndef CONF_SERCOM_0_USART_BAUD |
| 64 | +#define CONF_SERCOM_0_USART_BAUD 115200 |
| 65 | +#endif |
| 66 | + |
| 67 | +// </h> |
| 68 | + |
| 69 | +// <e> Advanced configuration |
| 70 | +// <id> usart_advanced |
| 71 | +#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG |
| 72 | +#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0 |
| 73 | +#endif |
| 74 | + |
| 75 | +// <q> Run in stand-by |
| 76 | +// <i> Keep the module running in standby sleep mode |
| 77 | +// <id> usart_arch_runstdby |
| 78 | +#ifndef CONF_SERCOM_0_USART_RUNSTDBY |
| 79 | +#define CONF_SERCOM_0_USART_RUNSTDBY 0 |
| 80 | +#endif |
| 81 | + |
| 82 | +// <q> Immediate Buffer Overflow Notification |
| 83 | +// <i> Controls when the BUFOVF status bit is asserted |
| 84 | +// <id> usart_arch_ibon |
| 85 | +#ifndef CONF_SERCOM_0_USART_IBON |
| 86 | +#define CONF_SERCOM_0_USART_IBON 0 |
| 87 | +#endif |
| 88 | + |
| 89 | +// <q> Start of Frame Detection Enable |
| 90 | +// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) |
| 91 | +// <id> usart_arch_sfde |
| 92 | +#ifndef CONF_SERCOM_0_USART_SFDE |
| 93 | +#define CONF_SERCOM_0_USART_SFDE 0 |
| 94 | +#endif |
| 95 | + |
| 96 | +// <q> Collision Detection Enable |
| 97 | +// <i> Collision detection enable |
| 98 | +// <id> usart_arch_cloden |
| 99 | +#ifndef CONF_SERCOM_0_USART_CLODEN |
| 100 | +#define CONF_SERCOM_0_USART_CLODEN 0 |
| 101 | +#endif |
| 102 | + |
| 103 | +// <o> Operating Mode |
| 104 | +// <0x0=>USART with external clock |
| 105 | +// <0x1=>USART with internal clock |
| 106 | +// <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. |
| 107 | +// <id> usart_arch_clock_mode |
| 108 | +#ifndef CONF_SERCOM_0_USART_MODE |
| 109 | +#define CONF_SERCOM_0_USART_MODE 0x1 |
| 110 | +#endif |
| 111 | + |
| 112 | +// Does not do anything in USRT mode |
| 113 | +#define CONF_SERCOM_0_USART_SAMPR 0x0 |
| 114 | +#define CONF_SERCOM_0_USART_SAMPA 0x0 |
| 115 | +#define CONF_SERCOM_0_USART_FRACTIONAL 0x0 |
| 116 | + |
| 117 | +// <o> Data Order |
| 118 | +// <0=>MSB is transmitted first |
| 119 | +// <1=>LSB is transmitted first |
| 120 | +// <i> Data order of the data bits in the frame |
| 121 | +// <id> usart_arch_dord |
| 122 | +#ifndef CONF_SERCOM_0_USART_DORD |
| 123 | +#define CONF_SERCOM_0_USART_DORD 1 |
| 124 | +#endif |
| 125 | + |
| 126 | +// Does not do anything in UART mode |
| 127 | +#define CONF_SERCOM_0_USART_CPOL 0 |
| 128 | + |
| 129 | +// Does not do anything in USRT mode |
| 130 | +#define CONF_SERCOM_0_USART_ENC 0 |
| 131 | + |
| 132 | +// Does not do anything in USRT mode |
| 133 | +#define CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE 0 |
| 134 | + |
| 135 | +// <o> Debug Stop Mode |
| 136 | +// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. |
| 137 | +// <0=>Keep running |
| 138 | +// <1=>Halt |
| 139 | +// <id> usart_arch_dbgstop |
| 140 | +#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE |
| 141 | +#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0 |
| 142 | +#endif |
| 143 | + |
| 144 | +// </e> |
| 145 | + |
| 146 | +#ifndef CONF_SERCOM_0_USART_INACK |
| 147 | +#define CONF_SERCOM_0_USART_INACK 0x0 |
| 148 | +#endif |
| 149 | + |
| 150 | +#ifndef CONF_SERCOM_0_USART_DSNACK |
| 151 | +#define CONF_SERCOM_0_USART_DSNACK 0x0 |
| 152 | +#endif |
| 153 | + |
| 154 | +#ifndef CONF_SERCOM_0_USART_MAXITER |
| 155 | +#define CONF_SERCOM_0_USART_MAXITER 0x7 |
| 156 | +#endif |
| 157 | + |
| 158 | +#ifndef CONF_SERCOM_0_USART_GTIME |
| 159 | +#define CONF_SERCOM_0_USART_GTIME 0x2 |
| 160 | +#endif |
| 161 | + |
| 162 | +#define CONF_SERCOM_0_USART_RXINV 0x0 |
| 163 | +#define CONF_SERCOM_0_USART_TXINV 0x0 |
| 164 | + |
| 165 | +#ifndef CONF_SERCOM_0_USART_CMODE |
| 166 | +#define CONF_SERCOM_0_USART_CMODE 0 |
| 167 | +#endif |
| 168 | + |
| 169 | +#ifndef CONF_SERCOM_0_USART_RXPO |
| 170 | +#define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA05 */ |
| 171 | +#endif |
| 172 | + |
| 173 | +#ifndef CONF_SERCOM_0_USART_TXPO |
| 174 | +#define CONF_SERCOM_0_USART_TXPO 2 /* TX is on PIN_PA04 */ |
| 175 | +#endif |
| 176 | + |
| 177 | +/* Set correct parity settings in register interface based on PARITY setting */ |
| 178 | +#if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 1 |
| 179 | +#if CONF_SERCOM_0_USART_PARITY == 0 |
| 180 | +#define CONF_SERCOM_0_USART_PMODE 0 |
| 181 | +#define CONF_SERCOM_0_USART_FORM 4 |
| 182 | +#else |
| 183 | +#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 |
| 184 | +#define CONF_SERCOM_0_USART_FORM 5 |
| 185 | +#endif |
| 186 | +#else /* #if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 0 */ |
| 187 | +#if CONF_SERCOM_0_USART_PARITY == 0 |
| 188 | +#define CONF_SERCOM_0_USART_PMODE 0 |
| 189 | +#define CONF_SERCOM_0_USART_FORM 0 |
| 190 | +#else |
| 191 | +#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 |
| 192 | +#define CONF_SERCOM_0_USART_FORM 1 |
| 193 | +#endif |
| 194 | +#endif |
| 195 | + |
| 196 | +// Calculate BAUD register value in UART mode |
| 197 | +#if CONF_SERCOM_0_USART_SAMPR == 0 |
| 198 | +#ifndef CONF_SERCOM_0_USART_BAUD_RATE |
| 199 | +#define CONF_SERCOM_0_USART_BAUD_RATE \ |
| 200 | + 65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) |
| 201 | +#endif |
| 202 | +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH |
| 203 | +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 |
| 204 | +#endif |
| 205 | +#elif CONF_SERCOM_0_USART_SAMPR == 1 |
| 206 | +#ifndef CONF_SERCOM_0_USART_BAUD_RATE |
| 207 | +#define CONF_SERCOM_0_USART_BAUD_RATE \ |
| 208 | + ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) |
| 209 | +#endif |
| 210 | +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH |
| 211 | +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 |
| 212 | +#endif |
| 213 | +#elif CONF_SERCOM_0_USART_SAMPR == 2 |
| 214 | +#ifndef CONF_SERCOM_0_USART_BAUD_RATE |
| 215 | +#define CONF_SERCOM_0_USART_BAUD_RATE \ |
| 216 | + 65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) |
| 217 | +#endif |
| 218 | +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH |
| 219 | +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 |
| 220 | +#endif |
| 221 | +#elif CONF_SERCOM_0_USART_SAMPR == 3 |
| 222 | +#ifndef CONF_SERCOM_0_USART_BAUD_RATE |
| 223 | +#define CONF_SERCOM_0_USART_BAUD_RATE \ |
| 224 | + ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) |
| 225 | +#endif |
| 226 | +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH |
| 227 | +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 |
| 228 | +#endif |
| 229 | +#elif CONF_SERCOM_0_USART_SAMPR == 4 |
| 230 | +#ifndef CONF_SERCOM_0_USART_BAUD_RATE |
| 231 | +#define CONF_SERCOM_0_USART_BAUD_RATE \ |
| 232 | + 65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) |
| 233 | +#endif |
| 234 | +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH |
| 235 | +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 |
| 236 | +#endif |
| 237 | +#endif |
| 238 | + |
| 239 | +#include <peripheral_clk_config.h> |
| 240 | + |
9 | 241 | #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER |
10 | 242 | #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) |
11 | 243 | #endif |
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