移植到正点原子，uboot LAN8720A, 网口tftp 一直 报错

[DanielCao0]

请问移植LAN8720A 有计划么

[Charliechen114514]

您好！抱歉现在才看到！“uboot LAN8720A, 网口tftp 一直 报错”的话，麻烦可以发一下日志我看看可能是什么问题。

然后的话LAN8720A，因为我的底板是V2.4的，不是用的老芯片QAQ，目前只能支持SR8201F了

[Charliechen114514]

不过的话，可以发送下日志 + 设备树，看看可能是什么问题。也有可能是上位机tftp没有配置好

[DanielCao0]

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (C) 2016 Freescale Semiconductor, Inc.

/dts-v1/;

#include "imx6ull.dtsi"
#include "imx6ul-14x14-evk.dtsi"
#include "imx6ul-14x14-evk-u-boot.dtsi"

/ {
	model = "ALIENTEK i.MX6ULL Mini";
	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";

	/*
	 * Mini boards only bring out ENET2; default eth0 maps to fec1.
	 * Point ethernet0 at fec2 so CONFIG_ETHPRIME=eth0 hits the real PHY.
	 */
	aliases {
		ethernet0 = &fec2;
		ethernet1 = &fec1;
	};
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>,
			  <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <320000000>, <786432000>;
};

&csi {
	status = "okay";
};

&ov5640 {
	status = "okay";
};

/delete-node/ &sim2;

&{/spi-4} {
	status = "disabled";
};

/*
 * Mini (正点原子): one RJ45 on ENET2 only — LAN8720A @ MDIO addr 1,
 * nRST on SNVS_TAMPER8 (GPIO5_IO08). fec1 disabled per official lab notes
 * 「只使用 ENET2」; see e.g. ATK imx6ULL mini Linux Ethernet chapter.
 */

&fec1 {
	/delete-property/ phy-handle;
	status = "disabled";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2_myboard &pinctrl_enet_mini2_reset>;
	phy-mode = "rmii";
	phy-handle = <&mini_ethphy1>;
	phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <200>;
	phy-reset-post-delay = <100>;
	phy-supply = <&reg_peri_3v3>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/delete-node/ ethernet-phy@2;
		/delete-node/ ethernet-phy@1;

		mini_ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
			clock-names = "rmii-ref";
		};
	};
};

/* gpio_spi is labeled gpio@0 under /spi-4; delete hog children here... */
&gpio_spi {
	/delete-node/ eth0-phy-hog;
	/delete-node/ eth1-phy-hog;
};

/*
 * ...cannot append /delete-property/ after hog subnodes in &gpio_spi; delete
 * 595 latch enable-gpios on the actual gpio_spi node by full path instead.
 */
&{/spi-4/gpio@0} {
	/delete-property/ enable-gpios;
};

&iomuxc {
	pinctrl_enet2_myboard: enet2myboardgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b009
		>;
	};

	/* Keep 595 SCK/MOSI only; TAMPER8 belongs to ENET2 PHY nRST on Mini */
	pinctrl_spi4: spi4grp {
		fsl,pins = <
			MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
			MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
		>;
	};

	pinctrl_enet_mini2_reset: enetmini2resetgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x10b0
		>;
	};
};

&display0 {
	bits-per-pixel = <24>;
	bus-width = <24>;
};

&timing0 {
	clock-frequency = <31000000>;
	hactive = <800>;
	vactive = <480>;
	hfront-porch = <40>;
	hback-porch = <88>;
	hsync-len = <48>;
	vback-porch = <32>;
	vfront-porch = <13>;
	vsync-len = <3>;
	hsync-active = <0>;
	vsync-active = <0>;
	de-active = <1>;
	pixelclk-active = <0>;
};

[DanielCao0]

我试了出厂了uboot ，环境是好的， 现在很奇怪，ping 可以 ，dhcp 也可以，但是tftp缺一直失败，应该LAN8720A 有哪里配置不对

[DanielCao0]

[DanielCao0]

[DanielCao0]

补充一下，我是1.7 MINI 的底板， 弄了好几天，找不到办法了，希望大神帮助，感谢

[Charliechen114514]

稍等以下哈，我在帮您看看，查查资料，看起来像是网卡底层啥参数搞错了。导致传输不太稳定（ping没事是因为包小可能）

[Charliechen114514]

你好,根据你贴的日志, 我大致猜测是这样的，我grep了以下uboot-imx的源码：这行打印来自 drivers/net/fec_mxc.c,就是把 FEC 中断事件寄存器的值打出来,0x40000000 这个位就是 BABR，是 U-Boot 的 FEC 驱动报的 BABR(Babbling Receiver)——FEC 收到了超长或帧定界异常的包。

我翻了下代码，ping / DHCP 都正常、只有 tftp 挂应该是因为ping、DHCP 都是小包,不会触发 BABR; tftp您应该知道，是大批量的运送内核和设备树的（起步都是几MB）正好压在 RMII 接收最吃紧的状态,一旦出现帧定界/时序异常,FEC 就置 BABR; 而 FEC 驱动检测到 BABR 后的处理是直接把 FEC halt 再 init 重启、并丢掉当前帧——所以每冒一次 BABR 就丢一批包,tftp 就一直超时重传(日志里那一长串 T),最后失败。

主要是因为咱们这个过程是针对 SR8201F 适配的——PHY 驱动、设备树里的 PHY id、还有板级 board_phy_config() 里对 PHY 的专用寄存器配置,都是按 SR8201F 写的。直接套到 LAN8720A 上,PHY 这层没被正确对待,RMII 大流量接收时序对不上,就冒 BABR。ping/DHCP 能通是因为小包还撑得住,大流量就露馅了。

建议这样处理:

先快速验证(几乎不用改代码),在 U-Boot 命令行把 tftp 块调小:

setenv tftpblocksize 512

如果调小后明显好转,基本就坐实是 BABR / 接收时序问题。

您可能需要看看正点原子在教程提供的参数，可能需要您确认以下：

1. 打开 LAN8720A 的 PHY 驱动:CONFIG_PHY_SMSC=y;（应该是默认打开的，正点我记得没提，这个当备选）
2. 设备树 PHY id 改成 LAN8720A 的(0007.c0f0),或去掉强制 id 让驱动自动匹配;
3. 重点检查 board_phy_config() 里对 PHY 写的寄存器——那是按我们的 PHY(SR8201F)写的,别原样套到 LAN8720A,按需屏蔽或改成 LAN8720A 自己的配置;
4. 确认 RMII 50M 参考时钟方向:i.MX 输出 50M 给 PHY、PHY 配成参考时钟输入。

然后的话，因为笔者手头没有LAN8720A， 这个真的没办法由笔者来维护驱动，目前的话可能暂不在我们主线支持范围(我们底板用的是 SR8201F),但按上面改应该就能跑通。改完还有问题的话,把新日志和改后的设备树发我看下 QAQ

[Charliechen114514]

可能做法不太对，因为我手头真没这个板子，要不然会尝试复现下的（手动捂脸，这个可能有点无能为力，但是肯定是FEC 收到了超长或帧定界异常的包。也就是您的驱动没配好板子，可以看看正点咋做的QAQ，只能迁移下了~

[DanielCao0]

打开 LAN8720A 的 PHY 驱动:CONFIG_PHY_SMSC=y;（应该是默认打开的，正点我记得没提，这个当备选） 已经开启
设备树 PHY id 改成 LAN8720A 的(0007.c0f0),或去掉强制 id 让驱动自动匹配; 删除了
setenv tftpblocksize 512 之后会有改善，但是还是有问题

[DanielCao0]

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 */

#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <config.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/sizes.h>
#include <linux/delay.h>
#include <mmc.h>
#include <miiphy.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"

DECLARE_GLOBAL_DATA_PTR;

#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
	PAD_CTL_ODE)

#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)

#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
			PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)


#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
	struct udevice *dev;
	int ret, dev_id, rev_id;
	unsigned int reg;

	ret = pmic_get("pfuze3000@8", &dev);
	if (ret == -ENODEV)
		return 0;
	if (ret != 0)
		return ret;

	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);

	/* disable Low Power Mode during standby mode */
	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
	reg |= 0x1;
	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);

	/* SW1B step ramp up time from 2us to 4us/25mV */
	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);

	/* SW1B mode to APS/PFM */
	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);

	/* SW1B standby voltage set to 0.975V */
	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);

	return 0;
}

#ifdef CONFIG_LDO_BYPASS_CHECK
void ldo_mode_set(int ldo_bypass)
{
	unsigned int value;
	u32 vddarm;
	struct udevice *dev;
	int ret;

	ret = pmic_get("pfuze3000@8", &dev);
	if (ret == -ENODEV) {
		printf("No PMIC found!\n");
		return;
	}

	/* switch to ldo_bypass mode */
	if (ldo_bypass) {
		prep_anatop_bypass();
		/* decrease VDDARM to 1.275V */
		value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
		value &= ~0x1f;
		value |= PFUZE3000_SW1AB_SETP(12750);
		pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);

		set_anatop_bypass(1);
		vddarm = PFUZE3000_SW1AB_SETP(11750);

		value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
		value &= ~0x1f;
		value |= vddarm;
		pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);

		finish_anatop_bypass();

		printf("switch to ldo_bypass mode!\n");
	}
}
#endif
#endif

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

int board_mmc_get_env_dev(int devno)
{
	return devno;
}

#ifdef CONFIG_FSL_QSPI

#ifndef CONFIG_DM_SPI
#define QSPI_PAD_CTRL1	\
	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)

static iomux_v3_cfg_t const quadspi_pads[] = {
	MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
#endif

static int board_qspi_init(void)
{
#ifndef CONFIG_DM_SPI
	/* Set the iomux */
	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
					 ARRAY_SIZE(quadspi_pads));
#endif
	/* Set the clock */
	enable_qspi_clk(0);

	return 0;
}
#endif

#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const nand_pads[] = {
	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
};

static void setup_gpmi_nand(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* config gpmi nand iomux */
	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));

	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));

	/* enable apbh clock gating */
	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif

#ifdef CONFIG_FEC_MXC
#define IOMUXC_ENET2_TX_CLK_MUX_OFFSET	0x00fc

/*
 * ALIENTEK boards set ENET2_TX_CLK to ALT4 (ENET2_REF_CLK2) with SION in the
 * Linux fec driver (writel(0x14, 0x020E00FC)). Mirror that here so the 50 MHz
 * ref clock is output to the PHY and looped back to the MAC before pinctrl runs.
 */
static void set_enet2_ref_clk_sion(void)
{
	writel(0x14, (void *)(IOMUXC_BASE_ADDR + IOMUXC_ENET2_TX_CLK_MUX_OFFSET));
}

static int setup_fec(void)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;

	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);

	set_enet2_ref_clk_sion();

	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
	if (ret)
		return ret;

	enable_enet_clk(1);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	/*
	 * ALIENTEK Mini uses a single LAN8720A on ENET2 (MDIO addr 1).
	 * Do NOT touch register 0x1F here — that register is AR803x-specific
	 * (MMD delay control). On LAN8720A reg 0x1F is the "Special Control/
	 * Status Register"; writing AR803x magic values into it scrambles
	 * bits like SQE-OFF / reserved, which then shows up as MAC-side
	 * BABR (IEVENT 0x40000000) when frames arrive. Just let the generic
	 * PHY driver run its config (auto-negotiation).
	 */
	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}
#endif

#ifdef CONFIG_VIDEO
static iomux_v3_cfg_t const lcd_pads[] = {
	/* Use GPIO for Brightness adjustment, duty cycle = period. */
	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static int setup_lcd(void)
{
	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);

	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));

	/* Reset the LCD */
	gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
	udelay(500);
	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);

	/* Set Brightness to high */
	gpio_request(IMX_GPIO_NR(1, 8), "backlight");
	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);

	return 0;
}
#else
static inline int setup_lcd(void) { return 0; }
#endif

int board_early_init_f(void)
{
	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef	CONFIG_FEC_MXC
	setup_fec();
#endif

#ifdef CONFIG_FSL_QSPI
	board_qspi_init();
#endif

#ifdef CONFIG_NAND_MXS
	setup_gpmi_nand();
#endif

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

	env_set("tee", "no");
#ifdef CONFIG_IMX_OPTEE
	env_set("tee", "yes");
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	env_set("board_name", "MYBOARD");
	env_set("board_rev", "A");

	if (is_cpu_type(MXC_CPU_MX6ULZ)) {
		env_set("board_name", "ULZ-EVK");
		env_set("usb_net_cmd", "usb start");
	}
#endif

	setup_lcd();

#ifdef CONFIG_ENV_IS_IN_MMC
	board_late_mmc_env_init();
#endif

	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);

	return 0;
}

int checkboard(void)
{
	puts("Board: MX6ULL My Board\n");

	return 0;
}

void board_quiesce_devices(void)
{
#if defined(CONFIG_VIDEO_MXS)
	enable_lcdif_clock(LCDIF1_BASE_ADDR, 0);
#endif
}