diff --git a/ARM.CMSIS-Driver_Validation.pdsc b/ARM.CMSIS-Driver_Validation.pdsc index fd08806..c3d4ef7 100644 --- a/ARM.CMSIS-Driver_Validation.pdsc +++ b/ARM.CMSIS-Driver_Validation.pdsc @@ -10,6 +10,7 @@ Active Development ... + - Add Driver Validation application template - Add GPIO Driver validation - Update SPI Server application to CMSIS solution format - Add SPI Server application template @@ -277,6 +278,13 @@ + + CMSIS-Driver Validation application + + + + + CMSIS-Driver Validation SPI Server application for STM32F429I-DISC1 board diff --git a/Documentation/Doxygen/src/DriverValidation.txt b/Documentation/Doxygen/src/DriverValidation.txt index 8c924ba..da213bf 100644 --- a/Documentation/Doxygen/src/DriverValidation.txt +++ b/Documentation/Doxygen/src/DriverValidation.txt @@ -1,4 +1,4 @@ -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \mainpage Overview @@ -70,78 +70,41 @@ The table below provides information about the changes delivered with specific v /** \page setup Setup -\section step1 Step 1: Create an MDK project for your target microcontroller device - - -\section step2 Step 2: Add the required software components - -For proper operation, add the following software components in the Manage Run-Time Environment window: -- CMSIS Driver Validation: Framework -- CMSIS Driver Validation: driver, driver interfaces to be tested -- CMSIS Driver: driver, driver implementations to be tested -- CMSIS: RTOS2 (API): Keil RTX5 -- Compiler: I/O: STDOUT, variant \b ITM (if your hardware does not support ITM select \b EVR to use Event Recorder instead of ITM) -- Resolve any unresolved component dependencies - - -\section step3 Step 3: Add the application's main file (main.c) - -Right-click Source Group 1... and select Add New Item to Group, select User Code Template and choose the -CMSIS-RTOS2 'main' function file from CMSIS: RTOS2:Keil RTX5. - -Add this include: -\code -#include "cmsis_dv.h" -\endcode - -In the app_main function, create the \c cmsis_dv thread, before endless for loop: -\code -osThreadNew(cmsis_dv, NULL, NULL); -\endcode -to run all the tests that you have chosen in the next step. - - -\section step4 Step 4: Configure the interface settings and tests in related DV_interface_Config.h files - -Each interface has a related DV_interface_Config.h file, where interface represents interface's acronym or abbreviation.
-For example for Serial Peripheral Interface (SPI) related config file name is DV_SPI_Config.h. - -For details on interface specific configuration and test selection please check the Configuration section in the -Reference of the related interface. - - -\section step5 Step 5: Configure the Heap memory +Using the [Arm CMSIS Solution](https://marketplace.visualstudio.com/items?itemName=Arm.cmsis-csolution) VS Code extension, +create a new solution from **template**: -Depending on the buffer sizes used for data transfer tests the heap size has to be adjusted to provide enough memory for these -buffers to be allocated.
-Depending on how heap is configured in your system, open your startup_\.s or startup_\.c file from the \b Device group in the \b Project window -or use a linker script to adjust the heap size.
-Set the heap size to minimum of 16384 bytes. +\section step1 Step 1: In the **CMSIS** extension, click **Create a New Solution**. +\image html server_new_sol_create.png -For details on heap requirements please refer to the \ref heap_req "Heap Memory requirements" documentation. +\section step2 Step 2: Select the **Target Board**. +\section step3 Step 3: Under **Templates, Reference Applications, and Examples**, select **Driver Validation (CMSIS-Driver Validation application)**. +\image html driver_validation_new_sol_template.png -\section step6 Step 6: Configure the CMSIS-RTOS2 (Keil RTX5) +\section step4 Step 4: Choose **Solution Base Folder**, click **Create**. +\image html driver_validation_new_sol_create.png -Open RTX_Config.h and set: -- System Configuration: Global Dynamic Memory size [bytes] to \a 16384 -- Thread configuration: Default Thread stack size [bytes] to \a 3072 +\section step5 Step 5: Select the **Board Layer** that provides **required CMSIS Driver**, click **OK**. +\image html driver_validation_new_sol_layer.png -For details on CMSIS-RTOS2 requirements please refer to the \ref rtos2_req "CMSIS-RTOS2 requirements" documentation. +\section step6 Step 6: In the **Manage Solution**, under **Build Type** select desired Driver for validation, click **Save**. +\image html driver_validation_build_type.png -\section step7 Step 7: Configure the Device +\section step7 Step 7: Configure the Driver Tests in appropriate **DV_..._Config.h** file. -Depending on your device, you might have different pin/hardware configuration options. Usually, you can configure the device -using the \c RTE_Device.h file from the \b Device group or with a vendor provided pin configuration tool. -Enable all interfaces you wish to test and make all necessary pin-out changes required by your actual board layout (consult the board schematics).
-You can check the provided \ref examples "examples" as a reference point. - -For a robust test with good coverage, implement various targets with different settings: -- Use non-DMA (IRQ) and DMA configurations if they are available on the driver -- Use different compiler optimization levels in the - C/C++ tab of the - Options for Target dialog +> **Note:** `...` in **DV_`...`_Config.h** file depends on the driver being validated; for example, for Ethernet, the file would be **DV_ETH_Config.h** file. +For validation configuration of specific driver check respective driver documentation: +- [CAN](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__can__config.html) +- [Ethernet](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__eth__config.html) +- [GPIO](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__gpio__config.html) +- [I2C](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__i2c__config.html) +- [MCI](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__mci__config.html) +- [SPI](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__spi__config.html) +- [USART](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__usart__config.html) +- [USB Device](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__usbd__config.html) +- [USB Host](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__usbh__config.html) +- [WiFi](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__wifi__config.html) \section step8 Step 8: Setup the required hardware @@ -152,89 +115,60 @@ connect the following pins on your target hardware together (refer to the hardwa - USART: RX and TX - SPI: MOSI and MISO -For the interfaces that support testing with dedicated server: \ref dv_wifi "WiFi" and \ref dv_spi "SPI", +For the interfaces that support testing with dedicated server: \ref dv_wifi "WiFi", \ref dv_spi "SPI" and \ref dv_usart "USART" connect the related hardware as required by the related server: - WiFi: WiFi module has to be in close proximity to the Access Point which is in the same network as the required \ref wifi_sock_setup - SPI: MOSI, MISO, SCLK, SS, GND to the same lines on the \ref spi_server +- USART: Tx, Rx, GND and optionally CLK, CTS, RTS, DCD and RI lines as described in \ref usart_server +\section step9 Step 9: Build and Run the application -\section step9 Step 9: Download and Run the Project - -In the Options for Target dialog, under debug settings, if you use ITM as standard output channel ensure that -\b Trace and ITM port 0 are enabled and that the correct Core Clock frequency is set: - -\image html target_dialog.png "ITM Channel setting" - -Build, load and run the project. The output is displayed in the Debug (printf) Viewer window.
-Example below shows output result of an SPI driver testing: +Example below shows output results (in STDOUT channel) of an Ethernet driver testing: \verbatim -CMSIS-Driver_Validation v3.0.0 CMSIS-Driver SPI Test Report March 30 2022 13:44:11 +CMSIS-Driver_Validation v3.1.0 CMSIS-Driver ETH Test Report Oct 9 2025 07:30:34 -TEST 01: SPI_GetVersion - DV_SPI.c (1023): [INFO] Driver API version 2.3, Driver version 2.15 +TEST 01: ETH_MAC_GetVersion + DV_ETH.c (267): [INFO] API version 2.2, Driver version 3.1 PASSED -TEST 02: SPI_GetCapabilities PASSED -TEST 03: SPI_Initialize_Uninitialize PASSED -TEST 04: SPI_PowerControl - DV_SPI.c (1314): [WARNING] PowerControl (ARM_POWER_LOW) is not supported +TEST 02: ETH_MAC_GetCapabilities PASSED +TEST 03: ETH_MAC_Initialization PASSED +TEST 04: ETH_MAC_PowerControl + DV_ETH.c (366): [WARNING] Low power is not supported PASSED -TEST 05: SPI_Mode_Master_SS_Unused PASSED -TEST 06: SPI_Mode_Master_SS_Sw_Ctrl PASSED -TEST 07: SPI_Mode_Master_SS_Hw_Ctrl_Out PASSED -TEST 08: SPI_Mode_Master_SS_Hw_Mon_In PASSED -TEST 09: SPI_Mode_Slave_SS_Hw_Mon PASSED -TEST 10: SPI_Mode_Slave_SS_Sw_Ctrl PASSED -TEST 11: SPI_Format_Clock_Pol0_Pha0 PASSED -TEST 12: SPI_Format_Clock_Pol0_Pha1 PASSED -TEST 13: SPI_Format_Clock_Pol1_Pha0 PASSED -TEST 14: SPI_Format_Clock_Pol1_Pha1 PASSED -TEST 15: SPI_Format_Frame_TI PASSED -TEST 16: SPI_Format_Clock_Microwire NOT EXECUTED -TEST 17: SPI_Data_Bits_1 NOT EXECUTED -TEST 18: SPI_Data_Bits_2 NOT EXECUTED -TEST 19: SPI_Data_Bits_3 NOT EXECUTED -TEST 20: SPI_Data_Bits_4 NOT EXECUTED -TEST 21: SPI_Data_Bits_5 NOT EXECUTED -TEST 22: SPI_Data_Bits_6 NOT EXECUTED -TEST 23: SPI_Data_Bits_7 NOT EXECUTED -TEST 24: SPI_Data_Bits_8 PASSED -TEST 25: SPI_Data_Bits_9 NOT EXECUTED -TEST 26: SPI_Data_Bits_10 NOT EXECUTED -TEST 27: SPI_Data_Bits_11 NOT EXECUTED -TEST 28: SPI_Data_Bits_12 NOT EXECUTED -TEST 29: SPI_Data_Bits_13 NOT EXECUTED -TEST 30: SPI_Data_Bits_14 NOT EXECUTED -TEST 31: SPI_Data_Bits_15 NOT EXECUTED -TEST 32: SPI_Data_Bits_16 PASSED -TEST 33: SPI_Data_Bits_17 NOT EXECUTED -TEST 34: SPI_Data_Bits_18 NOT EXECUTED -TEST 35: SPI_Data_Bits_19 NOT EXECUTED -TEST 36: SPI_Data_Bits_20 NOT EXECUTED -TEST 37: SPI_Data_Bits_21 NOT EXECUTED -TEST 38: SPI_Data_Bits_22 NOT EXECUTED -TEST 39: SPI_Data_Bits_23 NOT EXECUTED -TEST 40: SPI_Data_Bits_24 NOT EXECUTED -TEST 41: SPI_Data_Bits_25 NOT EXECUTED -TEST 42: SPI_Data_Bits_26 NOT EXECUTED -TEST 43: SPI_Data_Bits_27 NOT EXECUTED -TEST 44: SPI_Data_Bits_28 NOT EXECUTED -TEST 45: SPI_Data_Bits_29 NOT EXECUTED -TEST 46: SPI_Data_Bits_30 NOT EXECUTED -TEST 47: SPI_Data_Bits_31 NOT EXECUTED -TEST 48: SPI_Data_Bits_32 NOT EXECUTED -TEST 49: SPI_Bit_Order_MSB_LSB PASSED -TEST 50: SPI_Bit_Order_LSB_MSB PASSED -TEST 51: SPI_Bus_Speed_Min PASSED -TEST 52: SPI_Bus_Speed_Max - DV_SPI.c (3524): [WARNING] At requested bus speed of 10000000 bps, effective bus speed is 6477809 bps +TEST 05: ETH_MAC_MacAddress PASSED +TEST 06: ETH_MAC_SetBusSpeed + DV_ETH.c (445): [WARNING] Link speed 1G is not supported PASSED -TEST 53: SPI_Number_Of_Items PASSED -TEST 54: SPI_Abort PASSED -TEST 55: SPI_DataLost PASSED -TEST 56: SPI_ModeFault PASSED - -Test Summary: 56 Tests, 25 Passed, 0 Failed. +TEST 07: ETH_MAC_Config_Mode PASSED +TEST 08: ETH_MAC_Config_CommonParams PASSED +TEST 09: ETH_MAC_Control_Filtering PASSED +TEST 10: ETH_MAC_SetAddressFilter PASSED +TEST 11: ETH_MAC_VLAN_Filter + DV_ETH.c (910): [WARNING] Received non VLAN tagged frame + PASSED +TEST 12: ETH_MAC_SignalEvent PASSED +TEST 13: ETH_MAC_PTP_ControlTimer + DV_ETH.c (1412): [WARNING] Precision Time Protocol is not supported + NOT EXECUTED +TEST 14: ETH_MAC_CheckInvalidInit PASSED +TEST 15: ETH_PHY_GetVersion + DV_ETH.c (1018): [INFO] API version 2.2, Driver version 1.3 + PASSED +TEST 16: ETH_PHY_Initialization PASSED +TEST 17: ETH_PHY_PowerControl + DV_ETH.c (1114): [WARNING] Low power is not supported + DV_ETH.c (1131): [WARNING] MAC is locked when PHY power is off + PASSED +TEST 18: ETH_PHY_Config PASSED +TEST 19: ETH_PHY_CheckInvalidInit PASSED +TEST 20: ETH_Loopback_Transfer PASSED +TEST 21: ETH_Loopback_PTP + DV_ETH.c (1574): [WARNING] Precision Time Protocol is not supported + NOT EXECUTED +TEST 22: ETH_Loopback_External PASSED + +Test Summary: 22 Tests, 20 Passed, 0 Failed. Test Result: PASSED \endverbatim diff --git a/Documentation/Doxygen/src/images/driver_validation_build_type.png b/Documentation/Doxygen/src/images/driver_validation_build_type.png new file mode 100644 index 0000000..d9adac3 Binary files /dev/null and b/Documentation/Doxygen/src/images/driver_validation_build_type.png differ diff --git a/Documentation/Doxygen/src/images/driver_validation_new_sol_create.png b/Documentation/Doxygen/src/images/driver_validation_new_sol_create.png new file mode 100644 index 0000000..501a5df Binary files /dev/null and b/Documentation/Doxygen/src/images/driver_validation_new_sol_create.png differ diff --git a/Documentation/Doxygen/src/images/driver_validation_new_sol_layer.png b/Documentation/Doxygen/src/images/driver_validation_new_sol_layer.png new file mode 100644 index 0000000..7497d16 Binary files /dev/null and b/Documentation/Doxygen/src/images/driver_validation_new_sol_layer.png differ diff --git a/Documentation/Doxygen/src/images/driver_validation_new_sol_template.png b/Documentation/Doxygen/src/images/driver_validation_new_sol_template.png new file mode 100644 index 0000000..f7e94cf Binary files /dev/null and b/Documentation/Doxygen/src/images/driver_validation_new_sol_template.png differ diff --git a/README.md b/README.md index b995571..1758f37 100644 --- a/README.md +++ b/README.md @@ -33,10 +33,10 @@ Basic tests: | --------------------- | --------------------------------------------------------- | | [`Boards`](./Boards/) | Driver Validation examples for various boards | | [`Config`](./Config/) | Configuration files for the Driver Validation framework | -| [`Documentation`](./Documentation) | Placeholder for the offline documentation in the pack | -| [`DoxyGen`](./Doxygen) | Source of the documentation | +| [`Documentation`](./Documentation) | Placeholder and source for the offline documentation in the pack | | [`Include`](./Include) | Header files for Driver Validation components | | [`Source`](./Source) | Source files for Driver Validation components | +| [`Template`](./Template) | Driver Validation application template | | [`Tools`](./Tools) | Various Server implementations for extensive testing | | [`ARM.CMSIS-Driver_Validation.pdsc`](./ARM.CMSIS-Driver_Validation.pdsc) | Open-CMSIS-Pack description file | | [`gen_pack.sh`](./gen_pack.sh) | Open-CMSIS-Pack generation script | @@ -55,7 +55,7 @@ Folder [`Boards`](./Boards/) contains example projects that show how to use the - Verify that following tools are installed on the PC: - git bash (e.g. for Windows: https://gitforwindows.org/) - ZIP archive creation utility (e.g. [7-Zip](http://www.7-zip.org/download.html)) - - Doxygen version 1.9.2 (https://sourceforge.net/projects/doxygen/files/rel-1.9.2/) + - Doxygen version 1.13.2 (https://sourceforge.net/projects/doxygen/files/rel-1.13.2/) - Checkout this repository. For example in git bash with: ```git clone https://github.com/ARM-Software/CMSIS-Driver_Validation``` - In the local repository folder execute `./gen_pack.sh` in the bash shell. diff --git a/Template/CMSIS_DV.cproject.yml b/Template/CMSIS_DV.cproject.yml new file mode 100644 index 0000000..2cecd88 --- /dev/null +++ b/Template/CMSIS_DV.cproject.yml @@ -0,0 +1,74 @@ +project: + description: CMSIS Driver Validation application + + # List of packs used in the project. + packs: + - pack: ARM::CMSIS@^6.2.0 + - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::CMSIS-Driver_Validation@^3.1.0-0 + - pack: ARM::CMSIS-RTX@^5.9.0 + + # List of connections required or provided by the project. + connections: + - connect: Driver Validation + provides: + - CMSIS-RTOS2 + consumes: + - STDOUT + + # List of source groups and files. + groups: + - group: Documentation + files: + - file: README.md + - group: Source Files + files: + - file: app_main.c + + # List of components used by the application. + components: + - component: CMSIS:OS Tick:SysTick + - component: CMSIS:RTOS2:Keil RTX5&Source + - component: CMSIS Driver Validation:Framework + - component: CMSIS Driver Validation:CAN + for-context: + - .CAN + - component: CMSIS Driver Validation:Ethernet + for-context: + - .Ethernet + - component: CMSIS Driver Validation:GPIO + for-context: + - .GPIO + - component: CMSIS Driver Validation:I2C + for-context: + - .I2C + - component: CMSIS Driver Validation:MCI + for-context: + - .MCI + - component: CMSIS Driver Validation:SPI + for-context: + - .SPI + - component: CMSIS Driver Validation:USART + for-context: + - .USART + - component: CMSIS Driver Validation:USB Device + for-context: + - .USB_Device + - component: CMSIS Driver Validation:USB Host + for-context: + - .USB_Host + - component: CMSIS Driver Validation:WiFi + for-context: + - .WiFi + + # List of layers. + layers: + - layer: $Board-Layer$ + type: Board + + # List of executable file formats to be generated. + output: + type: + - elf + - hex + - map diff --git a/Template/CMSIS_DV.csolution.yml b/Template/CMSIS_DV.csolution.yml new file mode 100644 index 0000000..e578d4d --- /dev/null +++ b/Template/CMSIS_DV.csolution.yml @@ -0,0 +1,63 @@ +solution: + description: CMSIS Driver Validation application + created-for: CMSIS-Toolbox@2.11.0 + cdefault: + + # List of tested compilers that can be selected + select-compiler: + - compiler: AC6 + + # Selected compiler + compiler: AC6 + + # List of miscellaneous tool-specific controls + misc: + - for-compiler: AC6 # GDB requires DWARF 5, remove when using uVision Debugger + C-CPP: + - -gdwarf-5 + ASM: + - -gdwarf-5 + + # List different hardware targets that are used to deploy the solution. + target-types: + # - type: + # board: + # variables: + # - Board-Layer: .clayer.yml + + # List of different build configurations. + build-types: + - type: CAN + debug: on + optimize: balanced + - type: Ethernet + debug: on + optimize: balanced + - type: GPIO + debug: on + optimize: balanced + - type: I2C + debug: on + optimize: balanced + - type: MCI + debug: on + optimize: balanced + - type: SPI + debug: on + optimize: balanced + - type: USART + debug: on + optimize: balanced + - type: USB_Device + debug: on + optimize: balanced + - type: USB_Host + debug: on + optimize: balanced + - type: WiFi + debug: on + optimize: balanced + + # List related projects. + projects: + - project: CMSIS_DV.cproject.yml diff --git a/Template/README.md b/Template/README.md new file mode 100644 index 0000000..30f3e08 --- /dev/null +++ b/Template/README.md @@ -0,0 +1,86 @@ +# CMSIS-Driver Validation Template + +This folder provides a **CMSIS-Driver Validation template**, designed to validate CMSIS-Drivers in a **hardware-agnostic** way. +It leverages the [CMSIS-Toolbox Reference Applications](https://open-cmsis-pack.github.io/cmsis-toolbox/ReferenceApplications/) and requires only a board support layer with drivers for the target hardware. + +> **Note:** WiFi drivers for WiFi Shields require also [**WiFi shield layer**](https://github.com/ARM-software/CMSIS-Driver/tree/main/Shield/WiFi) (see example for WiFi driver validation). +> **Note:** Some board support layers do not have NSS pin for SPI configured for SPI mode so it might be necessary to configure NSS pin to respective SPI in the board layer (see example for SPI driver validation). + +--- + +## Driver Selection and Configuration + +To select a driver for testing, use the **Build Type** option in the **CMSIS_DV solution**. +> **Note:** Only one driver can be selected at a time. + +### Supported Drivers + +- CAN +- **Ethernet** +- **GPIO** +- I2C +- MCI +- **SPI** +- **USART** +- USB_Device +- USB_Host +- **WiFi** + +> **Note:** Drivers shown in **bold** in the above list provide extensive driver validation. + +### Configuration Files + +Each driver includes a dedicated configuration file: + +| Driver | Config File | +|-------------|------------------------| +| CAN | `DV_CAN_Config.h` | +| Ethernet | `DV_ETH_Config.h` | +| GPIO | `DV_GPIO_Config.h` | +| I2C | `DV_I2C_Config.h` | +| MCI | `DV_MCI_Config.h` | +| SPI | `DV_SPI_Config.h` | +| USART | `DV_USART_Config.h` | +| USB_Device | `DV_USBD_Config.h` | +| USB_Host | `DV_USBH_Config.h` | +| WiFi | `DV_WiFi_Config.h` | + +--- + +## Documentation + +Detailed validation documentation for each driver: + +- [CAN](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__can.html) +- [Ethernet](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__eth.html) +- [GPIO](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__gpio.html) +- [I2C](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__i2c.html) +- [MCI](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__mci.html) +- [SPI](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__spi.html) +- [USART](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__usart.html) +- [USB_Device](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__usbd.html) +- [USB_Host](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__usbh.html) +- [WiFi](https://arm-software.github.io/CMSIS-Driver_Validation/latest/group__dv__wifi.html) + +--- + +## Usage Instructions + +Follow these steps to run the validation tests: + +1. In the **CMSIS** extension, click **Create a New Solution**. +2. Select the **Target Board**. +3. Under **Templates, Reference Applications, and Examples**, select **Driver Validation (CMSIS-Driver Validation application)**. +4. Choose **Solution Base Folder**, click **Create**. +5. Select the **Board Layer** that provides **required CMSIS Driver**, click **OK**. +6. In the **Manage Solution**, under **Build Type** select desired Driver for validation, click **Save**. +7. Configure the Driver Tests in appropriate **DV_..._Config.h** file. +8. Setup the required hardware +9. Build and Run the application + +For more details, see [**Setup**](https://arm-software.github.io/CMSIS-Driver_Validation/latest/setup.html) documentation section. + +> **Note:** validation of **SPI** and **USART** drivers requires **SPI_Server** or **USART_Server**. +> **Note:** validation of **GPIO** driver requires **resistor between test pins**. +> **Note:** validation of **WiFi** driver requires **SockServer running on a Windows PC** connected to the same network as WiFi will connect to. + diff --git a/Template/RTE/CMSIS/RTX_Config.c b/Template/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/Template/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Template/RTE/CMSIS/RTX_Config.c.base@5.2.0 b/Template/RTE/CMSIS/RTX_Config.c.base@5.2.0 new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/Template/RTE/CMSIS/RTX_Config.c.base@5.2.0 @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Template/RTE/CMSIS/RTX_Config.h b/Template/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..3c4b14e --- /dev/null +++ b/Template/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 1 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Unprivileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Template/RTE/CMSIS/RTX_Config.h.base@5.6.0 b/Template/RTE/CMSIS/RTX_Config.h.base@5.6.0 new file mode 100644 index 0000000..fe0c57b --- /dev/null +++ b/Template/RTE/CMSIS/RTX_Config.h.base@5.6.0 @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Unprivileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 0 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_CAN_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_CAN_Config.h new file mode 100644 index 0000000..5b8a337 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_CAN_Config.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.1.0 + * + * Project: CMSIS-Driver Validation + * Title: Controller Area Network (CAN) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_CAN_CONFIG_H_ +#define DV_CAN_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// CAN +// Controller Area Network (CAN) driver validation configuration +// Driver_CAN# <0-255> +// Choose the Driver_CAN# instance to test. +// For example to test Driver_CAN0 select 0. +#define DRV_CAN 0 +// CAN bitrates +// Set the CAN bitrates (kbit/s) +// Value zero is ignored +// CAN bitrate 1 +#define CAN_BR_1 125 +// CAN bitrate 2 +#define CAN_BR_2 250 +// CAN bitrate 3 +#define CAN_BR_3 500 +// CAN bitrate 4 +#define CAN_BR_4 1000 +// CAN bitrate 5 +#define CAN_BR_5 0 +// CAN bitrate 6 +#define CAN_BR_6 0 +// +// Ratio data/arbitration bitrate +// Set the ratio between data and arbitration bitrate for CAN FD +#define CAN_DATA_ARB_RATIO 8 +// Percentual trigger for bitrate test +// Set the minimum margin between measured and expected bitrates (%) +#define MIN_BITRATE 10 +// Transfer timeout +// Set the transfer timeout (ms) +#define CAN_TRANSFER_TIMEOUT 1000 +// Tests +// Enable / disable tests. +// CAN_GetCapabilities +#define CAN_GETCAPABILITIES_EN 1 +// CAN_Initialization +#define CAN_INITIALIZATION_EN 1 +// CAN_PowerControl +#define CAN_POWERCONTROL_EN 1 +// CAN_Loopback_CheckBitrate +#define CAN_LOOPBACK_CHECK_BR_EN 1 +// CAN_Loopback_CheckBitrateFD +#define CAN_LOOPBACK_CHECK_BR_FD_EN 1 +// CAN_Loopback_Transfer +#define CAN_LOOPBACK_TRANSFER_EN 1 +// CAN_Loopback_TransferFD +#define CAN_LOOPBACK_TRANSFER_FD_EN 1 +// CAN_CheckInvalidInit +#define CAN_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_CAN_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_CAN_Config.h.base@1.1.0 b/Template/RTE/CMSIS_Driver_Validation/DV_CAN_Config.h.base@1.1.0 new file mode 100644 index 0000000..5b8a337 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_CAN_Config.h.base@1.1.0 @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.1.0 + * + * Project: CMSIS-Driver Validation + * Title: Controller Area Network (CAN) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_CAN_CONFIG_H_ +#define DV_CAN_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// CAN +// Controller Area Network (CAN) driver validation configuration +// Driver_CAN# <0-255> +// Choose the Driver_CAN# instance to test. +// For example to test Driver_CAN0 select 0. +#define DRV_CAN 0 +// CAN bitrates +// Set the CAN bitrates (kbit/s) +// Value zero is ignored +// CAN bitrate 1 +#define CAN_BR_1 125 +// CAN bitrate 2 +#define CAN_BR_2 250 +// CAN bitrate 3 +#define CAN_BR_3 500 +// CAN bitrate 4 +#define CAN_BR_4 1000 +// CAN bitrate 5 +#define CAN_BR_5 0 +// CAN bitrate 6 +#define CAN_BR_6 0 +// +// Ratio data/arbitration bitrate +// Set the ratio between data and arbitration bitrate for CAN FD +#define CAN_DATA_ARB_RATIO 8 +// Percentual trigger for bitrate test +// Set the minimum margin between measured and expected bitrates (%) +#define MIN_BITRATE 10 +// Transfer timeout +// Set the transfer timeout (ms) +#define CAN_TRANSFER_TIMEOUT 1000 +// Tests +// Enable / disable tests. +// CAN_GetCapabilities +#define CAN_GETCAPABILITIES_EN 1 +// CAN_Initialization +#define CAN_INITIALIZATION_EN 1 +// CAN_PowerControl +#define CAN_POWERCONTROL_EN 1 +// CAN_Loopback_CheckBitrate +#define CAN_LOOPBACK_CHECK_BR_EN 1 +// CAN_Loopback_CheckBitrateFD +#define CAN_LOOPBACK_CHECK_BR_FD_EN 1 +// CAN_Loopback_Transfer +#define CAN_LOOPBACK_TRANSFER_EN 1 +// CAN_Loopback_TransferFD +#define CAN_LOOPBACK_TRANSFER_FD_EN 1 +// CAN_CheckInvalidInit +#define CAN_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_CAN_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_ETH_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_ETH_Config.h new file mode 100644 index 0000000..dd5ec00 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_ETH_Config.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V2.1.0 + * + * Project: CMSIS-Driver Validation + * Title: Ethernet (ETH) driver validation configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_ETH_CONFIG_H_ +#define DV_ETH_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Ethernet +// Ethernet (ETH) driver validation configuration +// Driver_ETH_MAC# <0-255> +// Choose the Driver_ETH_MAC# instance to test. +// For example to test Driver_ETH_MAC0 select 0. +#define DRV_ETH 0 +// Link timeout +// Set the Ethernet link timeout (ms) +#define ETH_LINK_TIMEOUT 3000 +// Transfer timeout +// Set the transfer timeout (ms) +#define ETH_TRANSFER_TIMEOUT 100 +// Time duration for PTP Control Time +// Set time duration for Control Time tests (ms) +#define ETH_PTP_TIME_REF 1000 +// Tolerance for PTP Control Time +// Set tolerance for Control Time tests (ns) +#define ETH_PTP_TOLERANCE 0 +// Tests +// Enable / disable tests. +// ETH_MAC_GetVersion +#define ETH_MAC_GET_VERSION_EN 1 +// ETH_MAC_GetCapabilities +#define ETH_MAC_GET_CAPABILITIES_EN 1 +// ETH_MAC_Initialization +#define ETH_MAC_INITIALIZATION_EN 1 +// ETH_MAC_PowerControl +#define ETH_MAC_POWER_CONTROL_EN 1 +// ETH_MAC_MacAddress +#define ETH_MAC_MAC_ADDRESS_EN 1 +// ETH_MAC_SetBusSpeed +#define ETH_MAC_SET_BUS_SPEED_EN 1 +// ETH_MAC_Config_Mode +#define ETH_MAC_CONFIG_MODE_EN 1 +// ETH_MAC_Config_CommonParams +#define ETH_MAC_CONFIG_COMMON_PARAMS_EN 1 +// ETH_MAC_Control_Filtering +#define ETH_MAC_CONTROL_FILTERING_EN 1 +// ETH_MAC_SetAddressFilter +#define ETH_MAC_SET_ADDRESS_FILTER_EN 1 +// ETH_MAC_VLAN_Filter +#define ETH_MAC_VLAN_FILTER_EN 1 +// ETH_MAC_SignalEvent +#define ETH_MAC_SIGNAL_EVENT_EN 1 +// ETH_MAC_PTP_ControlTimer +#define ETH_MAC_PTP_CONTROL_TIMER_EN 1 +// ETH_MAC_CheckInvalidInit +#define ETH_MAC_CHECK_INVALID_INIT_EN 1 +// ETH_PHY_GetVersion +#define ETH_PHY_GET_VERSION_EN 1 +// ETH_PHY_Initialization +#define ETH_PHY_INITIALIZATION_EN 1 +// ETH_PHY_PowerControl +#define ETH_PHY_POWER_CONTROL_EN 1 +// ETH_PHY_Config +#define ETH_PHY_CONFIG_EN 1 +// ETH_PHY_CheckInvalidInit +#define ETH_PHY_CHECK_INVALID_INIT_EN 1 +// ETH_Loopback_Transfer +#define ETH_LOOPBACK_TRANSFER_EN 1 +// ETH_Loopback_PTP +#define ETH_LOOPBACK_PTP_EN 1 +// ETH_Loopback_External +#define ETH_LOOPBACK_EXTERNAL_EN 1 +// +// + +#endif /* DV_ETH_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_ETH_Config.h.base@2.1.0 b/Template/RTE/CMSIS_Driver_Validation/DV_ETH_Config.h.base@2.1.0 new file mode 100644 index 0000000..eff7371 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_ETH_Config.h.base@2.1.0 @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V2.1.0 + * + * Project: CMSIS-Driver Validation + * Title: Ethernet (ETH) driver validation configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_ETH_CONFIG_H_ +#define DV_ETH_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Ethernet +// Ethernet (ETH) driver validation configuration +// Driver_ETH_MAC# <0-255> +// Choose the Driver_ETH_MAC# instance to test. +// For example to test Driver_ETH_MAC0 select 0. +#define DRV_ETH 0 +// Link timeout +// Set the Ethernet link timeout (ms) +#define ETH_LINK_TIMEOUT 3000 +// Transfer timeout +// Set the transfer timeout (ms) +#define ETH_TRANSFER_TIMEOUT 100 +// Time duration for PTP Control Time +// Set time duration for Control Time tests (ms) +#define ETH_PTP_TIME_REF 1000 +// Tolerance for PTP Control Time +// Set tolerance for Control Time tests (ns) +#define ETH_PTP_TOLERANCE 0 +// Tests +// Enable / disable tests. +// ETH_MAC_GetVersion +#define ETH_MAC_GET_VERSION_EN 1 +// ETH_MAC_GetCapabilities +#define ETH_MAC_GET_CAPABILITIES_EN 1 +// ETH_MAC_Initialization +#define ETH_MAC_INITIALIZATION_EN 1 +// ETH_MAC_PowerControl +#define ETH_MAC_POWER_CONTROL_EN 1 +// ETH_MAC_MacAddress +#define ETH_MAC_MAC_ADDRESS_EN 1 +// ETH_MAC_SetBusSpeed +#define ETH_MAC_SET_BUS_SPEED_EN 1 +// ETH_MAC_Config_Mode +#define ETH_MAC_CONFIG_MODE_EN 1 +// ETH_MAC_Config_CommonParams +#define ETH_MAC_CONFIG_COMMON_PARAMS_EN 1 +// ETH_MAC_Control_Filtering +#define ETH_MAC_CONTROL_FILTERING_EN 1 +// ETH_MAC_SetAddressFilter +#define ETH_MAC_SET_ADDRESS_FILTER_EN 1 +// ETH_MAC_VLAN_Filter +#define ETH_MAC_VLAN_FILTER_EN 1 +// ETH_MAC_SignalEvent +#define ETH_MAC_SIGNAL_EVENT_EN 1 +// ETH_MAC_PTP_ControlTimer +#define ETH_MAC_PTP_CONTROL_TIMER_EN 1 +// ETH_MAC_CheckInvalidInit +#define ETH_MAC_CHECK_INVALID_INIT_EN 1 +// ETH_PHY_GetVersion +#define ETH_PHY_GET_VERSION_EN 1 +// ETH_PHY_Initialization +#define ETH_PHY_INITIALIZATION_EN 1 +// ETH_PHY_PowerControl +#define ETH_PHY_POWER_CONTROL_EN 1 +// ETH_PHY_Config +#define ETH_PHY_CONFIG_EN 1 +// ETH_PHY_CheckInvalidInit +#define ETH_PHY_CHECK_INVALID_INIT_EN 1 +// ETH_Loopback_Transfer +#define ETH_LOOPBACK_TRANSFER_EN 1 +// ETH_Loopback_PTP +#define ETH_LOOPBACK_PTP_EN 1 +// ETH_Loopback_External +#define ETH_LOOPBACK_EXTERNAL_EN 1 +// +// + +#endif /* DV_ETH_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_GPIO_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_GPIO_Config.h new file mode 100644 index 0000000..d3f5cc9 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_GPIO_Config.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2023-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: General-Purpose Input/Output (GPIO) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_GPIO_CONFIG_H_ +#define DV_GPIO_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// GPIO +// General-Purpose Input/Output (GPIO) driver validation configuration +// Driver_GPIO# <0-255> +// Choose the Driver_GPIO# instance to test. +// For example to test Driver_GPIO0 select 0. +// Configuration +// Pins and Tests configuration. +// Pin Under Test <0-255> +// Select pin to be tested. +// This pin should not have any external resistors or any external devices connected to it. +// Auxiliary Pin +// Select Auxiliary Pin with serial low resistance resistor connected to Pin Under Test. +// Suggested resistance of this serial resistor is around 1 kOhm. +// This pin should not have any external resistors or any external devices connected to it. +// +// Tests +// Enable / disable tests. +// GPIO_Setup +// Enable / disable Setup function tests. +// GPIO_SetDirection +// Enable / disable SetDirection function tests. +// GPIO_SetOutputMode +// Enable / disable SetOutputMode function tests. +// GPIO_SetPullResistor +// Enable / disable SetPullResistor function tests. +// GPIO_SetEventTrigger +// Enable / disable SetEventTrigger function tests. +// GPIO_SetOutput +// Enable / disable SetOutput function tests. +// GPIO_GetInput +// Enable / disable GetInput function tests. +// +// + +#define DRV_GPIO 0 +#define GPIO_CFG_PIN_UNDER_TEST 0 +#define GPIO_CFG_PIN_AUX 0 +#define GPIO_TC_SETUP_EN 1 +#define GPIO_TC_SET_DIRECTION_EN 1 +#define GPIO_TC_SET_OUTPUT_MODE_EN 1 +#define GPIO_TC_SET_PULL_RESISTOR_EN 1 +#define GPIO_TC_SET_EVENT_TRIGGER_EN 1 +#define GPIO_TC_SET_OUTPUT_EN 1 +#define GPIO_TC_GET_INPUT_EN 1 + +#endif /* DV_GPIO_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_GPIO_Config.h.base@1.0.0 b/Template/RTE/CMSIS_Driver_Validation/DV_GPIO_Config.h.base@1.0.0 new file mode 100644 index 0000000..d3f5cc9 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_GPIO_Config.h.base@1.0.0 @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2023-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: General-Purpose Input/Output (GPIO) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_GPIO_CONFIG_H_ +#define DV_GPIO_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// GPIO +// General-Purpose Input/Output (GPIO) driver validation configuration +// Driver_GPIO# <0-255> +// Choose the Driver_GPIO# instance to test. +// For example to test Driver_GPIO0 select 0. +// Configuration +// Pins and Tests configuration. +// Pin Under Test <0-255> +// Select pin to be tested. +// This pin should not have any external resistors or any external devices connected to it. +// Auxiliary Pin +// Select Auxiliary Pin with serial low resistance resistor connected to Pin Under Test. +// Suggested resistance of this serial resistor is around 1 kOhm. +// This pin should not have any external resistors or any external devices connected to it. +// +// Tests +// Enable / disable tests. +// GPIO_Setup +// Enable / disable Setup function tests. +// GPIO_SetDirection +// Enable / disable SetDirection function tests. +// GPIO_SetOutputMode +// Enable / disable SetOutputMode function tests. +// GPIO_SetPullResistor +// Enable / disable SetPullResistor function tests. +// GPIO_SetEventTrigger +// Enable / disable SetEventTrigger function tests. +// GPIO_SetOutput +// Enable / disable SetOutput function tests. +// GPIO_GetInput +// Enable / disable GetInput function tests. +// +// + +#define DRV_GPIO 0 +#define GPIO_CFG_PIN_UNDER_TEST 0 +#define GPIO_CFG_PIN_AUX 0 +#define GPIO_TC_SETUP_EN 1 +#define GPIO_TC_SET_DIRECTION_EN 1 +#define GPIO_TC_SET_OUTPUT_MODE_EN 1 +#define GPIO_TC_SET_PULL_RESISTOR_EN 1 +#define GPIO_TC_SET_EVENT_TRIGGER_EN 1 +#define GPIO_TC_SET_OUTPUT_EN 1 +#define GPIO_TC_GET_INPUT_EN 1 + +#endif /* DV_GPIO_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_I2C_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_I2C_Config.h new file mode 100644 index 0000000..cdbce90 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_I2C_Config.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Inter-Integrated Circuit (I2C) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_I2C_CONFIG_H_ +#define DV_I2C_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// I2C +// Inter-Integrated Circuit (I2C) driver validation configuration +// Driver_I2C# <0-255> +// Choose the Driver_I2C# instance to test. +// For example to test Driver_I2C0 select 0. +#define DRV_I2C 1 +// Tests +// Enable / disable tests. +// I2C_GetCapabilities +#define I2C_GETCAPABILITIES_EN 1 +// I2C_Initialization +#define I2C_INITIALIZATION_EN 1 +// I2C_PowerControl +#define I2C_POWERCONTROL_EN 1 +// I2C_SetBusSpeed +#define I2C_SETBUSSPEED_EN 1 +// I2C_SetOwnAddress +#define I2C_SETOWNADDRESS_EN 1 +// I2C_BusClear +#define I2C_BUSCLEAR_EN 1 +// I2C_AbortTransfer +#define I2C_ABORTTRANSFER_EN 1 +// I2C_CheckInvalidInit +#define I2C_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_I2C_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_I2C_Config.h.base@1.0.0 b/Template/RTE/CMSIS_Driver_Validation/DV_I2C_Config.h.base@1.0.0 new file mode 100644 index 0000000..cdbce90 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_I2C_Config.h.base@1.0.0 @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Inter-Integrated Circuit (I2C) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_I2C_CONFIG_H_ +#define DV_I2C_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// I2C +// Inter-Integrated Circuit (I2C) driver validation configuration +// Driver_I2C# <0-255> +// Choose the Driver_I2C# instance to test. +// For example to test Driver_I2C0 select 0. +#define DRV_I2C 1 +// Tests +// Enable / disable tests. +// I2C_GetCapabilities +#define I2C_GETCAPABILITIES_EN 1 +// I2C_Initialization +#define I2C_INITIALIZATION_EN 1 +// I2C_PowerControl +#define I2C_POWERCONTROL_EN 1 +// I2C_SetBusSpeed +#define I2C_SETBUSSPEED_EN 1 +// I2C_SetOwnAddress +#define I2C_SETOWNADDRESS_EN 1 +// I2C_BusClear +#define I2C_BUSCLEAR_EN 1 +// I2C_AbortTransfer +#define I2C_ABORTTRANSFER_EN 1 +// I2C_CheckInvalidInit +#define I2C_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_I2C_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_MCI_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_MCI_Config.h new file mode 100644 index 0000000..2f3cbd2 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_MCI_Config.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Memory Card Interface (MCI) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_MCI_CONFIG_H_ +#define DV_MCI_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// MCI +// Memory Card Interface (MCI) driver validation configuration +// Driver_MCI# <0-255> +// Choose the Driver_MCI# instance to test. +// For example to test Driver_MCI0 select 0. +#define DRV_MCI 0 +// Tests +// Enable / disable tests. +// MCI_GetCapabilities +#define MCI_GETCAPABILITIES_EN 1 +// MCI_Initialization +#define MCI_INITIALIZATION_EN 1 +// MCI_PowerControl +#define MCI_POWERCONTROL_EN 1 +// MCI_SetBusSpeedMode +#define MCI_SETBUSSPEEDMODE_EN 1 +// MCI_Config_DataWidth +#define MCI_CONFIG_DATAWIDTH_EN 1 +// MCI_Config_CmdLineMode +#define MCI_CONFIG_CMDLINEMODE_EN 1 +// MCI_Config_DriverStrength +#define MCI_CONFIG_DRIVERSTRENGTH_EN 1 +// MCI_CheckInvalidInit +#define MCI_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_MCI_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_MCI_Config.h.base@1.0.0 b/Template/RTE/CMSIS_Driver_Validation/DV_MCI_Config.h.base@1.0.0 new file mode 100644 index 0000000..2f3cbd2 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_MCI_Config.h.base@1.0.0 @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Memory Card Interface (MCI) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_MCI_CONFIG_H_ +#define DV_MCI_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// MCI +// Memory Card Interface (MCI) driver validation configuration +// Driver_MCI# <0-255> +// Choose the Driver_MCI# instance to test. +// For example to test Driver_MCI0 select 0. +#define DRV_MCI 0 +// Tests +// Enable / disable tests. +// MCI_GetCapabilities +#define MCI_GETCAPABILITIES_EN 1 +// MCI_Initialization +#define MCI_INITIALIZATION_EN 1 +// MCI_PowerControl +#define MCI_POWERCONTROL_EN 1 +// MCI_SetBusSpeedMode +#define MCI_SETBUSSPEEDMODE_EN 1 +// MCI_Config_DataWidth +#define MCI_CONFIG_DATAWIDTH_EN 1 +// MCI_Config_CmdLineMode +#define MCI_CONFIG_CMDLINEMODE_EN 1 +// MCI_Config_DriverStrength +#define MCI_CONFIG_DRIVERSTRENGTH_EN 1 +// MCI_CheckInvalidInit +#define MCI_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_MCI_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_SPI_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_SPI_Config.h new file mode 100644 index 0000000..d51baf1 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_SPI_Config.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.1.0 + * + * Project: CMSIS-Driver Validation + * Title: Serial Peripheral Interface Bus (SPI) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_SPI_CONFIG_H_ +#define DV_SPI_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// SPI +// Serial Peripheral Interface Bus (SPI) driver validation configuration +// Driver_SPI# <0-255> +// Choose the Driver_SPI# instance to test. +// For example to test Driver_SPI0 select 0. +// Configuration +// Test Mode, SPI Server and Tests configuration. +// Test Mode +// Select test mode: Loopback or SPI Server. +// For Loopback test mode connect the MISO and MOSI lines directly. +// Loopback test mode is used for basic driver functionality testing before using SPI Server test mode. +// For SPI Server test mode connect: MISO, MOSI, SCK, SS and GND lines to the same lines on the SPI Server. +// SPI Server test mode is used for extensive driver functionality testing. +// <0=> Loopback +// <1=> SPI Server +// SPI Server +// SPI Server configuration. +// Specifies the communication settings at which Driver Validation communicates with the SPI Server. +// Fixed settings: +// Mode: Master +// Clock / Frame Format: Clock Polarity 0, Clock Phase 0 +// Data Bits: 8 +// Bit Order: MSB to LSB +// Slave Select +// Select mode of driving Slave Select line. +// <1=> Software Controlled +// <2=> Hardware Controlled +// Bus Speed <10000-1000000000> +// Select bus speed setting (in bps) used by the SPI Server. +// +// Tests +// Tests configuration +// Default settings +// Default settings used for tests. +// Slave Select +// Select default mode of driving Slave Select line in tests. +// This setting is used for all tests except the Data Exchange: Mode tests. +// <0=> Not used +// <1=> Software Controlled +// <2=> Hardware Controlled +// Clock / Frame Format +// Select default clock / frame format setting for tests. +// This setting is used for all tests except the Data Exchange: Clock / Frame Format tests. +// <0=> Clock Polarity 0, Clock Phase 0 +// <1=> Clock Polarity 0, Clock Phase 1 +// <2=> Clock Polarity 1, Clock Phase 0 +// <3=> Clock Polarity 1, Clock Phase 1 +// <4=> Texas Instruments Frame Format +// <5=> National Semiconductor Microwire Frame Format +// Data Bits <1-32> +// Select default data bits setting for tests. +// This setting is used for all tests except the Data Exchange: Data Bits tests. +// Bit Order <0=> MSB to LSB <1=> LSB to MSB +// Select default bit order setting for tests. +// This setting is used for all tests except the Data Exchange: Bit Order tests. +// Bus Speed <10000-1000000000> +// Select default bus speed setting for tests. +// This setting is used for all tests except the Data Exchange: Bus Speed tests. +// Number of Items <1-1024> +// Select default number of data items for tests. +// This setting is used for all tests except the Data Exchange: Other: SPI_Number_Of_Items tests. +// +// Bus Speed +// Bus speed tests configuration. +// Minimum Bus Speed <10000-1000000000> +// Select minimum bus speed setting (in bps). +// This setting is used only in SPI_Bus_Speed_Min test function. +// Maximum Bus Speed <10000-1000000000> +// Select maximum bus speed setting (in bps). +// This setting is used only in SPI_Bus_Speed_Max test function. +// +// Number of Items +// Number of items test configuration. +// This setting is used only in SPI_Number_Of_Items test function. +// (Value 0 means setting is not used) +// Number of Items 1 <0-1024> +// Number of Items 2 <0-1024> +// Number of Items 3 <0-1024> +// Number of Items 4 <0-1024> +// Number of Items 5 <0-1024> +// +// +// +// Tests +// Enable / disable tests. +// Driver Management +// Enable / disable driver management tests (functions: GetVersion, GetCapabilities, Initialize, Uninitialize, PowerControl). +// SPI_GetVersion +// Enable / disable GetVersion function tests. +// SPI_GetCapabilities +// Enable / disable GetCapabilities function tests. +// SPI_Initialize_Uninitialize +// Enable / disable Initialize and Uninitialize functions tests. +// SPI_PowerControl +// Enable / disable PowerControl function tests. +// +// Data Exchange +// Enable / disable data exchange tests (functions: Send, Receive, Transfer, GetDataCount, Control, GetStatus, SignalEvent). +// Mode +// Enable / disable SPI mode and Slave Select mode tests. +// (for Loopback test mode only Master mode with Slave Select not used test is supported!) +// SPI_Mode_Master_SS_Unused +// Enable / disable data exchange in Master mode with Slave Select not used test. +// SPI_Mode_Master_SS_Sw_Ctrl +// Enable / disable data exchange in Master mode with Slave Select Software Controlled test. +// SPI_Mode_Master_SS_Hw_Ctrl_Out +// Enable / disable data exchange in Master mode with Slave Select Hardware Controlled Output test. +// SPI_Mode_Master_SS_Hw_Mon_In +// Enable / disable data exchange in Master mode with Slave Select Hardware Monitored Input test. +// SPI_Mode_Slave_SS_Hw_Mon +// Enable / disable data exchange in Slave mode with Slave Select Hardware Monitored test. +// SPI_Mode_Slave_SS_Sw_Ctrl +// Enable / disable data exchange in Slave mode with Slave Select Software Controlled test. +// +// Clock / Frame Format +// Enable / disable clock / frame format tests. +// (all of these tests are supported only in SPI Server test mode!) +// SPI_Format_Clock_Pol0_Pha0 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 0 test. +// SPI_Format_Clock_Pol0_Pha1 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 1 test. +// SPI_Format_Clock_Pol1_Pha0 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 0 test. +// SPI_Format_Clock_Pol1_Pha1 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 1 test. +// SPI_Format_Frame_TI +// Enable / disable data exchange with Texas Instruments frame format test. +// SPI_Format_Frame_Microwire +// Enable / disable data exchange with National Semiconductor Microwire frame format test. +// +// Data Bits +// Enable / disable data bits tests. +// (for Loopback test mode only: 8, 16, 24, and 32 data bit tests are supported!) +// SPI_Data_Bits_1 +// Enable / disable data exchange with 1 bit per frame test. +// SPI_Data_Bits_2 +// Enable / disable data exchange with 2 bits per frame test. +// SPI_Data_Bits_3 +// Enable / disable data exchange with 3 bits per frame test. +// SPI_Data_Bits_4 +// Enable / disable data exchange with 4 bits per frame test. +// SPI_Data_Bits_5 +// Enable / disable data exchange with 5 bits per frame test. +// SPI_Data_Bits_6 +// Enable / disable data exchange with 6 bits per frame test. +// SPI_Data_Bits_7 +// Enable / disable data exchange with 7 bits per frame test. +// SPI_Data_Bits_8 +// Enable / disable data exchange with 8 bits per frame test. +// SPI_Data_Bits_9 +// Enable / disable data exchange with 9 bits per frame test. +// SPI_Data_Bits_10 +// Enable / disable data exchange with 10 bits per frame test. +// SPI_Data_Bits_11 +// Enable / disable data exchange with 11 bits per frame test. +// SPI_Data_Bits_12 +// Enable / disable data exchange with 12 bits per frame test. +// SPI_Data_Bits_13 +// Enable / disable data exchange with 13 bits per frame test. +// SPI_Data_Bits_14 +// Enable / disable data exchange with 14 bits per frame test. +// SPI_Data_Bits_15 +// Enable / disable data exchange with 15 bits per frame test. +// SPI_Data_Bits_16 +// Enable / disable data exchange with 16 bits per frame test. +// SPI_Data_Bits_17 +// Enable / disable data exchange with 17 bits per frame test. +// SPI_Data_Bits_18 +// Enable / disable data exchange with 18 bits per frame test. +// SPI_Data_Bits_19 +// Enable / disable data exchange with 19 bits per frame test. +// SPI_Data_Bits_20 +// Enable / disable data exchange with 20 bits per frame test. +// SPI_Data_Bits_21 +// Enable / disable data exchange with 21 bits per frame test. +// SPI_Data_Bits_22 +// Enable / disable data exchange with 22 bits per frame test. +// SPI_Data_Bits_23 +// Enable / disable data exchange with 23 bits per frame test. +// SPI_Data_Bits_24 +// Enable / disable data exchange with 24 bits per frame test. +// SPI_Data_Bits_25 +// Enable / disable data exchange with 25 bits per frame test. +// SPI_Data_Bits_26 +// Enable / disable data exchange with 26 bits per frame test. +// SPI_Data_Bits_27 +// Enable / disable data exchange with 27 bits per frame test. +// SPI_Data_Bits_28 +// Enable / disable data exchange with 28 bits per frame test. +// SPI_Data_Bits_29 +// Enable / disable data exchange with 29 bits per frame test. +// SPI_Data_Bits_30 +// Enable / disable data exchange with 30 bits per frame test. +// SPI_Data_Bits_31 +// Enable / disable data exchange with 31 bits per frame test. +// SPI_Data_Bits_32 +// Enable / disable data exchange with 32 bits per frame test. +// +// Bit Order +// Enable / disable bit order tests. +// (all of these tests are supported only in SPI Server test mode!) +// SPI_Bit_Order_MSB_LSB +// Enable / disable data exchange with bit order from MSB to LSB test. +// SPI_Bit_Order_LSB_MSB +// Enable / disable data exchange with bit order from LSB to MSB test. +// +// Bus Speed +// Enable / disable bus speeds tests. +// SPI_Bus_Speed_Min +// Enable / disable data exchange at minimum supported bus speed test. +// SPI_Bus_Speed_Max +// Enable / disable data exchange at maximum supported bus speed test. +// +// Other +// Enable / disable other tests. +// SPI_Number_Of_Items +// Enable / disable data exchange with different number of data items test. +// SPI_GetDataCount +// Enable / disable GetDataCount count changing during data exchange test. +// SPI_Abort +// Enable / disable data exchange Abort test. +// +// +// Event +// Enable / disable event signaling tests (function: SignalEvent). +// (all of these tests are supported only in SPI Server test mode!) +// SPI_DataLost +// Enable / disable ARM_SPI_EVENT_DATA_LOST event generation test. +// SPI_ModeFault +// Enable / disable ARM_SPI_EVENT_MODE_FAULT event generation test. +// +// +// + +#define DRV_SPI 0 +#define SPI_CFG_TEST_MODE 1 +#define SPI_CFG_SRV_SS_MODE 1 +#define SPI_CFG_SRV_BUS_SPEED 1000000 +#define SPI_CFG_SRV_CMD_TOUT 100 +#define SPI_CFG_DEF_SS_MODE 1 +#define SPI_CFG_DEF_FORMAT 0 +#define SPI_CFG_DEF_DATA_BITS 8 +#define SPI_CFG_DEF_BIT_ORDER 0 +#define SPI_CFG_DEF_BUS_SPEED 1000000 +#define SPI_CFG_DEF_NUM 512 +#define SPI_CFG_MIN_BUS_SPEED 1000000 +#define SPI_CFG_MAX_BUS_SPEED 10000000 +#define SPI_CFG_NUM1 1 +#define SPI_CFG_NUM2 31 +#define SPI_CFG_NUM3 65 +#define SPI_CFG_NUM4 1023 +#define SPI_CFG_NUM5 1024 +#define SPI_CFG_XFER_TIMEOUT 100 +#define SPI_TG_DRIVER_MANAGEMENT_EN 1 +#define SPI_TC_GET_VERSION_EN 1 +#define SPI_TC_GET_CAPABILITIES_EN 1 +#define SPI_TC_INIT_UNINIT_EN 1 +#define SPI_TC_POWER_CONTROL_EN 1 +#define SPI_TG_DATA_EXCHANGE_EN 1 +#define SPI_TG_MODE_EN 1 +#define SPI_TC_MASTER_UNUSED_EN 1 +#define SPI_TC_MASTER_SW_EN 1 +#define SPI_TC_MASTER_HW_OUT_EN 1 +#define SPI_TC_MASTER_HW_IN_EN 1 +#define SPI_TC_SLAVE_HW_EN 1 +#define SPI_TC_SLAVE_SW_EN 1 +#define SPI_TG_FORMAT_EN 1 +#define SPI_TC_FORMAT_POL0_PHA0_EN 1 +#define SPI_TC_FORMAT_POL0_PHA1_EN 1 +#define SPI_TC_FORMAT_POL1_PHA0_EN 1 +#define SPI_TC_FORMAT_POL1_PHA1_EN 1 +#define SPI_TC_FORMAT_TI_EN 1 +#define SPI_TC_FORMAT_MICROWIRE_EN 0 +#define SPI_TG_DATA_BIT_EN 1 +#define SPI_TC_DATA_BIT_EN_MASK 0x00008080 +#define SPI_TG_BIT_ORDER_EN 1 +#define SPI_TC_BIT_ORDER_MSB_LSB_EN 1 +#define SPI_TC_BIT_ORDER_LSB_MSB_EN 1 +#define SPI_TG_BUS_SPEED_EN 1 +#define SPI_TC_BUS_SPEED_MIN_EN 1 +#define SPI_TC_BUS_SPEED_MAX_EN 1 +#define SPI_TG_OTHER_EN 1 +#define SPI_TC_NUMBER_OF_ITEMS_EN 1 +#define SPI_TC_GET_DATA_COUNT_EN 1 +#define SPI_TC_ABORT_EN 1 +#define SPI_TG_EVENT_EN 1 +#define SPI_TC_DATA_LOST_EN 1 +#define SPI_TC_MODE_FAULT_EN 1 + +#endif /* DV_SPI_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_SPI_Config.h.base@1.1.0 b/Template/RTE/CMSIS_Driver_Validation/DV_SPI_Config.h.base@1.1.0 new file mode 100644 index 0000000..d51baf1 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_SPI_Config.h.base@1.1.0 @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.1.0 + * + * Project: CMSIS-Driver Validation + * Title: Serial Peripheral Interface Bus (SPI) driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_SPI_CONFIG_H_ +#define DV_SPI_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// SPI +// Serial Peripheral Interface Bus (SPI) driver validation configuration +// Driver_SPI# <0-255> +// Choose the Driver_SPI# instance to test. +// For example to test Driver_SPI0 select 0. +// Configuration +// Test Mode, SPI Server and Tests configuration. +// Test Mode +// Select test mode: Loopback or SPI Server. +// For Loopback test mode connect the MISO and MOSI lines directly. +// Loopback test mode is used for basic driver functionality testing before using SPI Server test mode. +// For SPI Server test mode connect: MISO, MOSI, SCK, SS and GND lines to the same lines on the SPI Server. +// SPI Server test mode is used for extensive driver functionality testing. +// <0=> Loopback +// <1=> SPI Server +// SPI Server +// SPI Server configuration. +// Specifies the communication settings at which Driver Validation communicates with the SPI Server. +// Fixed settings: +// Mode: Master +// Clock / Frame Format: Clock Polarity 0, Clock Phase 0 +// Data Bits: 8 +// Bit Order: MSB to LSB +// Slave Select +// Select mode of driving Slave Select line. +// <1=> Software Controlled +// <2=> Hardware Controlled +// Bus Speed <10000-1000000000> +// Select bus speed setting (in bps) used by the SPI Server. +// +// Tests +// Tests configuration +// Default settings +// Default settings used for tests. +// Slave Select +// Select default mode of driving Slave Select line in tests. +// This setting is used for all tests except the Data Exchange: Mode tests. +// <0=> Not used +// <1=> Software Controlled +// <2=> Hardware Controlled +// Clock / Frame Format +// Select default clock / frame format setting for tests. +// This setting is used for all tests except the Data Exchange: Clock / Frame Format tests. +// <0=> Clock Polarity 0, Clock Phase 0 +// <1=> Clock Polarity 0, Clock Phase 1 +// <2=> Clock Polarity 1, Clock Phase 0 +// <3=> Clock Polarity 1, Clock Phase 1 +// <4=> Texas Instruments Frame Format +// <5=> National Semiconductor Microwire Frame Format +// Data Bits <1-32> +// Select default data bits setting for tests. +// This setting is used for all tests except the Data Exchange: Data Bits tests. +// Bit Order <0=> MSB to LSB <1=> LSB to MSB +// Select default bit order setting for tests. +// This setting is used for all tests except the Data Exchange: Bit Order tests. +// Bus Speed <10000-1000000000> +// Select default bus speed setting for tests. +// This setting is used for all tests except the Data Exchange: Bus Speed tests. +// Number of Items <1-1024> +// Select default number of data items for tests. +// This setting is used for all tests except the Data Exchange: Other: SPI_Number_Of_Items tests. +// +// Bus Speed +// Bus speed tests configuration. +// Minimum Bus Speed <10000-1000000000> +// Select minimum bus speed setting (in bps). +// This setting is used only in SPI_Bus_Speed_Min test function. +// Maximum Bus Speed <10000-1000000000> +// Select maximum bus speed setting (in bps). +// This setting is used only in SPI_Bus_Speed_Max test function. +// +// Number of Items +// Number of items test configuration. +// This setting is used only in SPI_Number_Of_Items test function. +// (Value 0 means setting is not used) +// Number of Items 1 <0-1024> +// Number of Items 2 <0-1024> +// Number of Items 3 <0-1024> +// Number of Items 4 <0-1024> +// Number of Items 5 <0-1024> +// +// +// +// Tests +// Enable / disable tests. +// Driver Management +// Enable / disable driver management tests (functions: GetVersion, GetCapabilities, Initialize, Uninitialize, PowerControl). +// SPI_GetVersion +// Enable / disable GetVersion function tests. +// SPI_GetCapabilities +// Enable / disable GetCapabilities function tests. +// SPI_Initialize_Uninitialize +// Enable / disable Initialize and Uninitialize functions tests. +// SPI_PowerControl +// Enable / disable PowerControl function tests. +// +// Data Exchange +// Enable / disable data exchange tests (functions: Send, Receive, Transfer, GetDataCount, Control, GetStatus, SignalEvent). +// Mode +// Enable / disable SPI mode and Slave Select mode tests. +// (for Loopback test mode only Master mode with Slave Select not used test is supported!) +// SPI_Mode_Master_SS_Unused +// Enable / disable data exchange in Master mode with Slave Select not used test. +// SPI_Mode_Master_SS_Sw_Ctrl +// Enable / disable data exchange in Master mode with Slave Select Software Controlled test. +// SPI_Mode_Master_SS_Hw_Ctrl_Out +// Enable / disable data exchange in Master mode with Slave Select Hardware Controlled Output test. +// SPI_Mode_Master_SS_Hw_Mon_In +// Enable / disable data exchange in Master mode with Slave Select Hardware Monitored Input test. +// SPI_Mode_Slave_SS_Hw_Mon +// Enable / disable data exchange in Slave mode with Slave Select Hardware Monitored test. +// SPI_Mode_Slave_SS_Sw_Ctrl +// Enable / disable data exchange in Slave mode with Slave Select Software Controlled test. +// +// Clock / Frame Format +// Enable / disable clock / frame format tests. +// (all of these tests are supported only in SPI Server test mode!) +// SPI_Format_Clock_Pol0_Pha0 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 0 test. +// SPI_Format_Clock_Pol0_Pha1 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 1 test. +// SPI_Format_Clock_Pol1_Pha0 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 0 test. +// SPI_Format_Clock_Pol1_Pha1 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 1 test. +// SPI_Format_Frame_TI +// Enable / disable data exchange with Texas Instruments frame format test. +// SPI_Format_Frame_Microwire +// Enable / disable data exchange with National Semiconductor Microwire frame format test. +// +// Data Bits +// Enable / disable data bits tests. +// (for Loopback test mode only: 8, 16, 24, and 32 data bit tests are supported!) +// SPI_Data_Bits_1 +// Enable / disable data exchange with 1 bit per frame test. +// SPI_Data_Bits_2 +// Enable / disable data exchange with 2 bits per frame test. +// SPI_Data_Bits_3 +// Enable / disable data exchange with 3 bits per frame test. +// SPI_Data_Bits_4 +// Enable / disable data exchange with 4 bits per frame test. +// SPI_Data_Bits_5 +// Enable / disable data exchange with 5 bits per frame test. +// SPI_Data_Bits_6 +// Enable / disable data exchange with 6 bits per frame test. +// SPI_Data_Bits_7 +// Enable / disable data exchange with 7 bits per frame test. +// SPI_Data_Bits_8 +// Enable / disable data exchange with 8 bits per frame test. +// SPI_Data_Bits_9 +// Enable / disable data exchange with 9 bits per frame test. +// SPI_Data_Bits_10 +// Enable / disable data exchange with 10 bits per frame test. +// SPI_Data_Bits_11 +// Enable / disable data exchange with 11 bits per frame test. +// SPI_Data_Bits_12 +// Enable / disable data exchange with 12 bits per frame test. +// SPI_Data_Bits_13 +// Enable / disable data exchange with 13 bits per frame test. +// SPI_Data_Bits_14 +// Enable / disable data exchange with 14 bits per frame test. +// SPI_Data_Bits_15 +// Enable / disable data exchange with 15 bits per frame test. +// SPI_Data_Bits_16 +// Enable / disable data exchange with 16 bits per frame test. +// SPI_Data_Bits_17 +// Enable / disable data exchange with 17 bits per frame test. +// SPI_Data_Bits_18 +// Enable / disable data exchange with 18 bits per frame test. +// SPI_Data_Bits_19 +// Enable / disable data exchange with 19 bits per frame test. +// SPI_Data_Bits_20 +// Enable / disable data exchange with 20 bits per frame test. +// SPI_Data_Bits_21 +// Enable / disable data exchange with 21 bits per frame test. +// SPI_Data_Bits_22 +// Enable / disable data exchange with 22 bits per frame test. +// SPI_Data_Bits_23 +// Enable / disable data exchange with 23 bits per frame test. +// SPI_Data_Bits_24 +// Enable / disable data exchange with 24 bits per frame test. +// SPI_Data_Bits_25 +// Enable / disable data exchange with 25 bits per frame test. +// SPI_Data_Bits_26 +// Enable / disable data exchange with 26 bits per frame test. +// SPI_Data_Bits_27 +// Enable / disable data exchange with 27 bits per frame test. +// SPI_Data_Bits_28 +// Enable / disable data exchange with 28 bits per frame test. +// SPI_Data_Bits_29 +// Enable / disable data exchange with 29 bits per frame test. +// SPI_Data_Bits_30 +// Enable / disable data exchange with 30 bits per frame test. +// SPI_Data_Bits_31 +// Enable / disable data exchange with 31 bits per frame test. +// SPI_Data_Bits_32 +// Enable / disable data exchange with 32 bits per frame test. +// +// Bit Order +// Enable / disable bit order tests. +// (all of these tests are supported only in SPI Server test mode!) +// SPI_Bit_Order_MSB_LSB +// Enable / disable data exchange with bit order from MSB to LSB test. +// SPI_Bit_Order_LSB_MSB +// Enable / disable data exchange with bit order from LSB to MSB test. +// +// Bus Speed +// Enable / disable bus speeds tests. +// SPI_Bus_Speed_Min +// Enable / disable data exchange at minimum supported bus speed test. +// SPI_Bus_Speed_Max +// Enable / disable data exchange at maximum supported bus speed test. +// +// Other +// Enable / disable other tests. +// SPI_Number_Of_Items +// Enable / disable data exchange with different number of data items test. +// SPI_GetDataCount +// Enable / disable GetDataCount count changing during data exchange test. +// SPI_Abort +// Enable / disable data exchange Abort test. +// +// +// Event +// Enable / disable event signaling tests (function: SignalEvent). +// (all of these tests are supported only in SPI Server test mode!) +// SPI_DataLost +// Enable / disable ARM_SPI_EVENT_DATA_LOST event generation test. +// SPI_ModeFault +// Enable / disable ARM_SPI_EVENT_MODE_FAULT event generation test. +// +// +// + +#define DRV_SPI 0 +#define SPI_CFG_TEST_MODE 1 +#define SPI_CFG_SRV_SS_MODE 1 +#define SPI_CFG_SRV_BUS_SPEED 1000000 +#define SPI_CFG_SRV_CMD_TOUT 100 +#define SPI_CFG_DEF_SS_MODE 1 +#define SPI_CFG_DEF_FORMAT 0 +#define SPI_CFG_DEF_DATA_BITS 8 +#define SPI_CFG_DEF_BIT_ORDER 0 +#define SPI_CFG_DEF_BUS_SPEED 1000000 +#define SPI_CFG_DEF_NUM 512 +#define SPI_CFG_MIN_BUS_SPEED 1000000 +#define SPI_CFG_MAX_BUS_SPEED 10000000 +#define SPI_CFG_NUM1 1 +#define SPI_CFG_NUM2 31 +#define SPI_CFG_NUM3 65 +#define SPI_CFG_NUM4 1023 +#define SPI_CFG_NUM5 1024 +#define SPI_CFG_XFER_TIMEOUT 100 +#define SPI_TG_DRIVER_MANAGEMENT_EN 1 +#define SPI_TC_GET_VERSION_EN 1 +#define SPI_TC_GET_CAPABILITIES_EN 1 +#define SPI_TC_INIT_UNINIT_EN 1 +#define SPI_TC_POWER_CONTROL_EN 1 +#define SPI_TG_DATA_EXCHANGE_EN 1 +#define SPI_TG_MODE_EN 1 +#define SPI_TC_MASTER_UNUSED_EN 1 +#define SPI_TC_MASTER_SW_EN 1 +#define SPI_TC_MASTER_HW_OUT_EN 1 +#define SPI_TC_MASTER_HW_IN_EN 1 +#define SPI_TC_SLAVE_HW_EN 1 +#define SPI_TC_SLAVE_SW_EN 1 +#define SPI_TG_FORMAT_EN 1 +#define SPI_TC_FORMAT_POL0_PHA0_EN 1 +#define SPI_TC_FORMAT_POL0_PHA1_EN 1 +#define SPI_TC_FORMAT_POL1_PHA0_EN 1 +#define SPI_TC_FORMAT_POL1_PHA1_EN 1 +#define SPI_TC_FORMAT_TI_EN 1 +#define SPI_TC_FORMAT_MICROWIRE_EN 0 +#define SPI_TG_DATA_BIT_EN 1 +#define SPI_TC_DATA_BIT_EN_MASK 0x00008080 +#define SPI_TG_BIT_ORDER_EN 1 +#define SPI_TC_BIT_ORDER_MSB_LSB_EN 1 +#define SPI_TC_BIT_ORDER_LSB_MSB_EN 1 +#define SPI_TG_BUS_SPEED_EN 1 +#define SPI_TC_BUS_SPEED_MIN_EN 1 +#define SPI_TC_BUS_SPEED_MAX_EN 1 +#define SPI_TG_OTHER_EN 1 +#define SPI_TC_NUMBER_OF_ITEMS_EN 1 +#define SPI_TC_GET_DATA_COUNT_EN 1 +#define SPI_TC_ABORT_EN 1 +#define SPI_TG_EVENT_EN 1 +#define SPI_TC_DATA_LOST_EN 1 +#define SPI_TC_MODE_FAULT_EN 1 + +#endif /* DV_SPI_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_USART_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_USART_Config.h new file mode 100644 index 0000000..6d55775 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_USART_Config.h @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V2.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Universal Synchronous Asynchronous Receiver/Transmitter (USART) + * driver validation configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_USART_CONFIG_H_ +#define DV_USART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USART +// Universal Synchronous Asynchronous Receiver/Transmitter (USART) driver validation configuration +// Driver_USART# <0-255> +// Choose the Driver_USART# instance to test. +// For example to test Driver_USART0 select 0. +// Configuration +// Test Mode, USART Server and Tests configuration. +// Test Mode +// Select test mode: Loopback or USART Server. +// For Loopback test mode connect the Tx and Rx lines directly. +// Loopback test mode is used for basic driver functionality testing before using USART Server test mode. +// For USART Server test mode connect: +// - Tx line to Rx on the USART Server +// - Rx line to Tx on the USART Server +// - GND to same line on the USART Server +// USART Server test mode is used for extensive driver functionality testing. +// <0=> Loopback +// <1=> USART Server +// USART Server +// USART Server configuration. +// Specifies the communication settings at which Driver Validation communicates with the USART Server. +// These settings must be same as settings configured and used by the USART Server. +// Fixed settings: +// Baudrate: 115200 +// Data Bits: 8 +// Parity: None +// Stop Bits: 1 +// Flow Control: None +// Mode +// Select mode setting used by the USART Server. +// <1=> Asynchronous +// <4=> Single-wire +// <5=> IrDA +// +// Tests +// Tests configuration +// Default settings +// Default settings used for tests. +// Mode +// Select default mode setting used for tests. +// <1=> Asynchronous +// <2=> Synchronous Master +// <3=> Synchronous Slave +// <4=> Single-wire +// <5=> IrDA +// Data Bits <5=> 5 <6=> 6 <7=> 7 <8=> 8 <9=> 9 +// Select default data bits setting for tests. +// This setting is used for all tests except the Data Exchange: Data Bits tests. +// Parity <0=> None <1=> Even <2=> Odd +// Select default parity setting for tests. +// This setting is used for all tests except the Data Exchange: Parity tests. +// Stop Bits <0=> 1 <1=> 2 <2=> 1.5 <3=> 0.5 +// Select default stop bits setting for tests. +// This setting is used for all tests except the Data Exchange: Stop Bits tests. +// Flow control <0=> No <1=> RTS <2=> CTS <3=> RTS/CTS +// Select default flow control setting for tests. +// This setting is used for all tests except the Data Exchange: Flow Control tests. +// Clock Polarity +// Select default clock polarity for tests. +// This setting is used for all tests except the Data Exchange: Polarity Phase tests. +// This setting is only relevant for synchronous mode. +// <0=> Clock Polarity 0 +// <1=> Clock Polarity 1 +// Clock Phase +// Select default clock phase setting for tests. +// This setting is used for all tests except the Data Exchange: Polarity Phase tests. +// This setting is only relevant for synchronous mode. +// <0=> Clock Phase 0 +// <1=> Clock Phase 1 +// Baudrate <115200-1000000000> +// Select default baudrate setting for tests. +// This setting is used for all tests except the Data Exchange: Baudrate tests. +// Number of Items <1-1024> +// Select default number of data items for tests. +// This setting is used for all tests except the Data Exchange: Other: USART_Number_Of_Items tests. +// +// Baudrate +// Baudrate tests configuration. +// Minimum Baudrate <115200-1000000000> +// Select minimum baudrate setting. +// This setting is used only in USART_Baudrate_Min test function. +// Maximum Baudrate <115200-1000000000> +// Select maximum baudrate setting. +// This setting is used only in USART_Baudrate_Max test function. +// +// Number of Items +// Number of items test configuration. +// This setting is used only in USART_Number_Of_Items test function. +// (Value 0 means setting is not used) +// Number of Items 1 <0-1024> +// Number of Items 2 <0-1024> +// Number of Items 3 <0-1024> +// Number of Items 4 <0-1024> +// Number of Items 5 <0-1024> +// +// +// +// Tests +// Enable / disable tests. +// Driver Management +// Enable / disable driver management tests (functions: GetVersion, GetCapabilities, Initialize, Uninitialize, PowerControl). +// USART_GetVersion +// Enable / disable GetVersion function tests. +// USART_GetCapabilities +// Enable / disable GetCapabilities function tests. +// USART_Initialize_Uninitialize +// Enable / disable Initialize and Uninitialize functions tests. +// USART_PowerControl +// Enable / disable PowerControl function tests. +// +// Data Exchange +// Enable / disable data exchange tests (functions: Send, Receive, Transfer, GetTxCount, GetRxCount, Control, GetStatus, SignalEvent). +// Mode +// Enable / disable USART mode tests. +// (for Loopback test mode only Asynchronous, Synchronous Master and Single-wire mode tests are supported!) +// USART_Mode_Asynchronous +// Enable / disable data exchange in Asynchronous mode test. +// USART_Mode_Synchronous_Master +// Enable / disable data exchange in Synchronous Master mode test. +// USART_Mode_Synchronous_Slave +// Enable / disable data exchange in Synchronous Slave mode test. +// USART_Mode_Single_Wire +// Enable / disable data exchange in Single-wire mode test. +// This test is supported only in Loopback test mode! +// USART_Mode_IrDA +// Enable / disable data exchange in Infra-red Data mode test. +// This test requires IrDA hardware. +// +// Data Bits +// Enable / disable data bits tests. +// (for Loopback test mode only: 8 data bit test is supported!) +// USART_Data_Bits_5 +// Enable / disable data exchange with 5 data bits per packet test. +// USART_Data_Bits_6 +// Enable / disable data exchange with 6 data bits per packet test. +// USART_Data_Bits_7 +// Enable / disable data exchange with 7 data bits per packet test. +// USART_Data_Bits_8 +// Enable / disable data exchange with 8 data bits per packet test. +// USART_Data_Bits_9 +// Enable / disable data exchange with 9 dtat bits per packet test. +// +// Parity +// Enable / disable parity tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Parity_None +// Enable / disable data exchange with no parity test. +// USART_Parity_Even +// Enable / disable data exchange with even parity test. +// USART_Parity_Odd +// Enable / disable data exchange odd parity test. +// +// Stop Bits +// Enable / disable stop bits tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Stop_Bits_1 +// Enable / disable data exchange with 1 stop bit test. +// USART_Stop_Bits_2 +// Enable / disable data exchange with 2 stop bits test. +// USART_Stop_Bits_1_5 +// Enable / disable data exchange with 1.5 stop bits test. +// USART_Stop_Bits_0_5 +// Enable / disable data exchange with 0.5 stop bit test. +// +// Flow Control +// Enable / disable flow control tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Flow_Control_None +// Enable / disable data exchange with no flow control test. +// USART_Flow_Control_RTS +// Enable / disable data exchange with no flow control using RTS signal test. +// USART_Flow_Control_CTS +// Enable / disable data exchange with no flow control using CTS signal test. +// USART_Flow_Control_RTS_CTS +// Enable / disable data exchange with no flow control using RTS and CTS signals test. +// +// Clock Format +// Enable / disable clock format tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Clock_Pol0_Pha0 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 0 test. +// USART_Clock_Pol0_Pha1 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 1 test. +// USART_Clock_Pol1_Pha0 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 0 test. +// USART_Clock_Pol1_Pha1 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 1 test. +// +// Baudrate +// Enable / disable baudrate tests. +// USART_Baudrate_Min +// Enable / disable data exchange at minimum supported baudrate test. +// USART_Baudrate_Max +// Enable / disable data exchange at maximum supported baudrate test. +// +// Other +// Enable / disable other tests. +// USART_Number_Of_Items +// Enable / disable data exchange with different number of data items test. +// USART_GetTxCount +// Enable / disable GetTxCount count changing during data exchange (Send) test. +// USART_GetRxCount +// Enable / disable GetRxCount count changing during data exchange (Receive) test. +// USART_GetTxRxCount +// Enable / disable GetTxRxCount count changing during data exchange (Transfer) test (in Synchronous Master mode only). +// USART_AbortSend +// Enable / disable data exchange Abort Send test. +// USART_AbortReceive +// Enable / disable data exchange Abort Receive test. +// USART_AbortTransfer +// Enable / disable data exchange Abort Transfer test. +// USART_TxBreak +// Enable / disable Break signaling (Tx) test. +// +// +// Modem +// Enable / disable modem line tests (functions: SetModemControl, GetModemStatus). +// (all of these tests are supported only in USART Server test mode!) +// USART_SetModem_RTS +// Enable / disable driving of RTS (Request To Send) modem line test. +// USART_SetModem_DTR +// Enable / disable driving of DTR (Data Terminal Ready) modem line test. +// USART_GetModem_CTS +// Enable / disable reading of CTS (Clear To Send) modem line test. +// USART_GetModem_DSR +// Enable / disable reading of DSR (Data Set Ready) modem line test. +// USART_GetModem_DCD +// Enable / disable reading of DCD (Data Carrier Detect) modem line test. +// USART_GetModem_RI +// Enable / disable reading of RI (Ring Indicator) modem line test. +// +// Event +// Enable / disable event signaling tests (function: SignalEvent). +// (all of these tests are supported only in USART Server test mode!) +// USART_Tx_Underflow +// Enable / disable ARM_USART_EVENT_TX_UNDERFLOW event generation test. +// USART_Rx_Overflow +// Enable / disable ARM_USART_EVENT_RX_OVERFLOW event generation test. +// USART_Rx_Timeout +// Enable / disable ARM_USART_EVENT_RX_TIMEOUT event generation test. +// USART_Rx_Break +// Enable / disable ARM_USART_EVENT_RX_BREAK event generation test. +// USART_Rx_Framing_Error +// Enable / disable ARM_USART_EVENT_RX_FRAMING_ERROR event generation test. +// USART_Rx_Parity_Error +// Enable / disable ARM_USART_EVENT_RX_PARITY_ERROR event generation test. +// USART_Event_CTS +// Enable / disable ARM_USART_EVENT_CTS event generation test. +// USART_Event_DSR +// Enable / disable ARM_USART_EVENT_DSR event generation test. +// USART_Event_DCD +// Enable / disable ARM_USART_EVENT_DCD event generation test. +// USART_Event_RI +// Enable / disable ARM_USART_EVENT_RI event generation test. +// +// +// + +#define DRV_USART 0 +#define USART_CFG_TEST_MODE 1 +#define USART_CFG_SRV_MODE 1 +#define USART_CFG_SRV_CMD_TOUT 100 +#define USART_CFG_DEF_MODE 1 +#define USART_CFG_DEF_DATA_BITS 8 +#define USART_CFG_DEF_PARITY 0 +#define USART_CFG_DEF_STOP_BITS 0 +#define USART_CFG_DEF_FLOW_CONTROL 0 +#define USART_CFG_DEF_CPOL 0 +#define USART_CFG_DEF_CPHA 0 +#define USART_CFG_DEF_BAUDRATE 115200 +#define USART_CFG_DEF_NUM 512 +#define USART_CFG_MIN_BAUDRATE 115200 +#define USART_CFG_MAX_BAUDRATE 921600 +#define USART_CFG_NUM1 1 +#define USART_CFG_NUM2 31 +#define USART_CFG_NUM3 65 +#define USART_CFG_NUM4 1023 +#define USART_CFG_NUM5 1024 +#define USART_CFG_XFER_TIMEOUT 200 +#define USART_TG_DRIVER_MANAGEMENT_EN 1 +#define USART_TC_GET_VERSION_EN 1 +#define USART_TC_GET_CAPABILITIES_EN 1 +#define USART_TC_INIT_UNINIT_EN 1 +#define USART_TC_POWER_CONTROL_EN 1 +#define USART_TG_DATA_EXCHANGE_EN 1 +#define USART_TG_MODE_EN 1 +#define USART_TC_ASYNC_EN 1 +#define USART_TC_SYNC_MASTER_EN 0 +#define USART_TC_SYNC_SLAVE_EN 0 +#define USART_TC_SINGLE_WIRE_EN 0 +#define USART_TC_IRDA_EN 0 +#define USART_TG_DATA_BITS_EN 1 +#define USART_TC_DATA_BITS_5_EN 0 +#define USART_TC_DATA_BITS_6_EN 0 +#define USART_TC_DATA_BITS_7_EN 0 +#define USART_TC_DATA_BITS_8_EN 1 +#define USART_TC_DATA_BITS_9_EN 0 +#define USART_TG_PARITY_EN 1 +#define USART_TC_PARITY_NONE_EN 1 +#define USART_TC_PARITY_EVEN_EN 1 +#define USART_TC_PARITY_ODD_EN 1 +#define USART_TG_STOP_BITS_EN 1 +#define USART_TC_STOP_BITS_1_EN 1 +#define USART_TC_STOP_BITS_2_EN 1 +#define USART_TC_STOP_BITS_1_5_EN 0 +#define USART_TC_STOP_BITS_0_5_EN 0 +#define USART_TG_FLOW_CTRL_EN 0 +#define USART_TC_FLOW_CTRL_NONE_EN 1 +#define USART_TC_FLOW_CTRL_RTS_EN 1 +#define USART_TC_FLOW_CTRL_CTS_EN 1 +#define USART_TC_FLOW_CTRL_RTS_CTS_EN 1 +#define USART_TG_CLOCK_EN 0 +#define USART_TC_CLOCK_POL0_PHA0_EN 1 +#define USART_TC_CLOCK_POL0_PHA1_EN 1 +#define USART_TC_CLOCK_POL1_PHA0_EN 1 +#define USART_TC_CLOCK_POL1_PHA1_EN 1 +#define USART_TG_BAUDRATE_EN 1 +#define USART_TC_BAUDRATE_MIN_EN 1 +#define USART_TC_BAUDRATE_MAX_EN 1 +#define USART_TG_OTHER_EN 1 +#define USART_TC_NUMBER_OF_ITEMS_EN 1 +#define USART_TC_GET_TX_COUNT_EN 1 +#define USART_TC_GET_RX_COUNT_EN 1 +#define USART_TC_GET_TX_RX_COUNT_EN 0 +#define USART_TC_ABORT_SEND_EN 1 +#define USART_TC_ABORT_RECEIVE_EN 1 +#define USART_TC_ABORT_TRANSFER_EN 0 +#define USART_TC_TX_BREAK_EN 1 +#define USART_TG_MODEM_EN 0 +#define USART_TC_MODEM_RTS_EN 1 +#define USART_TC_MODEM_DTR_EN 0 +#define USART_TC_MODEM_CTS_EN 1 +#define USART_TC_MODEM_DSR_EN 0 +#define USART_TC_MODEM_DCD_EN 0 +#define USART_TC_MODEM_RI_EN 0 +#define USART_TG_EVENT_EN 0 +#define USART_TC_TX_UNDERFLOW_EN 0 +#define USART_TC_RX_OVERFLOW_EN 1 +#define USART_TC_RX_TIMEOUT_EN 1 +#define USART_TC_RX_BREAK_EN 1 +#define USART_TC_RX_FRAMING_ERROR_EN 1 +#define USART_TC_RX_PARITY_ERROR_EN 1 +#define USART_TC_EVENT_CTS_EN 0 +#define USART_TC_EVENT_DSR_EN 0 +#define USART_TC_EVENT_DCD_EN 0 +#define USART_TC_EVENT_RI_EN 0 + +#endif /* DV_USART_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_USART_Config.h.base@2.0.0 b/Template/RTE/CMSIS_Driver_Validation/DV_USART_Config.h.base@2.0.0 new file mode 100644 index 0000000..6d55775 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_USART_Config.h.base@2.0.0 @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V2.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Universal Synchronous Asynchronous Receiver/Transmitter (USART) + * driver validation configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_USART_CONFIG_H_ +#define DV_USART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USART +// Universal Synchronous Asynchronous Receiver/Transmitter (USART) driver validation configuration +// Driver_USART# <0-255> +// Choose the Driver_USART# instance to test. +// For example to test Driver_USART0 select 0. +// Configuration +// Test Mode, USART Server and Tests configuration. +// Test Mode +// Select test mode: Loopback or USART Server. +// For Loopback test mode connect the Tx and Rx lines directly. +// Loopback test mode is used for basic driver functionality testing before using USART Server test mode. +// For USART Server test mode connect: +// - Tx line to Rx on the USART Server +// - Rx line to Tx on the USART Server +// - GND to same line on the USART Server +// USART Server test mode is used for extensive driver functionality testing. +// <0=> Loopback +// <1=> USART Server +// USART Server +// USART Server configuration. +// Specifies the communication settings at which Driver Validation communicates with the USART Server. +// These settings must be same as settings configured and used by the USART Server. +// Fixed settings: +// Baudrate: 115200 +// Data Bits: 8 +// Parity: None +// Stop Bits: 1 +// Flow Control: None +// Mode +// Select mode setting used by the USART Server. +// <1=> Asynchronous +// <4=> Single-wire +// <5=> IrDA +// +// Tests +// Tests configuration +// Default settings +// Default settings used for tests. +// Mode +// Select default mode setting used for tests. +// <1=> Asynchronous +// <2=> Synchronous Master +// <3=> Synchronous Slave +// <4=> Single-wire +// <5=> IrDA +// Data Bits <5=> 5 <6=> 6 <7=> 7 <8=> 8 <9=> 9 +// Select default data bits setting for tests. +// This setting is used for all tests except the Data Exchange: Data Bits tests. +// Parity <0=> None <1=> Even <2=> Odd +// Select default parity setting for tests. +// This setting is used for all tests except the Data Exchange: Parity tests. +// Stop Bits <0=> 1 <1=> 2 <2=> 1.5 <3=> 0.5 +// Select default stop bits setting for tests. +// This setting is used for all tests except the Data Exchange: Stop Bits tests. +// Flow control <0=> No <1=> RTS <2=> CTS <3=> RTS/CTS +// Select default flow control setting for tests. +// This setting is used for all tests except the Data Exchange: Flow Control tests. +// Clock Polarity +// Select default clock polarity for tests. +// This setting is used for all tests except the Data Exchange: Polarity Phase tests. +// This setting is only relevant for synchronous mode. +// <0=> Clock Polarity 0 +// <1=> Clock Polarity 1 +// Clock Phase +// Select default clock phase setting for tests. +// This setting is used for all tests except the Data Exchange: Polarity Phase tests. +// This setting is only relevant for synchronous mode. +// <0=> Clock Phase 0 +// <1=> Clock Phase 1 +// Baudrate <115200-1000000000> +// Select default baudrate setting for tests. +// This setting is used for all tests except the Data Exchange: Baudrate tests. +// Number of Items <1-1024> +// Select default number of data items for tests. +// This setting is used for all tests except the Data Exchange: Other: USART_Number_Of_Items tests. +// +// Baudrate +// Baudrate tests configuration. +// Minimum Baudrate <115200-1000000000> +// Select minimum baudrate setting. +// This setting is used only in USART_Baudrate_Min test function. +// Maximum Baudrate <115200-1000000000> +// Select maximum baudrate setting. +// This setting is used only in USART_Baudrate_Max test function. +// +// Number of Items +// Number of items test configuration. +// This setting is used only in USART_Number_Of_Items test function. +// (Value 0 means setting is not used) +// Number of Items 1 <0-1024> +// Number of Items 2 <0-1024> +// Number of Items 3 <0-1024> +// Number of Items 4 <0-1024> +// Number of Items 5 <0-1024> +// +// +// +// Tests +// Enable / disable tests. +// Driver Management +// Enable / disable driver management tests (functions: GetVersion, GetCapabilities, Initialize, Uninitialize, PowerControl). +// USART_GetVersion +// Enable / disable GetVersion function tests. +// USART_GetCapabilities +// Enable / disable GetCapabilities function tests. +// USART_Initialize_Uninitialize +// Enable / disable Initialize and Uninitialize functions tests. +// USART_PowerControl +// Enable / disable PowerControl function tests. +// +// Data Exchange +// Enable / disable data exchange tests (functions: Send, Receive, Transfer, GetTxCount, GetRxCount, Control, GetStatus, SignalEvent). +// Mode +// Enable / disable USART mode tests. +// (for Loopback test mode only Asynchronous, Synchronous Master and Single-wire mode tests are supported!) +// USART_Mode_Asynchronous +// Enable / disable data exchange in Asynchronous mode test. +// USART_Mode_Synchronous_Master +// Enable / disable data exchange in Synchronous Master mode test. +// USART_Mode_Synchronous_Slave +// Enable / disable data exchange in Synchronous Slave mode test. +// USART_Mode_Single_Wire +// Enable / disable data exchange in Single-wire mode test. +// This test is supported only in Loopback test mode! +// USART_Mode_IrDA +// Enable / disable data exchange in Infra-red Data mode test. +// This test requires IrDA hardware. +// +// Data Bits +// Enable / disable data bits tests. +// (for Loopback test mode only: 8 data bit test is supported!) +// USART_Data_Bits_5 +// Enable / disable data exchange with 5 data bits per packet test. +// USART_Data_Bits_6 +// Enable / disable data exchange with 6 data bits per packet test. +// USART_Data_Bits_7 +// Enable / disable data exchange with 7 data bits per packet test. +// USART_Data_Bits_8 +// Enable / disable data exchange with 8 data bits per packet test. +// USART_Data_Bits_9 +// Enable / disable data exchange with 9 dtat bits per packet test. +// +// Parity +// Enable / disable parity tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Parity_None +// Enable / disable data exchange with no parity test. +// USART_Parity_Even +// Enable / disable data exchange with even parity test. +// USART_Parity_Odd +// Enable / disable data exchange odd parity test. +// +// Stop Bits +// Enable / disable stop bits tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Stop_Bits_1 +// Enable / disable data exchange with 1 stop bit test. +// USART_Stop_Bits_2 +// Enable / disable data exchange with 2 stop bits test. +// USART_Stop_Bits_1_5 +// Enable / disable data exchange with 1.5 stop bits test. +// USART_Stop_Bits_0_5 +// Enable / disable data exchange with 0.5 stop bit test. +// +// Flow Control +// Enable / disable flow control tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Flow_Control_None +// Enable / disable data exchange with no flow control test. +// USART_Flow_Control_RTS +// Enable / disable data exchange with no flow control using RTS signal test. +// USART_Flow_Control_CTS +// Enable / disable data exchange with no flow control using CTS signal test. +// USART_Flow_Control_RTS_CTS +// Enable / disable data exchange with no flow control using RTS and CTS signals test. +// +// Clock Format +// Enable / disable clock format tests. +// (all of these tests are supported only in USART Server test mode!) +// USART_Clock_Pol0_Pha0 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 0 test. +// USART_Clock_Pol0_Pha1 +// Enable / disable data exchange with clock format: Polarity 0 / Phase 1 test. +// USART_Clock_Pol1_Pha0 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 0 test. +// USART_Clock_Pol1_Pha1 +// Enable / disable data exchange with clock format: Polarity 1 / Phase 1 test. +// +// Baudrate +// Enable / disable baudrate tests. +// USART_Baudrate_Min +// Enable / disable data exchange at minimum supported baudrate test. +// USART_Baudrate_Max +// Enable / disable data exchange at maximum supported baudrate test. +// +// Other +// Enable / disable other tests. +// USART_Number_Of_Items +// Enable / disable data exchange with different number of data items test. +// USART_GetTxCount +// Enable / disable GetTxCount count changing during data exchange (Send) test. +// USART_GetRxCount +// Enable / disable GetRxCount count changing during data exchange (Receive) test. +// USART_GetTxRxCount +// Enable / disable GetTxRxCount count changing during data exchange (Transfer) test (in Synchronous Master mode only). +// USART_AbortSend +// Enable / disable data exchange Abort Send test. +// USART_AbortReceive +// Enable / disable data exchange Abort Receive test. +// USART_AbortTransfer +// Enable / disable data exchange Abort Transfer test. +// USART_TxBreak +// Enable / disable Break signaling (Tx) test. +// +// +// Modem +// Enable / disable modem line tests (functions: SetModemControl, GetModemStatus). +// (all of these tests are supported only in USART Server test mode!) +// USART_SetModem_RTS +// Enable / disable driving of RTS (Request To Send) modem line test. +// USART_SetModem_DTR +// Enable / disable driving of DTR (Data Terminal Ready) modem line test. +// USART_GetModem_CTS +// Enable / disable reading of CTS (Clear To Send) modem line test. +// USART_GetModem_DSR +// Enable / disable reading of DSR (Data Set Ready) modem line test. +// USART_GetModem_DCD +// Enable / disable reading of DCD (Data Carrier Detect) modem line test. +// USART_GetModem_RI +// Enable / disable reading of RI (Ring Indicator) modem line test. +// +// Event +// Enable / disable event signaling tests (function: SignalEvent). +// (all of these tests are supported only in USART Server test mode!) +// USART_Tx_Underflow +// Enable / disable ARM_USART_EVENT_TX_UNDERFLOW event generation test. +// USART_Rx_Overflow +// Enable / disable ARM_USART_EVENT_RX_OVERFLOW event generation test. +// USART_Rx_Timeout +// Enable / disable ARM_USART_EVENT_RX_TIMEOUT event generation test. +// USART_Rx_Break +// Enable / disable ARM_USART_EVENT_RX_BREAK event generation test. +// USART_Rx_Framing_Error +// Enable / disable ARM_USART_EVENT_RX_FRAMING_ERROR event generation test. +// USART_Rx_Parity_Error +// Enable / disable ARM_USART_EVENT_RX_PARITY_ERROR event generation test. +// USART_Event_CTS +// Enable / disable ARM_USART_EVENT_CTS event generation test. +// USART_Event_DSR +// Enable / disable ARM_USART_EVENT_DSR event generation test. +// USART_Event_DCD +// Enable / disable ARM_USART_EVENT_DCD event generation test. +// USART_Event_RI +// Enable / disable ARM_USART_EVENT_RI event generation test. +// +// +// + +#define DRV_USART 0 +#define USART_CFG_TEST_MODE 1 +#define USART_CFG_SRV_MODE 1 +#define USART_CFG_SRV_CMD_TOUT 100 +#define USART_CFG_DEF_MODE 1 +#define USART_CFG_DEF_DATA_BITS 8 +#define USART_CFG_DEF_PARITY 0 +#define USART_CFG_DEF_STOP_BITS 0 +#define USART_CFG_DEF_FLOW_CONTROL 0 +#define USART_CFG_DEF_CPOL 0 +#define USART_CFG_DEF_CPHA 0 +#define USART_CFG_DEF_BAUDRATE 115200 +#define USART_CFG_DEF_NUM 512 +#define USART_CFG_MIN_BAUDRATE 115200 +#define USART_CFG_MAX_BAUDRATE 921600 +#define USART_CFG_NUM1 1 +#define USART_CFG_NUM2 31 +#define USART_CFG_NUM3 65 +#define USART_CFG_NUM4 1023 +#define USART_CFG_NUM5 1024 +#define USART_CFG_XFER_TIMEOUT 200 +#define USART_TG_DRIVER_MANAGEMENT_EN 1 +#define USART_TC_GET_VERSION_EN 1 +#define USART_TC_GET_CAPABILITIES_EN 1 +#define USART_TC_INIT_UNINIT_EN 1 +#define USART_TC_POWER_CONTROL_EN 1 +#define USART_TG_DATA_EXCHANGE_EN 1 +#define USART_TG_MODE_EN 1 +#define USART_TC_ASYNC_EN 1 +#define USART_TC_SYNC_MASTER_EN 0 +#define USART_TC_SYNC_SLAVE_EN 0 +#define USART_TC_SINGLE_WIRE_EN 0 +#define USART_TC_IRDA_EN 0 +#define USART_TG_DATA_BITS_EN 1 +#define USART_TC_DATA_BITS_5_EN 0 +#define USART_TC_DATA_BITS_6_EN 0 +#define USART_TC_DATA_BITS_7_EN 0 +#define USART_TC_DATA_BITS_8_EN 1 +#define USART_TC_DATA_BITS_9_EN 0 +#define USART_TG_PARITY_EN 1 +#define USART_TC_PARITY_NONE_EN 1 +#define USART_TC_PARITY_EVEN_EN 1 +#define USART_TC_PARITY_ODD_EN 1 +#define USART_TG_STOP_BITS_EN 1 +#define USART_TC_STOP_BITS_1_EN 1 +#define USART_TC_STOP_BITS_2_EN 1 +#define USART_TC_STOP_BITS_1_5_EN 0 +#define USART_TC_STOP_BITS_0_5_EN 0 +#define USART_TG_FLOW_CTRL_EN 0 +#define USART_TC_FLOW_CTRL_NONE_EN 1 +#define USART_TC_FLOW_CTRL_RTS_EN 1 +#define USART_TC_FLOW_CTRL_CTS_EN 1 +#define USART_TC_FLOW_CTRL_RTS_CTS_EN 1 +#define USART_TG_CLOCK_EN 0 +#define USART_TC_CLOCK_POL0_PHA0_EN 1 +#define USART_TC_CLOCK_POL0_PHA1_EN 1 +#define USART_TC_CLOCK_POL1_PHA0_EN 1 +#define USART_TC_CLOCK_POL1_PHA1_EN 1 +#define USART_TG_BAUDRATE_EN 1 +#define USART_TC_BAUDRATE_MIN_EN 1 +#define USART_TC_BAUDRATE_MAX_EN 1 +#define USART_TG_OTHER_EN 1 +#define USART_TC_NUMBER_OF_ITEMS_EN 1 +#define USART_TC_GET_TX_COUNT_EN 1 +#define USART_TC_GET_RX_COUNT_EN 1 +#define USART_TC_GET_TX_RX_COUNT_EN 0 +#define USART_TC_ABORT_SEND_EN 1 +#define USART_TC_ABORT_RECEIVE_EN 1 +#define USART_TC_ABORT_TRANSFER_EN 0 +#define USART_TC_TX_BREAK_EN 1 +#define USART_TG_MODEM_EN 0 +#define USART_TC_MODEM_RTS_EN 1 +#define USART_TC_MODEM_DTR_EN 0 +#define USART_TC_MODEM_CTS_EN 1 +#define USART_TC_MODEM_DSR_EN 0 +#define USART_TC_MODEM_DCD_EN 0 +#define USART_TC_MODEM_RI_EN 0 +#define USART_TG_EVENT_EN 0 +#define USART_TC_TX_UNDERFLOW_EN 0 +#define USART_TC_RX_OVERFLOW_EN 1 +#define USART_TC_RX_TIMEOUT_EN 1 +#define USART_TC_RX_BREAK_EN 1 +#define USART_TC_RX_FRAMING_ERROR_EN 1 +#define USART_TC_RX_PARITY_ERROR_EN 1 +#define USART_TC_EVENT_CTS_EN 0 +#define USART_TC_EVENT_DSR_EN 0 +#define USART_TC_EVENT_DCD_EN 0 +#define USART_TC_EVENT_RI_EN 0 + +#endif /* DV_USART_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_USBD_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_USBD_Config.h new file mode 100644 index 0000000..3d1d4b6 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_USBD_Config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Universal Serial Bus (USB) Device driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_USBD_CONFIG_H_ +#define DV_USBD_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device +// Universal Serial Bus (USB) Device driver validation configuration +// Driver_USBD# <0-255> +// Choose the Driver_USBD# instance to test. +// For example to test Driver_USBD0 select 0. +#define DRV_USBD 0 +// Tests +// Enable / disable tests. +// USBD_GetCapabilities +#define USBD_GETCAPABILITIES_EN 1 +// USBD_Initialization +#define USBD_INITIALIZATION_EN 1 +// USBD_PowerControl +#define USBD_POWERCONTROL_EN 1 +// USBD_CheckInvalidInit +#define USBD_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_USBD_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_USBD_Config.h.base@1.0.0 b/Template/RTE/CMSIS_Driver_Validation/DV_USBD_Config.h.base@1.0.0 new file mode 100644 index 0000000..3d1d4b6 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_USBD_Config.h.base@1.0.0 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Universal Serial Bus (USB) Device driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_USBD_CONFIG_H_ +#define DV_USBD_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device +// Universal Serial Bus (USB) Device driver validation configuration +// Driver_USBD# <0-255> +// Choose the Driver_USBD# instance to test. +// For example to test Driver_USBD0 select 0. +#define DRV_USBD 0 +// Tests +// Enable / disable tests. +// USBD_GetCapabilities +#define USBD_GETCAPABILITIES_EN 1 +// USBD_Initialization +#define USBD_INITIALIZATION_EN 1 +// USBD_PowerControl +#define USBD_POWERCONTROL_EN 1 +// USBD_CheckInvalidInit +#define USBD_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_USBD_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_USBH_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_USBH_Config.h new file mode 100644 index 0000000..1468953 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_USBH_Config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Universal Serial Bus (USB) Host driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_USBH_CONFIG_H_ +#define DV_USBH_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Host +// Universal Serial Bus (USB) Host driver validation configuration +// Driver_USBH# <0-255> +// Choose the Driver_USBH# instance to test. +// For example to test Driver_USBH0 select 0. +#define DRV_USBH 0 +// Tests +// Enable / disable tests. +// USBH_GetCapabilities +#define USBH_GETCAPABILITIES_EN 1 +// USBH_Initialization +#define USBH_INITIALIZATION_EN 1 +// USBH_PowerControl +#define USBH_POWERCONTROL_EN 1 +// USBH_CheckInvalidInit +#define USBH_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_USBH_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_USBH_Config.h.base@1.0.0 b/Template/RTE/CMSIS_Driver_Validation/DV_USBH_Config.h.base@1.0.0 new file mode 100644 index 0000000..1468953 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_USBH_Config.h.base@1.0.0 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.0.0 + * + * Project: CMSIS-Driver Validation + * Title: Universal Serial Bus (USB) Host driver validation + * configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_USBH_CONFIG_H_ +#define DV_USBH_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Host +// Universal Serial Bus (USB) Host driver validation configuration +// Driver_USBH# <0-255> +// Choose the Driver_USBH# instance to test. +// For example to test Driver_USBH0 select 0. +#define DRV_USBH 0 +// Tests +// Enable / disable tests. +// USBH_GetCapabilities +#define USBH_GETCAPABILITIES_EN 1 +// USBH_Initialization +#define USBH_INITIALIZATION_EN 1 +// USBH_PowerControl +#define USBH_POWERCONTROL_EN 1 +// USBH_CheckInvalidInit +#define USBH_CHECKINVALIDINIT_EN 1 +// +// + +#endif /* DV_USBH_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_WiFi_Config.h b/Template/RTE/CMSIS_Driver_Validation/DV_WiFi_Config.h new file mode 100644 index 0000000..30e68d0 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_WiFi_Config.h @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.1.0 + * + * Project: CMSIS-Driver Validation + * Title: WiFi driver validation configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_WIFI_CONFIG_H_ +#define DV_WIFI_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// WiFi +// WiFi driver validation configuration +// Driver_WiFi# <0-255> +// Choose the Driver_WiFi# instance to test. +// For example to test Driver_WiFi0 select 0. +#define DRV_WIFI 0 +// Configuration +// Configuration of valid settings for driver functionality testing +// Station +// Settings relevant for Station +// SSID +// SSID of network that Station will connect to +#define WIFI_STA_SSID "SSID" +// Password +// Password of network that Station will connect to +#define WIFI_STA_PASS "Password" +// Security Type +// <0=> Open <1=> WEP <2=> WPA <3=> WPA2 +// Security type of network that Station will connect to +#define WIFI_STA_SECURITY 3 +// Channel +// WiFi channel of network that Station will connect to +// Value 0 means Autodetect +#define WIFI_STA_CH 0 +// WPS PIN +// WiFi Protected Setup Personal Identification Number +#define WIFI_STA_WPS_PIN "12345678" +// +// Access Point +// Settings relevant for Access Point +// SSID +// SSID of created network +#define WIFI_AP_SSID "CMSIS_DV" +// Password +// Password of created network +#define WIFI_AP_PASS "Password" +// Security Type +// <0=> Open <1=> WEP <2=> WPA <3=> WPA2 +// Security type of created network +#define WIFI_AP_SECURITY 3 +// Channel +// WiFi channel of created network +// Value 0 means Autoselect +#define WIFI_AP_CH 0 +// WPS PIN +// WiFi Protected Setup Personal Identification Number +#define WIFI_AP_WPS_PIN "12345678" +// +// Socket +// Settings relevant for Socket testing +// SockServer IP +// Static IPv4 Address of SockServer +#define WIFI_SOCKET_SERVER_IP "192.168.1.10" +// Number of sockets +// Number of sockets that driver supports +// Default: 4 +#define WIFI_SOCKET_MAX_NUM 4 +// +// +// Tests +// Enable / disable tests. +// Control +// Control functions tests +#define WIFI_CONTROL_EN 1 +// WIFI_GetVersion +#define WIFI_GETVERSION_EN 1 +// WIFI_GetCapabilities +#define WIFI_GETCAPABILITIES_EN 1 +// WIFI_Initialization/Uninitialization +#define WIFI_INIT_UNINIT_EN 1 +// WIFI_PowerControl +#define WIFI_POWERCONTROL_EN 1 +// WIFI_GetModuleInfo +#define WIFI_GETMODULEINFO_EN 1 +// +// Management +// Management functions tests +#define WIFI_MANAGEMENT_EN 1 +// WIFI_SetOption/GetOption +#define WIFI_SETGETOPTION_EN 1 +// ARM_WIFI_BSSID <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_BSSID_STA/WIFI_BSSID_AP (1E-30-6C-A2-45-5E) +#define WIFI_SETGETOPTION_BSSID_EN 3 +// ARM_WIFI_TX_POWER <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_TX_POWER_STA/WIFI_TX_POWER_AP (16) +#define WIFI_SETGETOPTION_TX_POWER_EN 3 +// ARM_WIFI_LP_TIMER <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_LP_TIMER_STA (10) +#define WIFI_SETGETOPTION_LP_TIMER_EN 3 +// ARM_WIFI_DTIM <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_DTIM_STA/WIFI_DTIM_AP (3) +#define WIFI_SETGETOPTION_DTIM_EN 3 +// ARM_WIFI_BEACON <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_BEACON_AP (2000) +#define WIFI_SETGETOPTION_BEACON_EN 3 +// ARM_WIFI_MAC <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_MAC_STA/WIFI_MAC_AP (1E-30-6C-A2-45-5E) +#define WIFI_SETGETOPTION_MAC_EN 3 +// ARM_WIFI_IP <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_STA/WIFI_IP_AP (192.168.0.100) +#define WIFI_SETGETOPTION_IP_EN 3 +// ARM_WIFI_IP_SUBNET_MASK <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_SUBNET_MASK_STA/WIFI_IP_SUBNET_MASK_AP (255.255.255.0) +#define WIFI_SETGETOPTION_IP_SUBNET_MASK_EN 3 +// ARM_WIFI_IP_GATEWAY <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_GATEWAY_STA/WIFI_IP_GATEWAY_AP (192.168.0.254) +#define WIFI_SETGETOPTION_IP_GATEWAY_EN 3 +// ARM_WIFI_IP_DNS1 <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DNS1_STA/WIFI_IP_DNS1_AP (8.8.8.8) +#define WIFI_SETGETOPTION_IP_DNS1_EN 3 +// ARM_WIFI_IP_DNS2 <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DNS2_STA/WIFI_IP_DNS2_AP (8.8.4.4) +#define WIFI_SETGETOPTION_IP_DNS2_EN 3 +// ARM_WIFI_IP_DHCP <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +#define WIFI_SETGETOPTION_IP_DHCP_EN 3 +// ARM_WIFI_IP_DHCP_POOL_BEGIN <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DHCP_POOL_BEGIN_AP (192.168.0.100) +#define WIFI_SETGETOPTION_IP_DHCP_POOL_BEGIN_EN 3 +// ARM_WIFI_IP_DHCP_POOL_END <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DHCP_POOL_END_AP (192.168.0.200) +#define WIFI_SETGETOPTION_IP_DHCP_POOL_END_EN 3 +// ARM_WIFI_IP_DHCP_LEASE_TIME <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DHCP_LEASE_TIME_AP (3600) +#define WIFI_SETGETOPTION_IP_DHCP_LEASE_TIME_EN 3 +// +// WIFI_Scan +#define WIFI_SCAN_EN 1 +#define WIFI_SCAN_MAX_NUM 10 +// WIFI_Activate/Deactivate +#define WIFI_ACT_DEACT_EN 1 +// WIFI_IsConnected +#define WIFI_ISCONNECTED_EN 1 +// WIFI_GetNetInfo +#define WIFI_GETNETINFO_EN 1 +// +// Management (requires user interaction) +// Management functions tests that require user interaction +#define WIFI_MANAGEMENT_USER_EN 0 +// WIFI_Activate_AP +// For this test please connect a WiFi client (for example mobile phone) to AP +// and check if connection has succeeded +#define WIFI_ACT_AP 1 +// WPS +#define WIFI_WPS_USER_EN 1 +// WIFI_Activate_Station_WPS_PBC +// For this test please start WPS Push-button method on WiFi AP (router) manually +#define WIFI_ACT_STA_WPS_PBC 1 +// WIFI_Activate_Station_WPS_PIN +// For this test please configure WPS PIN method on WiFi AP (router) manually +#define WIFI_ACT_STA_WPS_PIN 1 +// WIFI_Activate_AP_WPS_PBC +// For this test please connect a WiFi client (for example mobile phone) to AP with WPS Push-button method +// and check if connection has succeeded +#define WIFI_ACT_AP_WPS_PBC 1 +// WIFI_Activate_AP_WPS_PIN +// For this test please connect a WiFi client (for example mobile phone) to AP with WPS PIN method +// and check if connection has succeeded +#define WIFI_ACT_AP_WPS_PIN 1 +// +// +// Socket API (requires SockServer) +// Socket functions tests +#define WIFI_SOCKET_EN 1 +// WIFI_SocketCreate +#define WIFI_SOCKETCREATE_EN 1 +// WIFI_SocketBind +#define WIFI_SOCKETBIND_EN 1 +// WIFI_SocketListen +#define WIFI_SOCKETLISTEN_EN 1 +// WIFI_SocketAccept +#define WIFI_SOCKETACCEPT_EN 1 +// WIFI_SocketAccept_nbio +#define WIFI_SOCKETACCEPT_NBIO_EN 1 +// WIFI_SocketConnect +#define WIFI_SOCKETCONNECT_EN 1 +// WIFI_SocketConnect_nbio +#define WIFI_SOCKETCONNECT_NBIO_EN 1 +// WIFI_SocketRecv +#define WIFI_SOCKETRECV_EN 1 +// WIFI_SocketRecv_nbio +#define WIFI_SOCKETRECV_NBIO_EN 1 +// WIFI_SocketRecvFrom +#define WIFI_SOCKETRECVFROM_EN 1 +// WIFI_SocketRecvFrom_nbio +#define WIFI_SOCKETRECVFROM_NBIO_EN 1 +// WIFI_SocketSend +#define WIFI_SOCKETSEND_EN 1 +// WIFI_SocketSendTo +#define WIFI_SOCKETSENDTO_EN 1 +// WIFI_SocketGetSockName +#define WIFI_SOCKETGETSOCKNAME_EN 1 +// WIFI_SocketGetPeerName +#define WIFI_SOCKETGETPEERNAME_EN 1 +// WIFI_SocketGetOpt +#define WIFI_SOCKETGETOPT_EN 1 +// WIFI_SocketSetOpt +#define WIFI_SOCKETSETOPT_EN 1 +// WIFI_SocketClose +#define WIFI_SOCKETCLOSE_EN 1 +// WIFI_SocketGetHostByName +#define WIFI_SOCKETGETHOSTBYNAME_EN 1 +// WIFI_Ping +#define WIFI_PING_EN 1 +// +// Socket Operation (requires SockServer) +// Socket operation tests +#define WIFI_SOCKET_OP_EN 1 +// WIFI_Transfer_Fixed +// Sends and receives in fixed size blocks +#define WIFI_TRANSFER_FIXED_EN 1 +// WIFI_Transfer_Incremental +// Sends and receives in ascending size blocks +#define WIFI_TRANSFER_INCREMENTAL_EN 1 +// WIFI_Send_Fragmented +// Sends several smaller blocks, receives one large block +#define WIFI_SEND_FRAGMENTED_EN 1 +// WIFI_Recv_Fragmented +// Sends one large block, receives several smaller blocks +#define WIFI_RECV_FRAGMENTED_EN 1 +// WIFI_Test_Speed +// Transmits data and measures transfer speed +#define WIFI_TEST_SPEED_EN 1 +// WIFI_Concurrent_Socket +// Transmits data in two sockets simultaneously +#define WIFI_CONCURRENT_SOCKET_EN 1 +// WIFI_Downstream_Rate +// Measures the downstream bandwidth +#define WIFI_DOWNSTREAM_RATE_EN 1 +// WIFI_Upstream_Rate +// Measures the upstream bandwidth +#define WIFI_UPSTREAM_RATE_EN 1 +// +// +// + +// Configuration settings of test values for Set/GetOptions +// BSSID +#define WIFI_BSSID_STA "1E-30-6C-A2-45-5E" +#define WIFI_BSSID_AP "1E-30-6C-A2-45-5E" +// Radio transmitting power in dBm +#define WIFI_TX_POWER_STA 16 +#define WIFI_TX_POWER_AP 16 +// Low-power deep-sleep time value in seconds +#define WIFI_LP_TIMER_STA 10 +// Delivery Traffic Indication Message interval value in beacons +#define WIFI_DTIM_STA 3 +#define WIFI_DTIM_AP 3 +// Beacon interval value in milliseconds +#define WIFI_BEACON_AP 2000 +// Ethernet MAC Address in text representation +#define WIFI_MAC_STA "1E-30-6C-A2-45-5E" +#define WIFI_MAC_AP "1E-30-6C-A2-45-5E" +// Static IPv4 Address in text representation +#define WIFI_IP_STA "192.168.0.100" +#define WIFI_IP_AP "192.168.0.100" +// Local Subnet mask in text representation +#define WIFI_IP_SUBNET_MASK_STA "255.255.255.0" +#define WIFI_IP_SUBNET_MASK_AP "255.255.255.0" +// IP Address of Default Gateway in text representation +#define WIFI_IP_GATEWAY_STA "192.168.0.254" +#define WIFI_IP_GATEWAY_AP "192.168.0.254" +// IP Address of Primary DNS Server in text representation +#define WIFI_IP_DNS1_STA "8.8.8.8" +#define WIFI_IP_DNS1_AP "8.8.8.8" +// IP Address of Secondary DNS Server in text representation +#define WIFI_IP_DNS2_STA "8.8.4.4" +#define WIFI_IP_DNS2_AP "8.8.4.4" +// IP Address of DHCP server pool beginning in text representation +#define WIFI_IP_DHCP_POOL_BEGIN_AP "192.168.0.100" +// IP Address of DHCP server pool end in text representation +#define WIFI_IP_DHCP_POOL_END_AP "192.168.0.200" +// DHCP lease time value in seconds +#define WIFI_IP_DHCP_LEASE_TIME_AP 3600 + +// Timeout configuration that can be used for adjusting tests to limitations of the WiFi Module (in ms) +#define WIFI_SOCKET_TIMEOUT 2000 +#define WIFI_SOCKET_TIMEOUT_LONG 35000 + +// Time that Access Point will wait for Client to connect to it (in ms) +#define WIFI_AP_CLIENT_CON_TIMEOUT 120000 + +#endif /* DV_WIFI_CONFIG_H_ */ diff --git a/Template/RTE/CMSIS_Driver_Validation/DV_WiFi_Config.h.base@1.1.0 b/Template/RTE/CMSIS_Driver_Validation/DV_WiFi_Config.h.base@1.1.0 new file mode 100644 index 0000000..30e68d0 --- /dev/null +++ b/Template/RTE/CMSIS_Driver_Validation/DV_WiFi_Config.h.base@1.1.0 @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2015-2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V1.1.0 + * + * Project: CMSIS-Driver Validation + * Title: WiFi driver validation configuration file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef DV_WIFI_CONFIG_H_ +#define DV_WIFI_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// WiFi +// WiFi driver validation configuration +// Driver_WiFi# <0-255> +// Choose the Driver_WiFi# instance to test. +// For example to test Driver_WiFi0 select 0. +#define DRV_WIFI 0 +// Configuration +// Configuration of valid settings for driver functionality testing +// Station +// Settings relevant for Station +// SSID +// SSID of network that Station will connect to +#define WIFI_STA_SSID "SSID" +// Password +// Password of network that Station will connect to +#define WIFI_STA_PASS "Password" +// Security Type +// <0=> Open <1=> WEP <2=> WPA <3=> WPA2 +// Security type of network that Station will connect to +#define WIFI_STA_SECURITY 3 +// Channel +// WiFi channel of network that Station will connect to +// Value 0 means Autodetect +#define WIFI_STA_CH 0 +// WPS PIN +// WiFi Protected Setup Personal Identification Number +#define WIFI_STA_WPS_PIN "12345678" +// +// Access Point +// Settings relevant for Access Point +// SSID +// SSID of created network +#define WIFI_AP_SSID "CMSIS_DV" +// Password +// Password of created network +#define WIFI_AP_PASS "Password" +// Security Type +// <0=> Open <1=> WEP <2=> WPA <3=> WPA2 +// Security type of created network +#define WIFI_AP_SECURITY 3 +// Channel +// WiFi channel of created network +// Value 0 means Autoselect +#define WIFI_AP_CH 0 +// WPS PIN +// WiFi Protected Setup Personal Identification Number +#define WIFI_AP_WPS_PIN "12345678" +// +// Socket +// Settings relevant for Socket testing +// SockServer IP +// Static IPv4 Address of SockServer +#define WIFI_SOCKET_SERVER_IP "192.168.1.10" +// Number of sockets +// Number of sockets that driver supports +// Default: 4 +#define WIFI_SOCKET_MAX_NUM 4 +// +// +// Tests +// Enable / disable tests. +// Control +// Control functions tests +#define WIFI_CONTROL_EN 1 +// WIFI_GetVersion +#define WIFI_GETVERSION_EN 1 +// WIFI_GetCapabilities +#define WIFI_GETCAPABILITIES_EN 1 +// WIFI_Initialization/Uninitialization +#define WIFI_INIT_UNINIT_EN 1 +// WIFI_PowerControl +#define WIFI_POWERCONTROL_EN 1 +// WIFI_GetModuleInfo +#define WIFI_GETMODULEINFO_EN 1 +// +// Management +// Management functions tests +#define WIFI_MANAGEMENT_EN 1 +// WIFI_SetOption/GetOption +#define WIFI_SETGETOPTION_EN 1 +// ARM_WIFI_BSSID <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_BSSID_STA/WIFI_BSSID_AP (1E-30-6C-A2-45-5E) +#define WIFI_SETGETOPTION_BSSID_EN 3 +// ARM_WIFI_TX_POWER <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_TX_POWER_STA/WIFI_TX_POWER_AP (16) +#define WIFI_SETGETOPTION_TX_POWER_EN 3 +// ARM_WIFI_LP_TIMER <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_LP_TIMER_STA (10) +#define WIFI_SETGETOPTION_LP_TIMER_EN 3 +// ARM_WIFI_DTIM <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_DTIM_STA/WIFI_DTIM_AP (3) +#define WIFI_SETGETOPTION_DTIM_EN 3 +// ARM_WIFI_BEACON <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_BEACON_AP (2000) +#define WIFI_SETGETOPTION_BEACON_EN 3 +// ARM_WIFI_MAC <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_MAC_STA/WIFI_MAC_AP (1E-30-6C-A2-45-5E) +#define WIFI_SETGETOPTION_MAC_EN 3 +// ARM_WIFI_IP <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_STA/WIFI_IP_AP (192.168.0.100) +#define WIFI_SETGETOPTION_IP_EN 3 +// ARM_WIFI_IP_SUBNET_MASK <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_SUBNET_MASK_STA/WIFI_IP_SUBNET_MASK_AP (255.255.255.0) +#define WIFI_SETGETOPTION_IP_SUBNET_MASK_EN 3 +// ARM_WIFI_IP_GATEWAY <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_GATEWAY_STA/WIFI_IP_GATEWAY_AP (192.168.0.254) +#define WIFI_SETGETOPTION_IP_GATEWAY_EN 3 +// ARM_WIFI_IP_DNS1 <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DNS1_STA/WIFI_IP_DNS1_AP (8.8.8.8) +#define WIFI_SETGETOPTION_IP_DNS1_EN 3 +// ARM_WIFI_IP_DNS2 <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DNS2_STA/WIFI_IP_DNS2_AP (8.8.4.4) +#define WIFI_SETGETOPTION_IP_DNS2_EN 3 +// ARM_WIFI_IP_DHCP <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +#define WIFI_SETGETOPTION_IP_DHCP_EN 3 +// ARM_WIFI_IP_DHCP_POOL_BEGIN <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DHCP_POOL_BEGIN_AP (192.168.0.100) +#define WIFI_SETGETOPTION_IP_DHCP_POOL_BEGIN_EN 3 +// ARM_WIFI_IP_DHCP_POOL_END <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DHCP_POOL_END_AP (192.168.0.200) +#define WIFI_SETGETOPTION_IP_DHCP_POOL_END_EN 3 +// ARM_WIFI_IP_DHCP_LEASE_TIME <0=>Disabled <1=>Set <2=>Get <3=>Set/Get +// Default test value is set in defines WIFI_IP_DHCP_LEASE_TIME_AP (3600) +#define WIFI_SETGETOPTION_IP_DHCP_LEASE_TIME_EN 3 +// +// WIFI_Scan +#define WIFI_SCAN_EN 1 +#define WIFI_SCAN_MAX_NUM 10 +// WIFI_Activate/Deactivate +#define WIFI_ACT_DEACT_EN 1 +// WIFI_IsConnected +#define WIFI_ISCONNECTED_EN 1 +// WIFI_GetNetInfo +#define WIFI_GETNETINFO_EN 1 +// +// Management (requires user interaction) +// Management functions tests that require user interaction +#define WIFI_MANAGEMENT_USER_EN 0 +// WIFI_Activate_AP +// For this test please connect a WiFi client (for example mobile phone) to AP +// and check if connection has succeeded +#define WIFI_ACT_AP 1 +// WPS +#define WIFI_WPS_USER_EN 1 +// WIFI_Activate_Station_WPS_PBC +// For this test please start WPS Push-button method on WiFi AP (router) manually +#define WIFI_ACT_STA_WPS_PBC 1 +// WIFI_Activate_Station_WPS_PIN +// For this test please configure WPS PIN method on WiFi AP (router) manually +#define WIFI_ACT_STA_WPS_PIN 1 +// WIFI_Activate_AP_WPS_PBC +// For this test please connect a WiFi client (for example mobile phone) to AP with WPS Push-button method +// and check if connection has succeeded +#define WIFI_ACT_AP_WPS_PBC 1 +// WIFI_Activate_AP_WPS_PIN +// For this test please connect a WiFi client (for example mobile phone) to AP with WPS PIN method +// and check if connection has succeeded +#define WIFI_ACT_AP_WPS_PIN 1 +// +// +// Socket API (requires SockServer) +// Socket functions tests +#define WIFI_SOCKET_EN 1 +// WIFI_SocketCreate +#define WIFI_SOCKETCREATE_EN 1 +// WIFI_SocketBind +#define WIFI_SOCKETBIND_EN 1 +// WIFI_SocketListen +#define WIFI_SOCKETLISTEN_EN 1 +// WIFI_SocketAccept +#define WIFI_SOCKETACCEPT_EN 1 +// WIFI_SocketAccept_nbio +#define WIFI_SOCKETACCEPT_NBIO_EN 1 +// WIFI_SocketConnect +#define WIFI_SOCKETCONNECT_EN 1 +// WIFI_SocketConnect_nbio +#define WIFI_SOCKETCONNECT_NBIO_EN 1 +// WIFI_SocketRecv +#define WIFI_SOCKETRECV_EN 1 +// WIFI_SocketRecv_nbio +#define WIFI_SOCKETRECV_NBIO_EN 1 +// WIFI_SocketRecvFrom +#define WIFI_SOCKETRECVFROM_EN 1 +// WIFI_SocketRecvFrom_nbio +#define WIFI_SOCKETRECVFROM_NBIO_EN 1 +// WIFI_SocketSend +#define WIFI_SOCKETSEND_EN 1 +// WIFI_SocketSendTo +#define WIFI_SOCKETSENDTO_EN 1 +// WIFI_SocketGetSockName +#define WIFI_SOCKETGETSOCKNAME_EN 1 +// WIFI_SocketGetPeerName +#define WIFI_SOCKETGETPEERNAME_EN 1 +// WIFI_SocketGetOpt +#define WIFI_SOCKETGETOPT_EN 1 +// WIFI_SocketSetOpt +#define WIFI_SOCKETSETOPT_EN 1 +// WIFI_SocketClose +#define WIFI_SOCKETCLOSE_EN 1 +// WIFI_SocketGetHostByName +#define WIFI_SOCKETGETHOSTBYNAME_EN 1 +// WIFI_Ping +#define WIFI_PING_EN 1 +// +// Socket Operation (requires SockServer) +// Socket operation tests +#define WIFI_SOCKET_OP_EN 1 +// WIFI_Transfer_Fixed +// Sends and receives in fixed size blocks +#define WIFI_TRANSFER_FIXED_EN 1 +// WIFI_Transfer_Incremental +// Sends and receives in ascending size blocks +#define WIFI_TRANSFER_INCREMENTAL_EN 1 +// WIFI_Send_Fragmented +// Sends several smaller blocks, receives one large block +#define WIFI_SEND_FRAGMENTED_EN 1 +// WIFI_Recv_Fragmented +// Sends one large block, receives several smaller blocks +#define WIFI_RECV_FRAGMENTED_EN 1 +// WIFI_Test_Speed +// Transmits data and measures transfer speed +#define WIFI_TEST_SPEED_EN 1 +// WIFI_Concurrent_Socket +// Transmits data in two sockets simultaneously +#define WIFI_CONCURRENT_SOCKET_EN 1 +// WIFI_Downstream_Rate +// Measures the downstream bandwidth +#define WIFI_DOWNSTREAM_RATE_EN 1 +// WIFI_Upstream_Rate +// Measures the upstream bandwidth +#define WIFI_UPSTREAM_RATE_EN 1 +// +// +// + +// Configuration settings of test values for Set/GetOptions +// BSSID +#define WIFI_BSSID_STA "1E-30-6C-A2-45-5E" +#define WIFI_BSSID_AP "1E-30-6C-A2-45-5E" +// Radio transmitting power in dBm +#define WIFI_TX_POWER_STA 16 +#define WIFI_TX_POWER_AP 16 +// Low-power deep-sleep time value in seconds +#define WIFI_LP_TIMER_STA 10 +// Delivery Traffic Indication Message interval value in beacons +#define WIFI_DTIM_STA 3 +#define WIFI_DTIM_AP 3 +// Beacon interval value in milliseconds +#define WIFI_BEACON_AP 2000 +// Ethernet MAC Address in text representation +#define WIFI_MAC_STA "1E-30-6C-A2-45-5E" +#define WIFI_MAC_AP "1E-30-6C-A2-45-5E" +// Static IPv4 Address in text representation +#define WIFI_IP_STA "192.168.0.100" +#define WIFI_IP_AP "192.168.0.100" +// Local Subnet mask in text representation +#define WIFI_IP_SUBNET_MASK_STA "255.255.255.0" +#define WIFI_IP_SUBNET_MASK_AP "255.255.255.0" +// IP Address of Default Gateway in text representation +#define WIFI_IP_GATEWAY_STA "192.168.0.254" +#define WIFI_IP_GATEWAY_AP "192.168.0.254" +// IP Address of Primary DNS Server in text representation +#define WIFI_IP_DNS1_STA "8.8.8.8" +#define WIFI_IP_DNS1_AP "8.8.8.8" +// IP Address of Secondary DNS Server in text representation +#define WIFI_IP_DNS2_STA "8.8.4.4" +#define WIFI_IP_DNS2_AP "8.8.4.4" +// IP Address of DHCP server pool beginning in text representation +#define WIFI_IP_DHCP_POOL_BEGIN_AP "192.168.0.100" +// IP Address of DHCP server pool end in text representation +#define WIFI_IP_DHCP_POOL_END_AP "192.168.0.200" +// DHCP lease time value in seconds +#define WIFI_IP_DHCP_LEASE_TIME_AP 3600 + +// Timeout configuration that can be used for adjusting tests to limitations of the WiFi Module (in ms) +#define WIFI_SOCKET_TIMEOUT 2000 +#define WIFI_SOCKET_TIMEOUT_LONG 35000 + +// Time that Access Point will wait for Client to connect to it (in ms) +#define WIFI_AP_CLIENT_CON_TIMEOUT 120000 + +#endif /* DV_WIFI_CONFIG_H_ */ diff --git a/Template/app_main.c b/Template/app_main.c new file mode 100644 index 0000000..c1cd00e --- /dev/null +++ b/Template/app_main.c @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#include "app_main.h" + +#include "cmsis_os2.h" + +#include "cmsis_dv.h" + +// Main stack size must be multiple of 8 Bytes +#define APP_MAIN_STK_SZ (4096U) +static uint64_t app_main_stk[APP_MAIN_STK_SZ / 8]; +static const osThreadAttr_t app_main_attr = { + .stack_mem = &app_main_stk[0], + .stack_size = sizeof(app_main_stk) +}; + +/*--------------------------------------------------------------------------- + * Application main thread + *---------------------------------------------------------------------------*/ +void app_main_thread (void *argument) { + (void)argument; + + cmsis_dv(NULL); // Execute tests + + osThreadExit(); +} + +/*--------------------------------------------------------------------------- + * Application main function + *---------------------------------------------------------------------------*/ +int32_t app_main (void) { + osKernelInitialize(); + osThreadNew(app_main_thread, NULL, &app_main_attr); + osKernelStart(); + return 0; +} diff --git a/Template/app_main.h b/Template/app_main.h new file mode 100644 index 0000000..c2f29b3 --- /dev/null +++ b/Template/app_main.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_MAIN_H_ +#define APP_MAIN_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +extern int32_t app_main (void); + +#ifdef __cplusplus +} +#endif + +#endif // APP_MAIN_H_ diff --git a/gen_pack.sh b/gen_pack.sh index 5ed65c2..cfebbad 100755 --- a/gen_pack.sh +++ b/gen_pack.sh @@ -34,6 +34,7 @@ PACK_DIRS=" Documentation Include Source + Template Tools "