diff --git a/ARM.CMSIS-Driver_Validation.pdsc b/ARM.CMSIS-Driver_Validation.pdsc index c2f4d1e..fd08806 100644 --- a/ARM.CMSIS-Driver_Validation.pdsc +++ b/ARM.CMSIS-Driver_Validation.pdsc @@ -16,6 +16,7 @@ - Update USART Server application to CMSIS solution format - Add USART Server application template - Remove XML report format + - Remove obsolete SockServer embedded implementations - Improve Ethernet driver validation - Minor update to SPI driver validation - Minor update to USART driver validation diff --git a/Documentation/Doxygen/src/DV_WiFi.txt b/Documentation/Doxygen/src/DV_WiFi.txt index 4aa750d..46cd028 100644 --- a/Documentation/Doxygen/src/DV_WiFi.txt +++ b/Documentation/Doxygen/src/DV_WiFi.txt @@ -5,8 +5,7 @@ The WiFi driver validation requires the following hardware: - WiFi Access Point connected to the local network -- Hardware running SockServer (can be \ref sockserver_pc "PC running Microsoft Windows" or an - \ref sockserver_embedded "embedded system") +- \ref sockserver_pc "PC running Microsoft Windows" The WiFi driver validation requires the following software: - \ref wifi_sock_setup "SockServer" application running in the same network as WiFi Access Point used for testing @@ -18,10 +17,10 @@ The WiFi driver validation requires the following software: \defgroup wifi_config Configuration \ingroup dv_wifi -The WiFi driver validation settings are available in the DV_WiFi_Config.h configuration file. +The WiFi driver validation settings are available in the **DV_WiFi_Config.h** configuration file. Some settings depend on the test environment and need to be changed for proper operation of the WiFi driver validation.
-These settings can be found under Configuration settings in the DV_WiFi_Config.h configuration file and need to +These settings can be found under **Configuration** settings in the **DV_WiFi_Config.h** configuration file and need to be set as follows: \image html dv_wifi_config_h.png "DV_WiFi_Config.h configuration file in Configuration Wizard view mode" @@ -46,17 +45,17 @@ be set as follows: \note IP address is displayed by the SockServer application (on the embedded board's LCD when using embedded SockServer). -Under Tests select testing functionality as required. +Under **Tests** select testing functionality as required. For details on tests performed by each test function please refer to \ref wifi_tests "WiFi Tests". -Control, Management and Socket API (requires SockServer) group of tests enable or disable +Control, **Management** and **Socket API (requires SockServer)** group of tests enable or disable WiFi Driver API function tests respectively. -Management (requires user interaction) and Socket Operation (requires SockServer) group of tests +Management (requires user interaction) and **Socket Operation (requires SockServer)** group of tests are used for more complex operational test of the WiFi driver.
A brief description of each test functionality can be viewed by using Configuration Wizard -view of the DV_WiFi_Config.h file and clicking on the test or hovering a mouse pointer over it. +view of the **DV_WiFi_Config.h** file and clicking on the test or hovering a mouse pointer over it. */ @@ -67,15 +66,10 @@ view of the DV_WiFi_Config.h file and clicking on the test or hovering a \ingroup dv_wifi The \b SockServer is an application providing a set of services used by the WiFi CMSIS-Driver Validation suite to test the -Socket interface of the WiFi driver. It is located in the .\\Tools\\SockServer subdirectory of the pack root directory. +Socket interface of the WiFi driver. It is located in the **`/Tools/SockServer`** subdirectory of the pack root directory. The SockServer is available for different target systems. It runs several standard network services. -The SockServer is available for following target systems: - - Personal Computer running Microsoft Windows (executable located in .\\Tools\\SockServer\\PC\\Win) - - Keil MCB4300 evaluation board (µVision project located in .\\Tools\\SockServer\\Embedded\\MDK\\Board\\MCB4300) - - Keil MCBSTM32F400 evaluation board (µVision project located in .\\Tools\\SockServer\\Embedded\\MDK\\Board\\MCBSTM32F400) - -\note To run SockServer in an embedded system, you need a license for MDK-Professional (for the MDK-Middleware Network component). +The **SockServer** is available for **Personal Computer** running Microsoft Windows (executable located in **`/Tools/SockServer/PC/Win`**). The following services are available by SockServer: - \b Echo service on port \token{7}, TCP and UDP @@ -89,26 +83,24 @@ The following services are available by SockServer: - \b Telnet service on port \token{23} \n (SockServer status monitoring service) -\note SockServer provides the Telnet service only in embedded systems. - \section sockserver_pc SockServer for PC running Microsoft Windows \b Requirements: - Personal Computer running Microsoft Windows - PC connection to local network -SockServer is already built and can be executed by running the SockServer.exe file in .\\Tools\\SockServer\\PC\\Win +SockServer is already built and can be executed by running the **SockServer.exe** file in **`/Tools/SockServer/PC/Win`**. If you need to change the functionality of SockServer, source files and a batch script for building the executable are -available in .\\Tools\\SockServer\\PC\\Win. +available in **`/Tools/SockServer/PC/Win`**. \note - SockServer build process requires Minimalist GNU for Windows (MinGW). - To build the SockServer executable for Windows, follow these steps: - Download and install MinGW from https://winlibs.com/ - Set environment path in Microsoft Windows as explained under Usage heading on https://winlibs.com/#usage - - Run Build.bat located in .\\Tools\\SockServer\\PC\\Win which will result in an executable that is located in - .\\Tools\\SockServer\\PC\\Win + - Run **Build.bat** located in **`/Tools/SockServer/PC/Win`** which will result in an executable that is located + in **`/Tools/SockServer/PC/Win`** \subsection sockserver_pc_win_troubleshooting Troubleshooting @@ -137,104 +129,6 @@ Problems and solutions: - Profile: Domain, Private (Public not advised) - Name: Ping Echo - -\section sockserver_embedded SockServer for embedded systems - -\b Requirements: - - Keil MCB4300 or Keil MCBSTM32F400 evaluation board - - Wired Ethernet connection to local network - -\subsection sockserver_embedded_telnet Using the Telnet service - -The Telnet service provides information about received and sent data. This can help to resolve driver problems when WiFi -socket sending and receiving does not work. For example, when the transfer test fails, either \b SocketSend or -\b SocketRecv functions may have failed or both. - -For the Telnet connection from the PC, open a CMD window. At the prompt, type the following command or use another Telnet -client application: -\code -c:\>telnet sockserver -\endcode - -The initial page opens: - \image html SockServer.png "Initial telnet connection" - -You can view the remote IP address, port number, receiving and transmitting counters with the \b stat command: - \image html SockMonitor.png "Status monitoring" - -Status monitor constantly updates the SockServer status on the screen. To stop the screen update, press any -telnet client key. - -\note You might need to enable the Telnet service in Windows 10 first. Here's a -tutorial on how to do this. - -\subsection sockserver_embedded_porting Porting SockServer to other targets - -Currently, the \b SockServer application is available for the \b MCB4300 and \b MCBSTM32F400 evaluation boards. -To create SockServer application for a different target device, follow the steps below: --# Create new network project in µVision --# Select and configure the following software components: - - \b Network:Core and configure the host name and pool size in \b Net_Config.c -\code -#define NET_HOST_NAME "SockServer" -#define NET_MEM_POOL_SIZE 16384 -\endcode - - \b Network:Interface:Ethernet and configure the MAC address in \b Net_Config_ETH0.h to avoid collisions -\code -#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5A" -\endcode - - \b Network:Socket:BSD and configure number of sockets in \b Net_Config_BSD.h -\code -#define BSD_NUM_SOCKS 8 -#define BSD_SERVER_SOCKS 4 -\endcode - - \b Network:Socket:TCP and configure number of sockets in \b Net_Config_TCP.h -\code -#define TCP_NUM_SOCKS 9 -\endcode - - \b Network:Socket:UDP and configure number of sockets in \b Net_Config_UDP.h -\code -#define UDP_NUM_SOCKS 10 -\endcode - - \b Network:Service:Telnet server and disable authentication in \b Net_Config_Telnet_Server.h -\code -#define TELNET_SERVER_AUTH_ENABLE 0 -\endcode - - \b CMSIS \b Driver:Ethernet/MAC/PHY(API) depending on your hardware --# Configure device specific hardware: - - Configure the CMSIS-Driver for Ethernet and other device specific components (clock system, I/O, ...) - as required. Please consult your device's/board's documentation for more information. --# Copy and add \b SockServer.c and \b SockServer.h files to the project --# Copy and add \b Telnet_Server_UIF.c to the project --# Add the code to start the services in \b main.c -\code -// Application main thread -static void app_main (void *argument) { - - netInitialize (); - osDelay (500); - - osThreadNew(DgramServer, NULL, NULL); - osThreadNew(StreamServer, NULL, NULL); - osThreadNew(TestAssistant, NULL, NULL); -} -\endcode --# Increase the default RTX stack size to 400 bytes in RTX_Config.h -\code -#define OS_STACK_SIZE 400 -\endcode --# Set the default global stack to 1024 bytes and heap to 6144 bytes in your device's \b startup \b file -\code -Stack_Size EQU 0x00000400 -Heap_Size EQU 0x00001800 -\endcode - -\subsection sockserver_embedded_troubleshooting Troubleshooting - -Problems and solutions: - 1. SockServer on multiple embedded systems on the same local network - - Set unique ETH0_MAC_ADDR in Net_Config_ETH0.h for each embedded system in embedded system project - */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/Abstract.txt b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/Abstract.txt deleted file mode 100644 index 1c2def3..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/Abstract.txt +++ /dev/null @@ -1,67 +0,0 @@ -This is socket test server example. -The example runs both CHARGEN and ECHO servers for TCP and UDP. -It is based on MW-Network and uses BSD sockets for the implementation. - -The SockServer is able to accept 7 connections simultaneously: -- 2 concurrent TCP echo sessions, -- 2 concurrent TCP chargen sessions, -- 1 concurrent TCP discard session, -- 1 socket UDP echo session, -- 1 socket UDP chargen session, -- 1 socket TCP test assistant session. - -Note: -- Use Network system viewer to see the assigned IP address of the server. -- Character ESC (0x1b) terminates TCP session. - - -ECHO -==== -Open a telnet session to your test platform at port 7. -For example: - -telnet 192.168.1.100 7 - -Then, enter in the telnet a few characters and you will see that the characters -are echoed back to you. In telnet you will see all duplicate characters: - -aabbccddee -kkwwaa -tteesstt - - -CHARGEN -======= - -Open a telnet session to your test platform at port 19. -For example: - -telnet 192.168.1.100 19 - -You will see a pattern similar to the following on streaming by on your -screen: - -ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01 -BCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012 -CDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123 -DEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01234 -EFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012345 -FGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456 -GHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01234567 -HIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012345678 -IJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789 -JKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789: -KLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:; -LMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:;< -MNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:;<= - - -DISCARD -======= - -Open a telnet session to your test platform at port 9. -For example: - -telnet 192.168.1.100 9 - -The service discards all received characters. diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/Board_IO/retarget_stdio.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/Board_IO/retarget_stdio.c deleted file mode 100644 index d564c00..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/Board_IO/retarget_stdio.c +++ /dev/null @@ -1,74 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * -------------------------------------------------------------------------- */ - -#include -#include "fsl_debug_console.h" // NXP::Device:SDK Utilities:debug_console - -int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); -int DbgConsole_ReadCharacter(uint8_t *ch); - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - int32_t ret; - - ret = DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); - - if (ret!= -1) { - ret = ch; - } - return (ret); -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - int32_t ret; - - ret = DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); - - if (ret!= -1) { - ret = ch; - } - return (ret); -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - int32_t ret; - uint8_t ch; - - ret = DbgConsole_ReadCharacter(&ch); - - if (ret!= -1) { - ret = ch; - } - return (ret); -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/IMXRT1050-EVKB.mex b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/IMXRT1050-EVKB.mex deleted file mode 100644 index 09d381a..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/IMXRT1050-EVKB.mex +++ /dev/null @@ -1,1427 +0,0 @@ - - - - MIMXRT1052xxxxB - MIMXRT1052DVL6B - IMXRT1050-EVKB - ksdk2_0 - - - - - - - true - false - false - true - false - - - - - - - - - 11.0.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - false - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - Configures pin routing and optionally pin electrical features. - - true - core0 - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11.0.1 - - - - - - - - - true - - - - - INPUT - - - - - true - - - - - OUTPUT - - - - - true - - - - - INPUT - - - - - true - - - - - OUTPUT - - - - - true - - - - - true - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - true - - - - - - - - - - 11.0.1 - c_array - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10.0.0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N/A - - - - \ No newline at end of file diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/board.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/board.c deleted file mode 100644 index 0f4335c..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/board.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_debug_console.h" -#include "board.h" -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -#include "fsl_lpi2c.h" -#endif /* SDK_I2C_BASED_COMPONENT_USED */ -#include "fsl_iomuxc.h" -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get debug console frequency. */ -uint32_t BOARD_DebugConsoleSrcFreq(void) -{ - uint32_t freq; - - /* To make it simple, we assume default PLL and divider settings, and the only variable - from application is use PLL3 source or OSC source */ - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ - { - freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { - freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - - return freq; -} - -/* Initialize debug console. */ -void BOARD_InitDebugConsole(void) -{ - uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq(); - - DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); -} - -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) -{ - lpi2c_master_config_t lpi2cConfig = {0}; - - /* - * lpi2cConfig.debugEnable = false; - * lpi2cConfig.ignoreAck = false; - * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; - * lpi2cConfig.baudRate_Hz = 100000U; - * lpi2cConfig.busIdleTimeout_ns = 0; - * lpi2cConfig.pinLowTimeout_ns = 0; - * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; - * lpi2cConfig.sclGlitchFilterWidth_ns = 0; - */ - LPI2C_MasterGetDefaultConfig(&lpi2cConfig); - LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); -} - -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *txBuff, - uint8_t txBuffSize) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = txBuff; - xfer.dataSize = txBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Read; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = rxBuff; - xfer.dataSize = rxBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *txBuff, - uint8_t txBuffSize) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = txBuff; - xfer.dataSize = txBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize) -{ - status_t status; - lpi2c_master_transfer_t xfer; - - xfer.flags = kLPI2C_TransferDefaultFlag; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = NULL; - xfer.dataSize = 0; - - status = LPI2C_MasterTransferBlocking(base, &xfer); - - if (kStatus_Success == status) - { - xfer.subaddressSize = 0; - xfer.direction = kLPI2C_Read; - xfer.data = rxBuff; - xfer.dataSize = rxBuffSize; - - status = LPI2C_MasterTransferBlocking(base, &xfer); - } - - return status; -} - -void BOARD_Accel_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ); -} - -status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff) -{ - uint8_t data = (uint8_t)txBuff; - - return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1); -} - -status_t BOARD_Accel_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize); -} - -void BOARD_Codec_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); -} - -status_t BOARD_Codec_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Codec_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); -} - -void BOARD_Camera_I2C_Init(void) -{ - CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT); - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER); - BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ); -} - -status_t BOARD_Camera_I2C_Send( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Camera_I2C_Receive( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, - rxBuffSize); -} - -status_t BOARD_Camera_I2C_SendSCCB( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) -{ - return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize); -} - -status_t BOARD_Camera_I2C_ReceiveSCCB( - uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) -{ - return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, - rxBuffSize); -} -#endif /* SDK_I2C_BASED_COMPONENT_USED */ - -/* MPU configuration. */ -void BOARD_ConfigMPU(void) -{ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$RW_m_ncache$$Base[]; - /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ - extern uint32_t Image$$RW_m_ncache_unused$$Base[]; - extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; - uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; - uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? - 0 : - ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); -#elif defined(__MCUXPRESSO) - extern uint32_t __base_NCACHE_REGION; - extern uint32_t __top_NCACHE_REGION; - uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); - uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; -#elif defined(__ICCARM__) || defined(__GNUC__) - extern uint32_t __NCACHE_REGION_START[]; - extern uint32_t __NCACHE_REGION_SIZE[]; - uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; - uint32_t size = (uint32_t)__NCACHE_REGION_SIZE; -#endif - volatile uint32_t i = 0; - - /* Disable I cache and D cache */ - if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) - { - SCB_DisableICache(); - } - if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) - { - SCB_DisableDCache(); - } - - /* Disable MPU */ - ARM_MPU_Disable(); - - /* MPU configure: - * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, - * SubRegionDisable, Size) - * API in mpu_armv7.h. - * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches - * disabled. - * param AccessPermission Data access permissions, allows you to configure read/write access for User and - * Privileged mode. - * Use MACROS defined in mpu_armv7.h: - * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO - * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. - * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache - * 0 x 0 0 Strongly Ordered shareable - * 0 x 0 1 Device shareable - * 0 0 1 0 Normal not shareable Outer and inner write - * through no write allocate - * 0 0 1 1 Normal not shareable Outer and inner write - * back no write allocate - * 0 1 1 0 Normal shareable Outer and inner write - * through no write allocate - * 0 1 1 1 Normal shareable Outer and inner write - * back no write allocate - * 1 0 0 0 Normal not shareable outer and inner - * noncache - * 1 1 0 0 Normal shareable outer and inner - * noncache - * 1 0 1 1 Normal not shareable outer and inner write - * back write/read acllocate - * 1 1 1 1 Normal shareable outer and inner write - * back write/read acllocate - * 2 x 0 0 Device not shareable - * Above are normal use settings, if your want to see more details or want to config different inner/outter cache - * policy. - * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide - * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. - * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in - * mpu_armv7.h. - */ - - /* - * Add default region to deny access to whole address space to workaround speculative prefetch. - * Refer to Arm errata 1013783-B for more details. - * - */ - /* Region 0 setting: Instruction access disabled, No data access permission. */ - MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); - - /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) - /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */ - MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); -#endif - - /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - - /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - - /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); - - while ((size >> i) > 0x1U) - { - i++; - } - - if (i != 0) - { - /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ - assert(!(nonCacheStart % size)); - assert(size == (uint32_t)(1 << i)); - assert(i >= 5); - - /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); - } - - /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB); - - /* Enable MPU */ - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - /* Enable I cache and D cache */ - SCB_EnableDCache(); - SCB_EnableICache(); -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/board.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/board.h deleted file mode 100644 index 8fdfdb0..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/board.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#include "clock_config.h" -#include "fsl_common.h" -#include "fsl_gpio.h" -#include "fsl_clock.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief The board name */ -#define BOARD_NAME "IMXRT1050-EVKB" - -/* The UART to use for debug messages. */ -#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart -#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 -#define BOARD_DEBUG_UART_INSTANCE 1U - -#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() - -#define BOARD_UART_IRQ LPUART1_IRQn -#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler - -#ifndef BOARD_DEBUG_UART_BAUDRATE -#define BOARD_DEBUG_UART_BAUDRATE (115200U) -#endif /* BOARD_DEBUG_UART_BAUDRATE */ - -/*! @brief The USER_LED used for board */ -#define LOGIC_LED_ON (0U) -#define LOGIC_LED_OFF (1U) -#ifndef BOARD_USER_LED_GPIO -#define BOARD_USER_LED_GPIO GPIO1 -#endif -#ifndef BOARD_USER_LED_GPIO_PIN -#define BOARD_USER_LED_GPIO_PIN (9U) -#endif - -#define USER_LED_INIT(output) \ - GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ - BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ -#define USER_LED_ON() \ - GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ -#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 3); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 0); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 63); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 2); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 0); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 62); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 1); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) - #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." -#endif - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 27); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* Init Audio PLL. */ - uint32_t pllAudio; - /* Disable Audio PLL output before initial Audio PLL. */ - CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* Bypass PLL first */ - CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | - CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(0); - CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(77); - CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(100); - pllAudio = (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | - CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(32); - pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - CCM_ANALOG->PLL_AUDIO = pllAudio; - while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) - { - } - /* Disable bypass for Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 0); - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* Init Enet PLL. */ - CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN); - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Ref clock source. */ -#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) - IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; -#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) - /* Backward compatibility for original bitfield name */ - IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; -#else -#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." -#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/clock_config.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/clock_config.h deleted file mode 100644 index 8b257af..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/clock_config.h +++ /dev/null @@ -1,120 +0,0 @@ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 50000000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 25000000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 50000000UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 56842105UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 12288750UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 12288750UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 12288750UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 8067226UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 8067226UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 163862068UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 163862068UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; -/*! @brief Audio PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_audio_pll_config_t audioPllConfig_BOARD_BootClockRUN; -/*! @brief Enet PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ - diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/dcd.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/dcd.c deleted file mode 100644 index a023d4e..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/dcd.c +++ /dev/null @@ -1,308 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#include "dcd.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.dcd_data"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.dcd_data" -#endif - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: DCDx v3.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 11.0.1 -board: IMXRT1050-EVKB -output_format: c_array - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ -const uint8_t dcd_data[] = { - /* HEADER */ - /* Tag */ - 0xD2, - /* Image Length */ - 0x04, 0x10, - /* Version */ - 0x41, - - /* COMMANDS */ - - /* group: 'Imported Commands' */ - /* #1.1-113, command header bytes for merged 'Write - value' command */ - 0xCC, 0x03, 0x8C, 0x04, - /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ - 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, - /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ - 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, - /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x98D40, size: 4 */ - 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x09, 0x8D, 0x40, - /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, - /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, - /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, - /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, - /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, - /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, - /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, - /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, - /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, - /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, - /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, - /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, - /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, - /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, - /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, - /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, - /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, - /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, - /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, - /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, - /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, - /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, - /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, - /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, - /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, - /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, - /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, - /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, - /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, - /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, - /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, - /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, - /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, - /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, - /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, - /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, - /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, - /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, - /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ - 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, - /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, - /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, - /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, - /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, - /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, - /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, - /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, - /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, - /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, - /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, - /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, - /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, - /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, - /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, - /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, - /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, - /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, - /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, - /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, - /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, - /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, - /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, - /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, - /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, - /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, - /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, - /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, - /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, - /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, - /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, - /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, - /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, - /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, - /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, - /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, - /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, - /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, - /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, - /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, - /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, - /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ - 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, - /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, - /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, - /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, - /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, - /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, - /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ - 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, - /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ - 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, - /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ - 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, - /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, - /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, - /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ - 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, - /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ - 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, - /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, - /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ - 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, - /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, - /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, - /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ - 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, - /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ - 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, - /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, - /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #3.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #5.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #7.1-3, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x1C, 0x04, - /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ - 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, - /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, - /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 - }; -/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ - -#else -const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/dcd.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/dcd.h deleted file mode 100644 index 3d8b7cd..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/dcd.h +++ /dev/null @@ -1,25 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef __DCD__ -#define __DCD__ - -#include - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/************************************* - * DCD Data - *************************************/ -#define DCD_TAG_HEADER (0xD2) -#define DCD_VERSION (0x41) -#define DCD_TAG_HEADER_SHIFT (24) -#define DCD_ARRAY_SIZE 1 - -#endif /* __DCD__ */ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/peripherals.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/peripherals.c deleted file mode 100644 index 66899c2..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/peripherals.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2017-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Peripherals v8.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 0.8.2 -board: IMXRT1050-EVKB -functionalGroups: -- name: BOARD_InitPeripherals - UUID: a7525270-2da6-4556-8d91-4ab9d0edc0e2 - called_from_default_init: true - selectedCore: core0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/*********************************************************************************************************************** - * Included files - **********************************************************************************************************************/ -#include "peripherals.h" - -/*********************************************************************************************************************** - * Initialization functions - **********************************************************************************************************************/ -void BOARD_InitPeripherals(void) -{ -} - -/*********************************************************************************************************************** - * BOARD_InitBootPeripherals function - **********************************************************************************************************************/ -void BOARD_InitBootPeripherals(void) -{ - BOARD_InitPeripherals(); -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/peripherals.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/peripherals.h deleted file mode 100644 index c2a309b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/peripherals.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2017-2020 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PERIPHERALS_H_ -#define _PERIPHERALS_H_ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*********************************************************************************************************************** - * Initialization functions - **********************************************************************************************************************/ -void BOARD_InitPeripherals(void); - -/*********************************************************************************************************************** - * BOARD_InitBootPeripherals function - **********************************************************************************************************************/ -void BOARD_InitBootPeripherals(void); - -#if defined(__cplusplus) -} -#endif - -#endif /* _PERIPHERALS_H_ */ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/pin_mux.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/pin_mux.c deleted file mode 100644 index 64994d4..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/pin_mux.c +++ /dev/null @@ -1,977 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v11.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 11.0.1 -board: IMXRT1050-EVKB -pin_labels: -- {pin_num: E3, pin_signal: GPIO_EMC_00, label: SEMC_D0, identifier: SEMC_D0} -- {pin_num: F3, pin_signal: GPIO_EMC_01, label: SEMC_D1, identifier: SEMC_D1} -- {pin_num: F4, pin_signal: GPIO_EMC_02, label: SEMC_D2, identifier: SEMC_D2} -- {pin_num: F2, pin_signal: GPIO_EMC_04, label: SEMC_D4, identifier: SEMC_D4} -- {pin_num: G4, pin_signal: GPIO_EMC_03, label: SEMC_D3, identifier: SEMC_D3} -- {pin_num: G5, pin_signal: GPIO_EMC_05, label: SEMC_D5, identifier: SEMC_D5} -- {pin_num: H5, pin_signal: GPIO_EMC_06, label: SEMC_D6, identifier: SEMC_D6} -- {pin_num: H4, pin_signal: GPIO_EMC_07, label: SEMC_D7, identifier: SEMC_D7} -- {pin_num: H3, pin_signal: GPIO_EMC_08, label: SEMC_DM0, identifier: SEMC_DM0} -- {pin_num: C2, pin_signal: GPIO_EMC_09, label: SEMC_A0, identifier: SEMC_A0} -- {pin_num: G1, pin_signal: GPIO_EMC_10, label: SEMC_A1, identifier: SEMC_A1} -- {pin_num: G3, pin_signal: GPIO_EMC_11, label: SEMC_A2, identifier: SEMC_A2} -- {pin_num: H1, pin_signal: GPIO_EMC_12, label: SEMC_A3, identifier: SEMC_A3} -- {pin_num: A6, pin_signal: GPIO_EMC_13, label: SEMC_A4, identifier: SEMC_A4} -- {pin_num: B6, pin_signal: GPIO_EMC_14, label: SEMC_A5, identifier: SEMC_A5} -- {pin_num: B1, pin_signal: GPIO_EMC_15, label: SEMC_A6, identifier: SEMC_A6} -- {pin_num: A5, pin_signal: GPIO_EMC_16, label: SEMC_A7, identifier: SEMC_A7} -- {pin_num: A4, pin_signal: GPIO_EMC_17, label: SEMC_A8, identifier: SEMC_A8} -- {pin_num: B2, pin_signal: GPIO_EMC_18, label: SEMC_A9, identifier: SEMC_A9} -- {pin_num: B4, pin_signal: GPIO_EMC_19, label: SEMC_A11, identifier: SEMC_A11} -- {pin_num: G2, pin_signal: GPIO_EMC_23, label: SEMC_A10, identifier: SEMC_A10} -- {pin_num: A3, pin_signal: GPIO_EMC_20, label: SEMC_A12, identifier: SEMC_A12} -- {pin_num: C1, pin_signal: GPIO_EMC_21, label: SEMC_BA0, identifier: SEMC_BA0} -- {pin_num: F1, pin_signal: GPIO_EMC_22, label: SEMC_BA1, identifier: SEMC_BA1} -- {pin_num: D3, pin_signal: GPIO_EMC_24, label: SEMC_CAS, identifier: SEMC_CAS} -- {pin_num: D2, pin_signal: GPIO_EMC_25, label: SEMC_RAS, identifier: SEMC_RAS} -- {pin_num: B3, pin_signal: GPIO_EMC_26, label: SEMC_CLK, identifier: SEMC_CLK} -- {pin_num: A2, pin_signal: GPIO_EMC_27, label: SEMC_CKE, identifier: SEMC_CKE} -- {pin_num: D1, pin_signal: GPIO_EMC_28, label: SEMC_WE, identifier: SEMC_WE} -- {pin_num: E1, pin_signal: GPIO_EMC_29, label: SEMC_CS0, identifier: SEMC_CS0} -- {pin_num: C6, pin_signal: GPIO_EMC_30, label: SEMC_D8, identifier: SEMC_D8} -- {pin_num: C5, pin_signal: GPIO_EMC_31, label: SEMC_D9, identifier: SEMC_D9} -- {pin_num: D5, pin_signal: GPIO_EMC_32, label: SEMC_D10, identifier: SEMC_D10} -- {pin_num: C4, pin_signal: GPIO_EMC_33, label: SEMC_D11, identifier: SEMC_D11} -- {pin_num: D4, pin_signal: GPIO_EMC_34, label: SEMC_D12, identifier: SEMC_D12} -- {pin_num: E5, pin_signal: GPIO_EMC_35, label: SEMC_D13, identifier: SEMC_D13} -- {pin_num: C3, pin_signal: GPIO_EMC_36, label: SEMC_D14, identifier: SEMC_D14} -- {pin_num: E4, pin_signal: GPIO_EMC_37, label: SEMC_D15, identifier: SEMC_D15} -- {pin_num: D6, pin_signal: GPIO_EMC_38, label: SEMC_DM1, identifier: SEMC_DM1} -- {pin_num: B7, pin_signal: GPIO_EMC_39, label: SEMC_DQS, identifier: SEMC_DQS} -- {pin_num: A7, pin_signal: GPIO_EMC_40, label: ENET_MDC, identifier: ENET_MDC} -- {pin_num: C7, pin_signal: GPIO_EMC_41, label: ENET_MDIO, identifier: ENET_MDIO} -- {pin_num: D7, pin_signal: GPIO_B0_00, label: LCDIF_CLK, identifier: LCDIF_CLK} -- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: LCDIF_ENABLE} -- {pin_num: E8, pin_signal: GPIO_B0_02, label: LCDIF_HSYNC, identifier: LCDIF_HSYNC} -- {pin_num: D8, pin_signal: GPIO_B0_03, label: LCDIF_VSYNC, identifier: LCDIF_VSYNC} -- {pin_num: C8, pin_signal: GPIO_B0_04, label: 'LCDIF_D0/BT_CFG[0]', identifier: LCDIF_D0} -- {pin_num: B8, pin_signal: GPIO_B0_05, label: 'LCDIF_D1/BT_CFG[1]', identifier: LCDIF_D1} -- {pin_num: A8, pin_signal: GPIO_B0_06, label: 'LCDIF_D2/BT_CFG[2]', identifier: LCDIF_D2} -- {pin_num: A9, pin_signal: GPIO_B0_07, label: 'LCDIF_D3/BT_CFG[3]', identifier: LCDIF_D3} -- {pin_num: B9, pin_signal: GPIO_B0_08, label: 'LCDIF_D4/BT_CFG[4]', identifier: LCDIF_D4} -- {pin_num: C9, pin_signal: GPIO_B0_09, label: 'LCDIF_D5/BT_CFG[5]', identifier: LCDIF_D5} -- {pin_num: D9, pin_signal: GPIO_B0_10, label: 'LCDIF_D6/BT_CFG[6]', identifier: LCDIF_D6} -- {pin_num: A10, pin_signal: GPIO_B0_11, label: 'LCDIF_D7/BT_CFG[7]', identifier: LCDIF_D7} -- {pin_num: C10, pin_signal: GPIO_B0_12, label: 'LCDIF_D8/BT_CFG[8]', identifier: LCDIF_D8} -- {pin_num: D10, pin_signal: GPIO_B0_13, label: 'LCDIF_D9/BT_CFG[9]', identifier: LCDIF_D9} -- {pin_num: E10, pin_signal: GPIO_B0_14, label: 'LCDIF_D10/BT_CFG[10]', identifier: LCDIF_D10} -- {pin_num: E11, pin_signal: GPIO_B0_15, label: 'LCDIF_D11/BT_CFG[11]', identifier: LCDIF_D11} -- {pin_num: A11, pin_signal: GPIO_B1_00, label: LCDIF_D12, identifier: LCDIF_D12} -- {pin_num: B11, pin_signal: GPIO_B1_01, label: LCDIF_D13, identifier: LCDIF_D13} -- {pin_num: C11, pin_signal: GPIO_B1_02, label: LCDIF_D14, identifier: LCDIF_D14} -- {pin_num: D11, pin_signal: GPIO_B1_03, label: LCDIF_D15, identifier: LCDIF_D15} -- {pin_num: E12, pin_signal: GPIO_B1_04, label: ENET_RXD0, identifier: ENET_RXD0} -- {pin_num: D12, pin_signal: GPIO_B1_05, label: ENET_RXD1, identifier: ENET_RXD1} -- {pin_num: C12, pin_signal: GPIO_B1_06, label: ENET_CRS_DV, identifier: ENET_CRS_DV} -- {pin_num: B12, pin_signal: GPIO_B1_07, label: ENET_TXD0, identifier: ENET_TXD0} -- {pin_num: A12, pin_signal: GPIO_B1_08, label: ENET_TXD1, identifier: ENET_TXD1} -- {pin_num: A13, pin_signal: GPIO_B1_09, label: ENET_TXEN, identifier: ENET_TXEN} -- {pin_num: B13, pin_signal: GPIO_B1_10, label: ENET_TX_CLK, identifier: ENET_TX_CLK} -- {pin_num: C13, pin_signal: GPIO_B1_11, label: ENET_RXER, identifier: ENET_RXER} -- {pin_num: D13, pin_signal: GPIO_B1_12, label: SD_CD_SW, identifier: SD1_CD} -- {pin_num: D14, pin_signal: GPIO_B1_13, label: WDOG_B, identifier: WDOG_B} -- {pin_num: C14, pin_signal: GPIO_B1_14, label: SD0_VSELECT, identifier: SD0_VSELECT} -- {pin_num: B14, pin_signal: GPIO_B1_15, label: USB_HOST_PWR/BACKLIGHT_CTL, identifier: BACKLIGHT_CTL} -- {pin_num: E9, pin_signal: NVCC_GPIO0, label: DCDC_3V3/NVCC_GPIO_3V3} -- {pin_num: F10, pin_signal: NVCC_GPIO1, label: DCDC_3V3/NVCC_GPIO_3V3} -- {pin_num: J10, pin_signal: NVCC_GPIO2, label: DCDC_3V3/NVCC_GPIO_3V3} -- {pin_num: M14, pin_signal: GPIO_AD_B0_00, label: 'USB_HOST_OC/J24[10]'} -- {pin_num: H10, pin_signal: GPIO_AD_B0_01, label: 'USB_OTG1_ID/J24[9]'} -- {pin_num: M11, pin_signal: GPIO_AD_B0_02, label: 'USB_OTG1_PWR/J24[2]'} -- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: 'USB_OTG1_OC/J24[1]'} -- {pin_num: F11, pin_signal: GPIO_AD_B0_04, label: 'CSI_PWDN/J35[17]/BOOT_MODE[0]', identifier: CSI_PWDN} -- {pin_num: G14, pin_signal: GPIO_AD_B0_05, label: 'CAN_STBY/BOOT_MODE[1]/Flash_RST/U12[8]', identifier: CAN_STBY} -- {pin_num: E14, pin_signal: GPIO_AD_B0_06, label: 'JTAG_TMS/J21[7]/SWD_DIO'} -- {pin_num: F12, pin_signal: GPIO_AD_B0_07, label: 'JTAG_TCK/J21[9]/SWD_CLK'} -- {pin_num: F13, pin_signal: GPIO_AD_B0_08, label: JTAG_MOD} -- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} -- {pin_num: G13, pin_signal: GPIO_AD_B0_10, label: 'JTAG_TDO/J21[13]/INT1_COMBO/ENET_INT/J22[6]/U32[11]', identifier: INT1_COMBO} -- {pin_num: G10, pin_signal: GPIO_AD_B0_11, label: 'JTAG_nTRST/J21[3]/INT2_COMBO/LCD_TOUCH_INT/J22[3]/U32[9]', identifier: INT2_COMBO} -- {pin_num: K14, pin_signal: GPIO_AD_B0_12, label: UART1_TXD, identifier: UART1_TXD} -- {pin_num: L14, pin_signal: GPIO_AD_B0_13, label: UART1_RXD, identifier: UART1_RXD} -- {pin_num: H14, pin_signal: GPIO_AD_B0_14, label: 'CAN2_TX/U12[1]', identifier: CAN2_TX} -- {pin_num: L10, pin_signal: GPIO_AD_B0_15, label: 'CAN2_RX/U12[4]', identifier: CAN2_RX} -- {pin_num: J11, pin_signal: GPIO_AD_B1_00, label: 'I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4]', identifier: I2C_SCL_FXOS8700CQ;CSI_I2C_SCL;I2C_SCL;I2C1_SCL} -- {pin_num: K11, pin_signal: GPIO_AD_B1_01, label: 'I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6]', identifier: I2C_SDA_FXOS8700CQ;CSI_I2C_SDA;I2C1_SDA} -- {pin_num: L11, pin_signal: GPIO_AD_B1_02, label: 'SPDIF_OUT/J22[7]', identifier: SPDIF_OUT} -- {pin_num: M12, pin_signal: GPIO_AD_B1_03, label: 'SPDIF_IN/J22[8]', identifier: SPDIF_IN} -- {pin_num: H13, pin_signal: GPIO_AD_B1_08, label: 'AUD_INT/CSI_D9//J35[13]/J22[4]', identifier: CSI_D9} -- {pin_num: M13, pin_signal: GPIO_AD_B1_09, label: 'SAI1_MCLK/CSI_D8/J35[11]', identifier: CSI_D8} -- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: 'SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1]', identifier: CSI_D7} -- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: 'SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2]', identifier: CSI_D6} -- {pin_num: H12, pin_signal: GPIO_AD_B1_12, label: 'SAI1_RXD/CSI_D5/J35[5]/U13[16]', identifier: CSI_D5} -- {pin_num: H11, pin_signal: GPIO_AD_B1_13, label: 'SAI1_TXD/CSI_D4/J35[3]/U13[14]', identifier: CSI_D4} -- {pin_num: G12, pin_signal: GPIO_AD_B1_14, label: 'SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12]', identifier: CSI_D3} -- {pin_num: J14, pin_signal: GPIO_AD_B1_15, label: 'SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13]', identifier: CSI_D2} -- {pin_num: J4, pin_signal: GPIO_SD_B0_00, label: 'SD1_CMD/J24[6]', identifier: SD1_CMD} -- {pin_num: J3, pin_signal: GPIO_SD_B0_01, label: 'SD1_CLK/J24[3]', identifier: SD1_CLK} -- {pin_num: J1, pin_signal: GPIO_SD_B0_02, label: 'SD1_D0/J24[4]/SPI_MOSI/PWM', identifier: SD1_D0} -- {pin_num: K1, pin_signal: GPIO_SD_B0_03, label: 'SD1_D1/J24[5]/SPI_MISO', identifier: SD1_D1} -- {pin_num: H2, pin_signal: GPIO_SD_B0_04, label: SD1_D2, identifier: SD1_D2} -- {pin_num: J2, pin_signal: GPIO_SD_B0_05, label: SD1_D3, identifier: SD1_D3} -- {pin_num: L5, pin_signal: GPIO_SD_B1_00, label: FlexSPI_D3_B, identifier: FlexSPI_D3_B} -- {pin_num: M5, pin_signal: GPIO_SD_B1_01, label: FlexSPI_D2_B, identifier: FlexSPI_D2_B} -- {pin_num: M3, pin_signal: GPIO_SD_B1_02, label: FlexSPI_D1_B, identifier: FlexSPI_D1_B} -- {pin_num: M4, pin_signal: GPIO_SD_B1_03, label: FlexSPI_D0_B, identifier: FlexSPI_D0_B} -- {pin_num: P2, pin_signal: GPIO_SD_B1_04, label: FlexSPI_CLK_B, identifier: FlexSPI_CLK_B} -- {pin_num: N3, pin_signal: GPIO_SD_B1_05, label: FlexSPI_DQS, identifier: FlexSPI_DQS} -- {pin_num: L3, pin_signal: GPIO_SD_B1_06, label: FlexSPI_SS0, identifier: FlexSPI_SS0} -- {pin_num: L4, pin_signal: GPIO_SD_B1_07, label: FlexSPI_CLK, identifier: FlexSPI_CLK} -- {pin_num: P3, pin_signal: GPIO_SD_B1_08, label: FlexSPI_D0_A, identifier: FlexSPI_D0_A} -- {pin_num: N4, pin_signal: GPIO_SD_B1_09, label: FlexSPI_D1_A, identifier: FlexSPI_D1_A} -- {pin_num: P4, pin_signal: GPIO_SD_B1_10, label: FlexSPI_D2_A, identifier: FlexSPI_D2_A} -- {pin_num: P5, pin_signal: GPIO_SD_B1_11, label: FlexSPI_D3_A, identifier: FlexSPI_D3_A} -- {pin_num: M8, pin_signal: USB_OTG1_DN, label: OTG1_DN, identifier: OTG1_DN} -- {pin_num: L8, pin_signal: USB_OTG1_DP, label: OTG1_DP, identifier: OTG1_DP} -- {pin_num: N7, pin_signal: USB_OTG2_DN, label: OTG2_DN, identifier: OTG2_DN} -- {pin_num: P7, pin_signal: USB_OTG2_DP, label: OTG2_DP, identifier: OTG2_DP} -- {pin_num: K8, pin_signal: VDD_USB_CAP, label: VDD_USB_3V} -- {pin_num: N6, pin_signal: USB_OTG1_VBUS, label: 5V_USB_OTG} -- {pin_num: P6, pin_signal: USB_OTG2_VBUS, label: 5V_USB_HS} -- {pin_num: L12, pin_signal: GPIO_AD_B1_04, label: 'CSI_PIXCLK/J35[8]/J23[3]', identifier: CSI_PIXCLK} -- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: 'CSI_MCLK/J35[12]/J23[4]', identifier: CSI_MCLK} -- {pin_num: J12, pin_signal: GPIO_AD_B1_06, label: 'CSI_VSYNC/J35[18]/J22[2]/UART_TX', identifier: CSI_VSYNC} -- {pin_num: K10, pin_signal: GPIO_AD_B1_07, label: 'CSI_HSYNC/J35[16]/J22[1]/UART_RX', identifier: CSI_HSYNC} -- {pin_num: M7, pin_signal: POR_B, label: 'RST_TGTMCU_B/POR_B/J21[15]', identifier: RST_TGTMCU_B;POR_B} -- {pin_num: N14, pin_signal: VDDA_ADC_3P3, label: VDDA_ADC_3P3_MCU} -- {pin_num: P12, pin_signal: VDD_HIGH_IN, label: VDD_HIGH_IN_MCU} -- {pin_num: M9, pin_signal: VDD_SNVS_IN, label: VDD_SNVS_IN} -- {pin_num: F6, pin_signal: VDD_SOC_IN0, label: VDD_SOC_IN} -- {pin_num: H6, pin_signal: VDD_SOC_IN2, label: VDD_SOC_IN} -- {pin_num: G6, pin_signal: VDD_SOC_IN1, label: VDD_SOC_IN} -- {pin_num: F7, pin_signal: VDD_SOC_IN3, label: VDD_SOC_IN} -- {pin_num: F8, pin_signal: VDD_SOC_IN4, label: VDD_SOC_IN} -- {pin_num: F9, pin_signal: VDD_SOC_IN5, label: VDD_SOC_IN} -- {pin_num: G9, pin_signal: VDD_SOC_IN6, label: VDD_SOC_IN} -- {pin_num: H9, pin_signal: VDD_SOC_IN7, label: VDD_SOC_IN} -- {pin_num: J9, pin_signal: VDD_SOC_IN8, label: VDD_SOC_IN} -- {pin_num: P1, pin_signal: VSS1, label: GND} -- {pin_num: E2, pin_signal: VSS2, label: GND} -- {pin_num: K2, pin_signal: VSS3, label: GND} -- {pin_num: B5, pin_signal: VSS4, label: GND} -- {pin_num: N5, pin_signal: VSS5, label: GND} -- {pin_num: G7, pin_signal: VSS6, label: GND} -- {pin_num: H7, pin_signal: VSS7, label: GND} -- {pin_num: J7, pin_signal: VSS8, label: GND} -- {pin_num: G8, pin_signal: VSS9, label: GND} -- {pin_num: H8, pin_signal: VSS10, label: GND} -- {pin_num: J8, pin_signal: VSS11, label: GND} -- {pin_num: N8, pin_signal: VSS12, label: GND} -- {pin_num: L9, pin_signal: VSS13, label: GND} -- {pin_num: B10, pin_signal: VSS14, label: GND} -- {pin_num: E13, pin_signal: VSS15, label: GND} -- {pin_num: K13, pin_signal: VSS16, label: GND} -- {pin_num: A14, pin_signal: VSS17, label: GND} -- {pin_num: P14, pin_signal: VSS18, label: GND} -- {pin_num: A1, pin_signal: VSS0, label: GND} -- {pin_num: J6, pin_signal: NVCC_SD0, label: NVCC_SD, identifier: NVCC_SD} -- {pin_num: K5, pin_signal: NVCC_SD1, label: FLASH_VCC, identifier: FLASH_VCC} -- {pin_num: F5, pin_signal: NVCC_EMC0, label: DCDC_3V3} -- {pin_num: E6, pin_signal: NVCC_EMC1, label: DCDC_3V3} -- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON} -- {pin_num: L1, pin_signal: DCDC_IN0, label: MCU_DCDC_IN_3V3} -- {pin_num: L2, pin_signal: DCDC_IN1, label: MCU_DCDC_IN_3V3} -- {pin_num: K4, pin_signal: DCDC_IN_Q, label: MCU_DCDC_IN_3V3} -- {pin_num: M1, pin_signal: DCDC_LP0, label: VDD_SOC_IN} -- {pin_num: M2, pin_signal: DCDC_LP1, label: VDD_SOC_IN} -- {pin_num: P11, pin_signal: XTALI, label: XTALI, identifier: XTALI} -- {pin_num: N11, pin_signal: XTALO, label: XTALO, identifier: XTALO} -- {pin_num: N9, pin_signal: RTC_XTALI, label: RTC_XTALI, identifier: RTC_XTALI} -- {pin_num: P9, pin_signal: RTC_XTALO, label: RTC_XTALO, identifier: RTC_XTALO} -- {pin_num: N1, pin_signal: DCDC_GND0, label: GND} -- {pin_num: N2, pin_signal: DCDC_GND1, label: GND} -- {pin_num: J5, pin_signal: DCDC_SENSE, label: VDD_SOC_IN} -- {pin_num: K3, pin_signal: DCDC_PSWITCH, label: MCU_DCDC_IN_3V3} -- {pin_num: K7, pin_signal: PMIC_ON_REQ, label: PMIC_ON_REQ, identifier: PMIC_ON_REQ} -- {pin_num: L7, pin_signal: PMIC_STBY_REQ, label: PERI_PWREN, identifier: PERI_PWREN} -- {pin_num: M6, pin_signal: ONOFF, label: ONOFF, identifier: ONOFF} -- {pin_num: K6, pin_signal: TEST_MODE, label: GND} -- {pin_num: P10, pin_signal: NVCC_PLL, label: VDDA_1P1_CAP} -- {pin_num: P8, pin_signal: VDD_HIGH_CAP, label: VDDA_2P5_CAP} -- {pin_num: K9, pin_signal: NGND_KEL0, label: GND} -- {pin_num: M10, pin_signal: VDD_SNVS_CAP, label: GND} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -#include "fsl_common.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) { - BOARD_InitPins(); - BOARD_InitDEBUG_UART(); - BOARD_InitENET(); - BOARD_InitUSDHC(); - BOARD_InitARDUINO_UART(); - BOARD_InitUSER_LED(); - BOARD_InitUSER_BUTTON(); - BOARD_InitI2C(); - BOARD_InitAudio(); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: [] - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitPins(void) { -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitDEBUG_UART: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, - pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} - - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm, - pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitDEBUG_UART - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitDEBUG_UART(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U); -#else - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U); -#else - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); -#endif -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSDRAM: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09} - - {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10} - - {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11} - - {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12} - - {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13} - - {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14} - - {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15} - - {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16} - - {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17} - - {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18} - - {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23} - - {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19} - - {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20} - - {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21} - - {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22} - - {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24} - - {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27} - - {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26} - - {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00} - - {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01} - - {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02} - - {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03} - - {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04} - - {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05} - - {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06} - - {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07} - - {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30} - - {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31} - - {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32} - - {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33} - - {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34} - - {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35} - - {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36} - - {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37} - - {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08} - - {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38} - - {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25} - - {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28} - - {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitSDRAM - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitSDRAM(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U); -#endif - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U); -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U); -#endif - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U); -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U); -#endif -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitCSI: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08} - - {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09} - - {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10} - - {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11} - - {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12} - - {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13} - - {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15} - - {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14} - - {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04} - - {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05} - - {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06} - - {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07} - - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm, - pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} - - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm, - pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow} - - {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitCSI - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitCSI(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitLCD: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull} - - {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitLCD - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitLCD(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitCAN: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14, software_input_on: Enable, speed: MHZ_50} - - {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15, software_input_on: Enable, speed: MHZ_50} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitCAN - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitCAN(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0x1030U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0x1030U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitENET: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10, direction: OUTPUT, software_input_on: Enable, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08, pull_keeper_enable: Disable, slew_rate: Fast} - - {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09, pull_keeper_enable: Disable, slew_rate: Fast} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitENET - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitENET(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB1U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitUSDHC: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05, pull_up_down_config: Pull_Up_47K_Ohm, pull_keeper_select: Pull, pull_keeper_enable: Enable, - speed: MHZ_200, drive_strength: R0, slew_rate: Fast} - - {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04, pull_up_down_config: Pull_Up_47K_Ohm, pull_keeper_select: Pull, speed: MHZ_200, - drive_strength: R0, slew_rate: Fast} - - {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03, pull_up_down_config: Pull_Up_47K_Ohm, pull_keeper_select: Pull, speed: MHZ_200, - drive_strength: R0, slew_rate: Fast} - - {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02, pull_up_down_config: Pull_Up_47K_Ohm, pull_keeper_select: Pull, speed: MHZ_200, - drive_strength: R0, slew_rate: Fast} - - {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00, pull_up_down_config: Pull_Up_47K_Ohm, pull_keeper_select: Pull, speed: MHZ_200, - drive_strength: R0, slew_rate: Fast} - - {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01, pull_keeper_enable: Disable, speed: MHZ_200, drive_strength: R0, slew_rate: Fast} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitUSDHC - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitUSDHC(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0x70C9U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0xC9U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0x70C9U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0x70C9U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0x70C9U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0x70C9U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitHyperFlash: -- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07} - - {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10} - - {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08} - - {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09} - - {pin_num: L5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: GPIO_SD_B1_00} - - {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: GPIO_SD_B1_01} - - {pin_num: M3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: GPIO_SD_B1_02} - - {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: GPIO_SD_B1_03} - - {pin_num: P2, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: GPIO_SD_B1_04} - - {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06} - - {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11} - - {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitHyperFlash - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitHyperFlash(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); -#endif -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitARDUINO_UART: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: J12, peripheral: LPUART3, signal: TX, pin_signal: GPIO_AD_B1_06} - - {pin_num: K10, peripheral: LPUART3, signal: RX, pin_signal: GPIO_AD_B1_07} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitARDUINO_UART - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitARDUINO_UART(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TXD, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0U); -#endif -#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3) - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RXD, 0U); -#else - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0U); -#endif -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitUSER_LED: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, gpio_init_state: 'true', pull_keeper_enable: Disable, open_drain: Disable} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitUSER_LED - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitUSER_LED(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */ - gpio_pin_config_t USER_LED_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 1U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */ - GPIO_PinInit(GPIO1, 9U, &USER_LED_config); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x60A0U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitUSER_BUTTON: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitUSER_BUTTON - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitUSER_BUTTON(void) { - CLOCK_EnableClock(kCLOCK_IomuxcSnvs); - - /* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */ - gpio_pin_config_t USER_BUTTON_config = { - .direction = kGPIO_DigitalInput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on WAKEUP (pin L6) */ - GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config); - - IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitI2C: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: I2C1_SCL, software_input_on: Enable, pull_keeper_enable: Disable, open_drain: Enable} - - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: I2C1_SDA, software_input_on: Enable, pull_keeper_enable: Disable, open_drain: Enable} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitI2C - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitI2C(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0x08B0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0x08B0U); -} - - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitAudio: -- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: H13, peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: INPUT, gpio_interrupt: kGPIO_IntRisingEdge, pull_up_down_config: Pull_Up_47K_Ohm} - - {pin_num: M13, peripheral: SAI1, signal: sai_mclk, pin_signal: GPIO_AD_B1_09, direction: OUTPUT, software_input_on: Enable} - - {pin_num: H12, peripheral: SAI1, signal: sai_rx_data0, pin_signal: GPIO_AD_B1_12, software_input_on: Enable} - - {pin_num: H11, peripheral: SAI1, signal: sai_tx_data0, pin_signal: GPIO_AD_B1_13, software_input_on: Enable} - - {pin_num: G12, peripheral: SAI1, signal: sai_tx_bclk, pin_signal: GPIO_AD_B1_14, software_input_on: Enable} - - {pin_num: J14, peripheral: SAI1, signal: sai_tx_sync, pin_signal: GPIO_AD_B1_15, software_input_on: Enable} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitAudio - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitAudio(void) { - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* GPIO configuration of CSI_D9 on GPIO_AD_B1_08 (pin H13) */ - gpio_pin_config_t CSI_D9_config = { - .direction = kGPIO_DigitalInput, - .outputLogic = 0U, - .interruptMode = kGPIO_IntRisingEdge - }; - /* Initialize GPIO functionality on GPIO_AD_B1_08 (pin H13) */ - GPIO_PinInit(GPIO1, 24U, &CSI_D9_config); - /* Enable GPIO pin interrupt on GPIO_AD_B1_08 (pin H13) */ - GPIO_PortEnableInterrupts(GPIO1, 1U << 24U); - - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U); - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClkOutputDir, true); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, 0x50B0U); -} - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/pin_mux.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/pin_mux.h deleted file mode 100644 index b8d79dc..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Board_Support/MIMXRT1052DVL6B/pin_mux.h +++ /dev/null @@ -1,855 +0,0 @@ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/*! @brief Direction type */ -typedef enum _pin_mux_direction -{ - kPIN_MUX_DirectionInput = 0U, /* Input direction */ - kPIN_MUX_DirectionOutput = 1U, /* Output direction */ - kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ -} pin_mux_direction_t; - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); - -/* GPIO_AD_B0_12 (coord K14), UART1_TXD */ -/* Routed pin properties */ -#define BOARD_INITDEBUG_UART_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITDEBUG_UART_UART1_TXD_SIGNAL TX /*!< Signal name */ - -/* GPIO_AD_B0_13 (coord L14), UART1_RXD */ -/* Routed pin properties */ -#define BOARD_INITDEBUG_UART_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITDEBUG_UART_UART1_RXD_SIGNAL RX /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitDEBUG_UART(void); - -/* GPIO_EMC_09 (coord C2), SEMC_A0 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A0_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_EMC_10 (coord G1), SEMC_A1 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A1_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_EMC_11 (coord G3), SEMC_A2 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A2_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A2_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_EMC_12 (coord H1), SEMC_A3 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A3_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A3_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_EMC_13 (coord A6), SEMC_A4 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A4_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A4_CHANNEL 4U /*!< Signal channel */ - -/* GPIO_EMC_14 (coord B6), SEMC_A5 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A5_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A5_CHANNEL 5U /*!< Signal channel */ - -/* GPIO_EMC_15 (coord B1), SEMC_A6 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A6_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A6_CHANNEL 6U /*!< Signal channel */ - -/* GPIO_EMC_16 (coord A5), SEMC_A7 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A7_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A7_CHANNEL 7U /*!< Signal channel */ - -/* GPIO_EMC_17 (coord A4), SEMC_A8 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A8_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A8_CHANNEL 8U /*!< Signal channel */ - -/* GPIO_EMC_18 (coord B2), SEMC_A9 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A9_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A9_CHANNEL 9U /*!< Signal channel */ - -/* GPIO_EMC_23 (coord G2), SEMC_A10 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A10_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A10_CHANNEL 10U /*!< Signal channel */ - -/* GPIO_EMC_19 (coord B4), SEMC_A11 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A11_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A11_CHANNEL 11U /*!< Signal channel */ - -/* GPIO_EMC_20 (coord A3), SEMC_A12 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_A12_SIGNAL ADDR /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_A12_CHANNEL 12U /*!< Signal channel */ - -/* GPIO_EMC_21 (coord C1), SEMC_BA0 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_BA0_SIGNAL BA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_BA0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_EMC_22 (coord F1), SEMC_BA1 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_BA1_SIGNAL BA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_BA1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_EMC_24 (coord D3), SEMC_CAS */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */ - -/* GPIO_EMC_27 (coord A2), SEMC_CKE */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */ - -/* GPIO_EMC_26 (coord B3), SEMC_CLK */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */ - -/* GPIO_EMC_00 (coord E3), SEMC_D0 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D0_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_EMC_01 (coord F3), SEMC_D1 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D1_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_EMC_02 (coord F4), SEMC_D2 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D2_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D2_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_EMC_03 (coord G4), SEMC_D3 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D3_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D3_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_EMC_04 (coord F2), SEMC_D4 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D4_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D4_CHANNEL 4U /*!< Signal channel */ - -/* GPIO_EMC_05 (coord G5), SEMC_D5 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D5_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D5_CHANNEL 5U /*!< Signal channel */ - -/* GPIO_EMC_06 (coord H5), SEMC_D6 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D6_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D6_CHANNEL 6U /*!< Signal channel */ - -/* GPIO_EMC_07 (coord H4), SEMC_D7 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D7_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D7_CHANNEL 7U /*!< Signal channel */ - -/* GPIO_EMC_30 (coord C6), SEMC_D8 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D8_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D8_CHANNEL 8U /*!< Signal channel */ - -/* GPIO_EMC_31 (coord C5), SEMC_D9 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D9_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D9_CHANNEL 9U /*!< Signal channel */ - -/* GPIO_EMC_32 (coord D5), SEMC_D10 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D10_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D10_CHANNEL 10U /*!< Signal channel */ - -/* GPIO_EMC_33 (coord C4), SEMC_D11 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D11_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D11_CHANNEL 11U /*!< Signal channel */ - -/* GPIO_EMC_34 (coord D4), SEMC_D12 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D12_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D12_CHANNEL 12U /*!< Signal channel */ - -/* GPIO_EMC_35 (coord E5), SEMC_D13 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D13_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D13_CHANNEL 13U /*!< Signal channel */ - -/* GPIO_EMC_36 (coord C3), SEMC_D14 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D14_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D14_CHANNEL 14U /*!< Signal channel */ - -/* GPIO_EMC_37 (coord E4), SEMC_D15 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_D15_SIGNAL DATA /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_D15_CHANNEL 15U /*!< Signal channel */ - -/* GPIO_EMC_08 (coord H3), SEMC_DM0 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_DM0_SIGNAL DM /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_DM0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_EMC_38 (coord D6), SEMC_DM1 */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_DM1_SIGNAL DM /*!< Signal name */ -#define BOARD_INITSDRAM_SEMC_DM1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_EMC_25 (coord D2), SEMC_RAS */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */ - -/* GPIO_EMC_28 (coord D1), SEMC_WE */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_SEMC_WE_SIGNAL semc_we /*!< Signal name */ - -/* GPIO_EMC_41 (coord C7), ENET_MDIO */ -/* Routed pin properties */ -#define BOARD_INITSDRAM_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */ -#define BOARD_INITSDRAM_ENET_MDIO_SIGNAL CSX /*!< Signal name */ -#define BOARD_INITSDRAM_ENET_MDIO_CHANNEL 0U /*!< Signal channel */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSDRAM(void); - -/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D9_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D9_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D9_CHANNEL 9U /*!< Signal channel */ - -/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D8_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D8_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D8_CHANNEL 8U /*!< Signal channel */ - -/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D7_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D7_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D7_CHANNEL 7U /*!< Signal channel */ - -/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D6_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D6_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D6_CHANNEL 6U /*!< Signal channel */ - -/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D5_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D5_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D5_CHANNEL 5U /*!< Signal channel */ - -/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D4_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D4_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D4_CHANNEL 4U /*!< Signal channel */ - -/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D2_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D2_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D2_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_D3_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_D3_SIGNAL csi_data /*!< Signal name */ -#define BOARD_INITCSI_CSI_D3_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_PIXCLK_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_PIXCLK_SIGNAL csi_pixclk /*!< Signal name */ - -/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_MCLK_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_MCLK_SIGNAL csi_mclk /*!< Signal name */ - -/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_VSYNC_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_VSYNC_SIGNAL csi_vsync /*!< Signal name */ - -/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_HSYNC_PERIPHERAL CSI /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_HSYNC_SIGNAL csi_hsync /*!< Signal name */ - -/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_I2C_SCL_SIGNAL SCL /*!< Signal name */ - -/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_I2C_SDA_SIGNAL SDA /*!< Signal name */ - -/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */ -/* Routed pin properties */ -#define BOARD_INITCSI_CSI_PWDN_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITCSI_CSI_PWDN_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITCSI_CSI_PWDN_CHANNEL 4U /*!< Signal channel */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITCSI_CSI_PWDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITCSI_CSI_PWDN_GPIO_PIN 4U /*!< GPIO pin number */ -#define BOARD_INITCSI_CSI_PWDN_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */ -#define BOARD_INITCSI_CSI_PWDN_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITCSI_CSI_PWDN_PIN 4U /*!< PORT pin number */ -#define BOARD_INITCSI_CSI_PWDN_PIN_MASK (1U << 4U) /*!< PORT pin mask */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitCSI(void); - -/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D2_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_B0_00 (coord D7), LCDIF_CLK */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */ - -/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D3_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D4_CHANNEL 4U /*!< Signal channel */ - -/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D5_CHANNEL 5U /*!< Signal channel */ - -/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D6_CHANNEL 6U /*!< Signal channel */ - -/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D7_CHANNEL 7U /*!< Signal channel */ - -/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D8_CHANNEL 8U /*!< Signal channel */ - -/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D9_CHANNEL 9U /*!< Signal channel */ - -/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D10_CHANNEL 10U /*!< Signal channel */ - -/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D11_CHANNEL 11U /*!< Signal channel */ - -/* GPIO_B1_00 (coord A11), LCDIF_D12 */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D12_CHANNEL 12U /*!< Signal channel */ - -/* GPIO_B1_01 (coord B11), LCDIF_D13 */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D13_CHANNEL 13U /*!< Signal channel */ - -/* GPIO_B1_02 (coord C11), LCDIF_D14 */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D14_CHANNEL 14U /*!< Signal channel */ - -/* GPIO_B1_03 (coord D11), LCDIF_D15 */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */ -#define BOARD_INITLCD_LCDIF_D15_CHANNEL 15U /*!< Signal channel */ - -/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */ - -/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */ - -/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */ -/* Routed pin properties */ -#define BOARD_INITLCD_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */ -#define BOARD_INITLCD_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */ - -/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */ -/* Routed pin properties */ -#define BOARD_INITLCD_BACKLIGHT_CTL_PERIPHERAL GPIO2 /*!< Peripheral name */ -#define BOARD_INITLCD_BACKLIGHT_CTL_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITLCD_BACKLIGHT_CTL_CHANNEL 31U /*!< Signal channel */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO peripheral base pointer */ -#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO pin number */ -#define BOARD_INITLCD_BACKLIGHT_CTL_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */ -#define BOARD_INITLCD_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT peripheral base pointer */ -#define BOARD_INITLCD_BACKLIGHT_CTL_PIN 31U /*!< PORT pin number */ -#define BOARD_INITLCD_BACKLIGHT_CTL_PIN_MASK (1U << 31U) /*!< PORT pin mask */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitLCD(void); - -/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */ -/* Routed pin properties */ -#define BOARD_INITCAN_CAN2_TX_PERIPHERAL CAN2 /*!< Peripheral name */ -#define BOARD_INITCAN_CAN2_TX_SIGNAL TX /*!< Signal name */ - -/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */ -/* Routed pin properties */ -#define BOARD_INITCAN_CAN2_RX_PERIPHERAL CAN2 /*!< Peripheral name */ -#define BOARD_INITCAN_CAN2_RX_SIGNAL RX /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitCAN(void); - -/* GPIO_EMC_40 (coord A7), ENET_MDC */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_MDC_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_MDC_SIGNAL enet_mdc /*!< Signal name */ - -/* GPIO_EMC_41 (coord C7), ENET_MDIO */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_MDIO_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_MDIO_SIGNAL enet_mdio /*!< Signal name */ - -/* GPIO_B1_10 (coord B13), ENET_TX_CLK */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< Signal name */ - -/* GPIO_B1_04 (coord E12), ENET_RXD0 */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */ -#define BOARD_INITENET_ENET_RXD0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_B1_05 (coord D12), ENET_RXD1 */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */ -#define BOARD_INITENET_ENET_RXD1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_B1_06 (coord C12), ENET_CRS_DV */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */ - -/* GPIO_B1_11 (coord C13), ENET_RXER */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */ - -/* GPIO_B1_07 (coord B12), ENET_TXD0 */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */ -#define BOARD_INITENET_ENET_TXD0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_B1_08 (coord A12), ENET_TXD1 */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */ -#define BOARD_INITENET_ENET_TXD1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_B1_09 (coord A13), ENET_TXEN */ -/* Routed pin properties */ -#define BOARD_INITENET_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */ -#define BOARD_INITENET_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitENET(void); - -/* GPIO_SD_B0_05 (coord J2), SD1_D3 */ -/* Routed pin properties */ -#define BOARD_INITUSDHC_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */ -#define BOARD_INITUSDHC_SD1_D3_SIGNAL usdhc_data /*!< Signal name */ -#define BOARD_INITUSDHC_SD1_D3_CHANNEL 3U /*!< Signal channel */ - -/* GPIO_SD_B0_04 (coord H2), SD1_D2 */ -/* Routed pin properties */ -#define BOARD_INITUSDHC_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */ -#define BOARD_INITUSDHC_SD1_D2_SIGNAL usdhc_data /*!< Signal name */ -#define BOARD_INITUSDHC_SD1_D2_CHANNEL 2U /*!< Signal channel */ - -/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */ -/* Routed pin properties */ -#define BOARD_INITUSDHC_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */ -#define BOARD_INITUSDHC_SD1_D1_SIGNAL usdhc_data /*!< Signal name */ -#define BOARD_INITUSDHC_SD1_D1_CHANNEL 1U /*!< Signal channel */ - -/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */ -/* Routed pin properties */ -#define BOARD_INITUSDHC_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */ -#define BOARD_INITUSDHC_SD1_D0_SIGNAL usdhc_data /*!< Signal name */ -#define BOARD_INITUSDHC_SD1_D0_CHANNEL 0U /*!< Signal channel */ - -/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */ -/* Routed pin properties */ -#define BOARD_INITUSDHC_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */ -#define BOARD_INITUSDHC_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */ - -/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */ -/* Routed pin properties */ -#define BOARD_INITUSDHC_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */ -#define BOARD_INITUSDHC_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitUSDHC(void); - -/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */ - -/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */ - -/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */ - -/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */ - -/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D3_B_SIGNAL FLEXSPI_B_DATA3 /*!< Signal name */ - -/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D2_B_SIGNAL FLEXSPI_B_DATA2 /*!< Signal name */ - -/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D1_B_SIGNAL FLEXSPI_B_DATA1 /*!< Signal name */ - -/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D0_B_SIGNAL FLEXSPI_B_DATA0 /*!< Signal name */ - -/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_CLK_B_SIGNAL FLEXSPI_B_SCLK /*!< Signal name */ - -/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */ - -/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */ - -/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */ -/* Routed pin properties */ -#define BOARD_INITHYPERFLASH_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */ -#define BOARD_INITHYPERFLASH_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitHyperFlash(void); - -/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */ -/* Routed pin properties */ -#define BOARD_INITARDUINO_UART_CSI_VSYNC_PERIPHERAL LPUART3 /*!< Peripheral name */ -#define BOARD_INITARDUINO_UART_CSI_VSYNC_SIGNAL TX /*!< Signal name */ - -/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */ -/* Routed pin properties */ -#define BOARD_INITARDUINO_UART_CSI_HSYNC_PERIPHERAL LPUART3 /*!< Peripheral name */ -#define BOARD_INITARDUINO_UART_CSI_HSYNC_SIGNAL RX /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitARDUINO_UART(void); - -/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */ -/* Routed pin properties */ -#define BOARD_INITUSER_LED_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITUSER_LED_USER_LED_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITUSER_LED_USER_LED_CHANNEL 9U /*!< Signal channel */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITUSER_LED_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITUSER_LED_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ -#define BOARD_INITUSER_LED_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ -#define BOARD_INITUSER_LED_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITUSER_LED_USER_LED_PIN 9U /*!< PORT pin number */ -#define BOARD_INITUSER_LED_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitUSER_LED(void); - -/* WAKEUP (coord L6), SD_PWREN */ -/* Routed pin properties */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_CHANNEL 0U /*!< Signal channel */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_PIN 0U /*!< PORT pin number */ -#define BOARD_INITUSER_BUTTON_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitUSER_BUTTON(void); - -/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */ -/* Routed pin properties */ -#define BOARD_INITI2C_I2C1_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */ -#define BOARD_INITI2C_I2C1_SCL_SIGNAL SCL /*!< Signal name */ - -/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */ -/* Routed pin properties */ -#define BOARD_INITI2C_I2C1_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */ -#define BOARD_INITI2C_I2C1_SDA_SIGNAL SDA /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitI2C(void); - -/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */ -/* Routed pin properties */ -#define BOARD_INITAUDIO_CSI_D9_PERIPHERAL GPIO1 /*!< Peripheral name */ -#define BOARD_INITAUDIO_CSI_D9_SIGNAL gpio_io /*!< Signal name */ -#define BOARD_INITAUDIO_CSI_D9_CHANNEL 24U /*!< Signal channel */ - -/* Symbols to be used with GPIO driver */ -#define BOARD_INITAUDIO_CSI_D9_GPIO GPIO1 /*!< GPIO peripheral base pointer */ -#define BOARD_INITAUDIO_CSI_D9_GPIO_PIN 24U /*!< GPIO pin number */ -#define BOARD_INITAUDIO_CSI_D9_GPIO_PIN_MASK (1U << 24U) /*!< GPIO pin mask */ -#define BOARD_INITAUDIO_CSI_D9_PORT GPIO1 /*!< PORT peripheral base pointer */ -#define BOARD_INITAUDIO_CSI_D9_PIN 24U /*!< PORT pin number */ -#define BOARD_INITAUDIO_CSI_D9_PIN_MASK (1U << 24U) /*!< PORT pin mask */ - -/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */ -/* Routed pin properties */ -#define BOARD_INITAUDIO_CSI_D8_PERIPHERAL SAI1 /*!< Peripheral name */ -#define BOARD_INITAUDIO_CSI_D8_SIGNAL sai_mclk /*!< Signal name */ - -/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */ -/* Routed pin properties */ -#define BOARD_INITAUDIO_CSI_D5_PERIPHERAL SAI1 /*!< Peripheral name */ -#define BOARD_INITAUDIO_CSI_D5_SIGNAL sai_rx_data0 /*!< Signal name */ - -/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */ -/* Routed pin properties */ -#define BOARD_INITAUDIO_CSI_D4_PERIPHERAL SAI1 /*!< Peripheral name */ -#define BOARD_INITAUDIO_CSI_D4_SIGNAL sai_tx_data0 /*!< Signal name */ - -/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */ -/* Routed pin properties */ -#define BOARD_INITAUDIO_CSI_D3_PERIPHERAL SAI1 /*!< Peripheral name */ -#define BOARD_INITAUDIO_CSI_D3_SIGNAL sai_tx_bclk /*!< Signal name */ - -/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */ -/* Routed pin properties */ -#define BOARD_INITAUDIO_CSI_D2_PERIPHERAL SAI1 /*!< Peripheral name */ -#define BOARD_INITAUDIO_CSI_D2_SIGNAL sai_tx_sync /*!< Signal name */ - - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitAudio(void); - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/CMSIS/RTX_Config.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/CMSIS/RTX_Config.c deleted file mode 100644 index 737078a..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/CMSIS/RTX_Config.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.1.1 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration - * - * ----------------------------------------------------------------------------- - */ - -#include "cmsis_compiler.h" -#include "rtx_os.h" - -// OS Idle Thread -__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { - (void)argument; - - for (;;) {} -} - -// OS Error Callback function -__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { - (void)object_id; - - switch (code) { - case osRtxErrorStackOverflow: - // Stack overflow detected for thread (thread_id=object_id) - break; - case osRtxErrorISRQueueOverflow: - // ISR Queue overflow detected when inserting object (object_id) - break; - case osRtxErrorTimerQueueOverflow: - // User Timer Callback Queue overflow detected for timer (timer_id=object_id) - break; - case osRtxErrorClibSpace: - // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM - break; - case osRtxErrorClibMutex: - // Standard C/C++ library mutex initialization failed - break; - default: - // Reserved - break; - } - for (;;) {} -//return 0U; -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/CMSIS/RTX_Config.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/CMSIS/RTX_Config.h deleted file mode 100644 index 4ebcc71..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/CMSIS/RTX_Config.h +++ /dev/null @@ -1,580 +0,0 @@ -/* - * Copyright (c) 2013-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.5.2 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration definitions - * - * ----------------------------------------------------------------------------- - */ - -#ifndef RTX_CONFIG_H_ -#define RTX_CONFIG_H_ - -#ifdef _RTE_ -#include "RTE_Components.h" -#ifdef RTE_RTX_CONFIG_H -#include RTE_RTX_CONFIG_H -#endif -#endif - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Configuration -// ======================= - -// Global Dynamic Memory size [bytes] <0-1073741824:8> -// Defines the combined global dynamic memory size. -// Default: 32768 -#ifndef OS_DYNAMIC_MEM_SIZE -#define OS_DYNAMIC_MEM_SIZE 24000 -#endif - -// Kernel Tick Frequency [Hz] <1-1000000> -// Defines base time unit for delays and timeouts. -// Default: 1000 (1ms tick) -#ifndef OS_TICK_FREQ -#define OS_TICK_FREQ 1000 -#endif - -// Round-Robin Thread switching -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN_ENABLE -#define OS_ROBIN_ENABLE 1 -#endif - -// Round-Robin Timeout <1-1000> -// Defines how many ticks a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBIN_TIMEOUT -#define OS_ROBIN_TIMEOUT 5 -#endif - -// - -// ISR FIFO Queue -// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries -// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries -// RTOS Functions called from ISR store requests to this buffer. -// Default: 16 entries -#ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 16 -#endif - -// Object Memory usage counters -// Enables object memory usage counters (requires RTX source variant). -#ifndef OS_OBJ_MEM_USAGE -#define OS_OBJ_MEM_USAGE 0 -#endif - -// - -// Thread Configuration -// ======================= - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_THREAD_OBJ_MEM -#define OS_THREAD_OBJ_MEM 0 -#endif - -// Number of user Threads <1-1000> -// Defines maximum number of user threads that can be active at the same time. -// Applies to user threads with system provided memory for control blocks. -#ifndef OS_THREAD_NUM -#define OS_THREAD_NUM 1 -#endif - -// Number of user Threads with default Stack size <0-1000> -// Defines maximum number of user threads with default stack size. -// Applies to user threads with zero stack size specified. -#ifndef OS_THREAD_DEF_STACK_NUM -#define OS_THREAD_DEF_STACK_NUM 0 -#endif - -// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> -// Defines the combined stack size for user threads with user-provided stack size. -// Applies to user threads with user-provided stack size and system provided memory for stack. -// Default: 0 -#ifndef OS_THREAD_USER_STACK_SIZE -#define OS_THREAD_USER_STACK_SIZE 0 -#endif - -// - -// Default Thread Stack size [bytes] <96-1073741824:8> -// Defines stack size for threads with zero stack size specified. -// Default: 3072 -#ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 3072 -#endif - -// Idle Thread Stack size [bytes] <72-1073741824:8> -// Defines stack size for Idle thread. -// Default: 512 -#ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 256 -#endif - -// Idle Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_IDLE_THREAD_TZ_MOD_ID -#define OS_IDLE_THREAD_TZ_MOD_ID 0 -#endif - -// Stack overrun checking -// Enables stack overrun check at thread switch (requires RTX source variant). -// Enabling this option increases slightly the execution time of a thread switch. -#ifndef OS_STACK_CHECK -#define OS_STACK_CHECK 1 -#endif - -// Stack usage watermark -// Initializes thread stack with watermark pattern for analyzing stack usage. -// Enabling this option increases significantly the execution time of thread creation. -#ifndef OS_STACK_WATERMARK -#define OS_STACK_WATERMARK 0 -#endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_PRIVILEGE_MODE -#define OS_PRIVILEGE_MODE 1 -#endif - -// - -// Timer Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_TIMER_OBJ_MEM -#define OS_TIMER_OBJ_MEM 0 -#endif - -// Number of Timer objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_TIMER_NUM -#define OS_TIMER_NUM 1 -#endif - -// - -// Timer Thread Priority -// <8=> Low -// <16=> Below Normal <24=> Normal <32=> Above Normal -// <40=> High -// <48=> Realtime -// Defines priority for timer thread -// Default: High -#ifndef OS_TIMER_THREAD_PRIO -#define OS_TIMER_THREAD_PRIO 40 -#endif - -// Timer Thread Stack size [bytes] <0-1073741824:8> -// Defines stack size for Timer thread. -// May be set to 0 when timers are not used. -// Default: 512 -#ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 256 -#endif - -// Timer Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_TIMER_THREAD_TZ_MOD_ID -#define OS_TIMER_THREAD_TZ_MOD_ID 0 -#endif - -// Timer Callback Queue entries <0-256> -// Number of concurrent active timer callback functions. -// May be set to 0 when timers are not used. -// Default: 4 -#ifndef OS_TIMER_CB_QUEUE -#define OS_TIMER_CB_QUEUE 4 -#endif - -// - -// Event Flags Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_EVFLAGS_OBJ_MEM -#define OS_EVFLAGS_OBJ_MEM 0 -#endif - -// Number of Event Flags objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_EVFLAGS_NUM -#define OS_EVFLAGS_NUM 1 -#endif - -// - -// - -// Mutex Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MUTEX_OBJ_MEM -#define OS_MUTEX_OBJ_MEM 0 -#endif - -// Number of Mutex objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MUTEX_NUM -#define OS_MUTEX_NUM 1 -#endif - -// - -// - -// Semaphore Configuration -// ========================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_SEMAPHORE_OBJ_MEM -#define OS_SEMAPHORE_OBJ_MEM 0 -#endif - -// Number of Semaphore objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_SEMAPHORE_NUM -#define OS_SEMAPHORE_NUM 1 -#endif - -// - -// - -// Memory Pool Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MEMPOOL_OBJ_MEM -#define OS_MEMPOOL_OBJ_MEM 0 -#endif - -// Number of Memory Pool objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MEMPOOL_NUM -#define OS_MEMPOOL_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MEMPOOL_DATA_SIZE -#define OS_MEMPOOL_DATA_SIZE 0 -#endif - -// - -// - -// Message Queue Configuration -// ============================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MSGQUEUE_OBJ_MEM -#define OS_MSGQUEUE_OBJ_MEM 0 -#endif - -// Number of Message Queue objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MSGQUEUE_NUM -#define OS_MSGQUEUE_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MSGQUEUE_DATA_SIZE -#define OS_MSGQUEUE_DATA_SIZE 0 -#endif - -// - -// - -// Event Recorder Configuration -// =============================== - -// Global Initialization -// Initialize Event Recorder during 'osKernelInitialize'. -#ifndef OS_EVR_INIT -#define OS_EVR_INIT 1 -#endif - -// Start recording -// Start event recording after initialization. -#ifndef OS_EVR_START -#define OS_EVR_START 1 -#endif - -// Global Event Filter Setup -// Initial recording level applied to all components. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_LEVEL -#define OS_EVR_LEVEL 0x00U -#endif - -// RTOS Event Filter Setup -// Recording levels for RTX components. -// Only applicable if events for the respective component are generated. - -// Memory Management -// Recording level for Memory Management events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMORY_LEVEL -#define OS_EVR_MEMORY_LEVEL 0x81U -#endif - -// Kernel -// Recording level for Kernel events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_KERNEL_LEVEL -#define OS_EVR_KERNEL_LEVEL 0x81U -#endif - -// Thread -// Recording level for Thread events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THREAD_LEVEL -#define OS_EVR_THREAD_LEVEL 0x85U -#endif - -// Generic Wait -// Recording level for Generic Wait events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_WAIT_LEVEL -#define OS_EVR_WAIT_LEVEL 0x81U -#endif - -// Thread Flags -// Recording level for Thread Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THFLAGS_LEVEL -#define OS_EVR_THFLAGS_LEVEL 0x81U -#endif - -// Event Flags -// Recording level for Event Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_EVFLAGS_LEVEL -#define OS_EVR_EVFLAGS_LEVEL 0x81U -#endif - -// Timer -// Recording level for Timer events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_TIMER_LEVEL -#define OS_EVR_TIMER_LEVEL 0x81U -#endif - -// Mutex -// Recording level for Mutex events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MUTEX_LEVEL -#define OS_EVR_MUTEX_LEVEL 0x81U -#endif - -// Semaphore -// Recording level for Semaphore events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_SEMAPHORE_LEVEL -#define OS_EVR_SEMAPHORE_LEVEL 0x81U -#endif - -// Memory Pool -// Recording level for Memory Pool events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMPOOL_LEVEL -#define OS_EVR_MEMPOOL_LEVEL 0x81U -#endif - -// Message Queue -// Recording level for Message Queue events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MSGQUEUE_LEVEL -#define OS_EVR_MSGQUEUE_LEVEL 0x81U -#endif - -// - -// - -// RTOS Event Generation -// Enables event generation for RTX components (requires RTX source variant). - -// Memory Management -// Enables Memory Management event generation. -#ifndef OS_EVR_MEMORY -#define OS_EVR_MEMORY 1 -#endif - -// Kernel -// Enables Kernel event generation. -#ifndef OS_EVR_KERNEL -#define OS_EVR_KERNEL 1 -#endif - -// Thread -// Enables Thread event generation. -#ifndef OS_EVR_THREAD -#define OS_EVR_THREAD 1 -#endif - -// Generic Wait -// Enables Generic Wait event generation. -#ifndef OS_EVR_WAIT -#define OS_EVR_WAIT 1 -#endif - -// Thread Flags -// Enables Thread Flags event generation. -#ifndef OS_EVR_THFLAGS -#define OS_EVR_THFLAGS 1 -#endif - -// Event Flags -// Enables Event Flags event generation. -#ifndef OS_EVR_EVFLAGS -#define OS_EVR_EVFLAGS 1 -#endif - -// Timer -// Enables Timer event generation. -#ifndef OS_EVR_TIMER -#define OS_EVR_TIMER 1 -#endif - -// Mutex -// Enables Mutex event generation. -#ifndef OS_EVR_MUTEX -#define OS_EVR_MUTEX 1 -#endif - -// Semaphore -// Enables Semaphore event generation. -#ifndef OS_EVR_SEMAPHORE -#define OS_EVR_SEMAPHORE 1 -#endif - -// Memory Pool -// Enables Memory Pool event generation. -#ifndef OS_EVR_MEMPOOL -#define OS_EVR_MEMPOOL 1 -#endif - -// Message Queue -// Enables Message Queue event generation. -#ifndef OS_EVR_MSGQUEUE -#define OS_EVR_MSGQUEUE 1 -#endif - -// - -// - -// Number of Threads which use standard C/C++ library libspace -// (when thread specific memory allocation is not used). -#if (OS_THREAD_OBJ_MEM == 0) -#ifndef OS_THREAD_LIBSPACE_NUM -#define OS_THREAD_LIBSPACE_NUM 4 -#endif -#else -#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM -#endif - -//------------- <<< end of configuration section >>> --------------------------- - -#endif // RTX_CONFIG_H_ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Compiler/EventRecorderConf.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Compiler/EventRecorderConf.h deleted file mode 100644 index b3191d6..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Compiler/EventRecorderConf.h +++ /dev/null @@ -1,34 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK - Component ::Event Recorder - * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: EventRecorderConf.h - * Purpose: Event Recorder Configuration - * Rev.: V1.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Event Recorder - -// Number of Records -// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 -// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 -// <65536=>65536 -// Configures size of Event Record Buffer (each record is 16 bytes) -// Must be 2^n (min=8, max=65536) -#define EVENT_RECORD_COUNT 64U - -// Time Stamp Source -// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer -// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) -// Selects source for 32-bit time stamp -#define EVENT_TIMESTAMP_SOURCE 0 - -// Time Stamp Clock Frequency [Hz] <0-1000000000> -// Defines initial time stamp clock frequency (0 when not used) -#define EVENT_TIMESTAMP_FREQ 0U - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx.scf b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx.scf deleted file mode 100644 index 32691fc..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx.scf +++ /dev/null @@ -1,158 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 -** Version: rev. 1.0, 2018-09-21 -** Build: b210709 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Modified by Keil */ - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000400 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -#define m_flash_config_start 0x60000000 -#define m_flash_config_size 0x00001000 - -#define m_ivt_start 0x60001000 -#define m_ivt_size 0x00001000 - -#define m_interrupts_start 0x60002000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x60002400 -#define m_text_size 0x03FFDC00 - -#define m_qacode_start 0x00000000 -#define m_qacode_size 0x00020000 - -#define m_interrupts_ram_start 0x80000000 -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x01E00000 - m_interrupts_ram_size) - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -#define m_data_noinit_size 0x00000500 - -#define m_data2_start 0x20000000 -#define m_data2_size 0x00020000 - -#define m_data3_start 0x20200000 -#define m_data3_size 0x00040000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x10000 -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region - RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address - * (.boot_hdr.conf, +FIRST) - } - - RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -#else -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region -#endif - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - RW_m_data2 m_data2_start m_data2_size { - * (RamFunction) - * (DataQuickAccess) - * (dtcm) - emac_imxrt105x.o (+RW +ZI) - mci_imxrt105x.o (+RW +ZI) - } - RW_m_data3 m_data3_start m_data3_size { - .ANY (+RW +ZI) - } -#if (defined(__heap_noncacheable__)) - RW_m_data m_data_start m_data_size-Stack_Size { ; RW data -#else - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size-m_ncache_size-m_data_noinit_size { ; RW data -#endif - .ANY (+RW +ZI) - * (*m_usb_dma_init_data) - * (*m_usb_dma_noninit_data) - } - RW_NOINIT +0 UNINIT { ; RW uninitialized data - * (.bss.noinit) - } -#if (!defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } -#endif - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - RW_m_ram_text m_qacode_start m_qacode_size { ; - * (CodeQuickAccess) - * (itcm) - } -#if (defined(__heap_noncacheable__)) - RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data -#else - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data -#endif - * (NonCacheable.init) - * (*NonCacheable) - } -#if (defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration -#else - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration -#endif - } -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_flexspi_nor.scf b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_flexspi_nor.scf deleted file mode 100644 index 3534297..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_flexspi_nor.scf +++ /dev/null @@ -1,118 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 -** Version: rev. 1.0, 2018-09-21 -** Build: b210709 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000400 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -#define m_flash_config_start 0x60000000 -#define m_flash_config_size 0x00001000 - -#define m_ivt_start 0x60001000 -#define m_ivt_size 0x00001000 - -#define m_interrupts_start 0x60002000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x60002400 -#define m_text_size 0x03FFDC00 - -#define m_qacode_start 0x00000000 -#define m_qacode_size 0x00020000 - -#define m_interrupts_ram_start 0x20000000 -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x00020000 - m_interrupts_ram_size) - -#define m_data2_start 0x20200000 -#define m_data2_size 0x00040000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region - RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address - * (.boot_hdr.conf, +FIRST) - } - - RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -#else -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region -#endif - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - * (RamFunction) - * (NonCacheable.init) - * (*NonCacheable) - * (DataQuickAccess) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - RW_m_ram_text m_qacode_start m_qacode_size { ; - * (CodeQuickAccess) - } - RW_m_ncache m_data2_start EMPTY 0 { - } - RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration - } -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_flexspi_nor_sdram.scf b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_flexspi_nor_sdram.scf deleted file mode 100644 index a09fbf0..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_flexspi_nor_sdram.scf +++ /dev/null @@ -1,144 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 -** Version: rev. 1.0, 2018-09-21 -** Build: b210709 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#if (defined(__ram_vector_table__)) - #define __ram_vector_table_size__ 0x00000400 -#else - #define __ram_vector_table_size__ 0x00000000 -#endif - -#define m_flash_config_start 0x60000000 -#define m_flash_config_size 0x00001000 - -#define m_ivt_start 0x60001000 -#define m_ivt_size 0x00001000 - -#define m_interrupts_start 0x60002000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x60002400 -#define m_text_size 0x03FFDC00 - -#define m_qacode_start 0x00000000 -#define m_qacode_size 0x00020000 - -#define m_interrupts_ram_start 0x80000000 -#define m_interrupts_ram_size __ram_vector_table_size__ - -#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) -#define m_data_size (0x01E00000 - m_interrupts_ram_size) - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -#define m_data2_start 0x20000000 -#define m_data2_size 0x00020000 - -#define m_data3_start 0x20200000 -#define m_data3_size 0x00040000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region - RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address - * (.boot_hdr.conf, +FIRST) - } - - RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address - * (.boot_hdr.ivt, +FIRST) - * (.boot_hdr.boot_data) - * (.boot_hdr.dcd_data) - } -#else -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region -#endif - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } -#if (defined(__ram_vector_table__)) - VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { - } -#else - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#endif - RW_m_data2 m_data2_start m_data2_size { - * (RamFunction) - * (DataQuickAccess) - } -#if (defined(__heap_noncacheable__)) - RW_m_data m_data_start m_data_size-Stack_Size { ; RW data -#else - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data -#endif - .ANY (+RW +ZI) - * (*m_usb_dma_init_data) - * (*m_usb_dma_noninit_data) - } -#if (!defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } -#endif - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - RW_m_ram_text m_qacode_start m_qacode_size { ; - * (CodeQuickAccess) - } -#if (defined(__heap_noncacheable__)) - RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data -#else - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data -#endif - * (NonCacheable.init) - * (*NonCacheable) - } -#if (defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration -#else - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration -#endif - } -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_ram.scf b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_ram.scf deleted file mode 100644 index c81e5c2..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_ram.scf +++ /dev/null @@ -1,79 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 -** Version: rev. 1.0, 2018-09-21 -** Build: b210709 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x00000400 -#define m_text_size 0x0001FC00 - -#define m_data_start 0x20000000 -#define m_data_size 0x00020000 - -#define m_data2_start 0x20200000 -#define m_data2_size 0x00040000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - * (CodeQuickAccess) - .ANY (+RO) - } - VECTOR_RAM m_interrupts_start EMPTY 0 { - } - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - * (NonCacheable.init) - * (*NonCacheable) - * (DataQuickAccess) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - RW_m_ncache m_data2_start EMPTY 0 { - } - RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration - } -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_sdram.scf b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_sdram.scf deleted file mode 100644 index 350f016..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_sdram.scf +++ /dev/null @@ -1,105 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 -** Version: rev. 1.0, 2018-09-21 -** Build: b210709 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x00000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x00000400 -#define m_text_size 0x0001FC00 - -#define m_data_start 0x80000000 -#define m_data_size 0x01E00000 - -#define m_data2_start 0x20000000 -#define m_data2_size 0x00020000 - -#define m_data3_start 0x20200000 -#define m_data3_size 0x00040000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - * (CodeQuickAccess) - .ANY (+RO) - } - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#if (defined(__heap_noncacheable__)) - RW_m_data m_data_start m_data_size-Stack_Size { ; RW data -#else - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data -#endif - .ANY (+RW +ZI) - * (*m_usb_dma_init_data) - * (*m_usb_dma_noninit_data) - } -#if (!defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } -#endif - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - RW_m_data2 m_data2_start m_data2_size { ; - * (DataQuickAccess) - } -#if (defined(__heap_noncacheable__)) - RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data -#else - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data -#endif - * (NonCacheable.init) - * (*NonCacheable) - } -#if (defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration -#else - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration -#endif - } -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_sdram_txt.scf b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_sdram_txt.scf deleted file mode 100644 index 902c6d0..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/MIMXRT1052xxxxx_sdram_txt.scf +++ /dev/null @@ -1,110 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c -/* -** ################################################################### -** Processors: MIMXRT1052CVJ5B -** MIMXRT1052CVL5B -** MIMXRT1052DVJ6B -** MIMXRT1052DVL6B -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2 -** Version: rev. 1.0, 2018-09-21 -** Build: b210709 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2021 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -#define m_interrupts_start 0x80000000 -#define m_interrupts_size 0x00000400 - -#define m_text_start 0x80000400 -#define m_text_size 0x001FFC00 - -#define m_qacode_start 0x00000000 -#define m_qacode_size 0x00020000 - -#define m_data_start 0x20200000 -#define m_data_size 0x00040000 - -#define m_data2_start 0x20000000 -#define m_data2_size 0x00020000 - -#define m_data3_start 0x80200000 -#define m_data3_size 0x01C00000 - -#define m_ncache_start 0x81E00000 -#define m_ncache_size 0x00200000 - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region - VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address - * (.isr_vector,+FIRST) - } - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - .ANY (+RO) - } - VECTOR_RAM m_interrupts_start EMPTY 0 { - } -#if (defined(__heap_noncacheable__)) - RW_m_data m_data_start m_data_size-Stack_Size { ; RW data -#else - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data -#endif - .ANY (+RW +ZI) - * (*m_usb_dma_init_data) - * (*m_usb_dma_noninit_data) - } -#if (!defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } -#endif - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - RW_m_ram_text m_qacode_start m_qacode_size { ; - * (CodeQuickAccess) - } - RW_m_data2 m_data2_start m_data2_size { ; - * (DataQuickAccess) - } -#if (defined(__heap_noncacheable__)) - RW_m_ncache m_ncache_start m_ncache_size - Heap_Size { ; ncache RW data -#else - RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data -#endif - * (NonCacheable.init) - * (*NonCacheable) - } -#if (defined(__heap_noncacheable__)) - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache)-Heap_Size { ; Empty region added for MPU configuration -#else - RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration -#endif - } -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/RTE_Device.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/RTE_Device.h deleted file mode 100644 index 0fc4089..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/RTE_Device.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2020 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _RTE_DEVICE_H -#define _RTE_DEVICE_H - -#include "pin_mux.h" -#include "main.h" - -/* UART Select, UART0 - UART5. */ -/* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled - * LPUART instance. */ -#define RTE_USART1 1 -#define RTE_USART1_DMA_EN 1 -#define RTE_USART2 0 -#define RTE_USART2_DMA_EN 0 -#define RTE_USART3 1 -#define RTE_USART3_DMA_EN 0 -#define RTE_USART4 0 -#define RTE_USART4_DMA_EN 0 -#define RTE_USART5 0 -#define RTE_USART5_DMA_EN 0 -#define RTE_USART6 0 -#define RTE_USART6_DMA_EN 0 -#define RTE_USART7 0 -#define RTE_USART7_DMA_EN 0 -#define RTE_USART8 0 -#define RTE_USART8_DMA_EN 0 - -/* UART configuration. */ -#define RTE_USART1_PIN_INIT LPUART1_InitPins -#define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins -#define RTE_USART1_DMA_TX_CH 0 -#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Tx -#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART1_DMA_TX_DMA_BASE DMA0 -#define RTE_USART1_DMA_RX_CH 1 -#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Rx -#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART1_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART2_PIN_INIT LPUART2_InitPins -#define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins -#define RTE_USART2_DMA_TX_CH 2 -#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Tx -#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART2_DMA_TX_DMA_BASE DMA0 -#define RTE_USART2_DMA_RX_CH 3 -#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Rx -#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART2_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART3_PIN_INIT LPUART3_InitPins -#define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins -#define RTE_USART3_DMA_TX_CH 4 -#define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Tx -#define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART3_DMA_TX_DMA_BASE DMA0 -#define RTE_USART3_DMA_RX_CH 5 -#define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Rx -#define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART3_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART4_PIN_INIT LPUART4_InitPins -#define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins -#define RTE_USART4_DMA_TX_CH 6 -#define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Tx -#define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART4_DMA_TX_DMA_BASE DMA0 -#define RTE_USART4_DMA_RX_CH 7 -#define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Rx -#define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART4_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART5_PIN_INIT LPUART5_InitPins -#define RTE_USART5_PIN_DEINIT LPUART5_DeinitPins -#define RTE_USART5_DMA_TX_CH 8 -#define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Tx -#define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART5_DMA_TX_DMA_BASE DMA0 -#define RTE_USART5_DMA_RX_CH 9 -#define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Rx -#define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART5_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART6_PIN_INIT LPUART6_InitPins -#define RTE_USART6_PIN_DEINIT LPUART6_DeinitPins -#define RTE_USART6_DMA_TX_CH 10 -#define RTE_USART6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Tx -#define RTE_USART6_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART6_DMA_TX_DMA_BASE DMA0 -#define RTE_USART6_DMA_RX_CH 11 -#define RTE_USART6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Rx -#define RTE_USART6_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART6_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART7_PIN_INIT LPUART7_InitPins -#define RTE_USART7_PIN_DEINIT LPUART7_DeinitPins -#define RTE_USART7_DMA_TX_CH 12 -#define RTE_USART7_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Tx -#define RTE_USART7_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART7_DMA_TX_DMA_BASE DMA0 -#define RTE_USART7_DMA_RX_CH 13 -#define RTE_USART7_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Rx -#define RTE_USART7_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART7_DMA_RX_DMA_BASE DMA0 - -#define RTE_USART8_PIN_INIT LPUART8_InitPins -#define RTE_USART8_PIN_DEINIT LPUART8_DeinitPins -#define RTE_USART8_DMA_TX_CH 14 -#define RTE_USART8_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Tx -#define RTE_USART8_DMA_TX_DMAMUX_BASE DMAMUX -#define RTE_USART8_DMA_TX_DMA_BASE DMA0 -#define RTE_USART8_DMA_RX_CH 15 -#define RTE_USART8_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Rx -#define RTE_USART8_DMA_RX_DMAMUX_BASE DMAMUX -#define RTE_USART8_DMA_RX_DMA_BASE DMA0 - -/* ENET configuration. */ -#define RTE_ENET 1 -#define RTE_ENET_PHY_ADDRESS 2 -#define RTE_ENET_MII 0 -#define RTE_ENET_RMII 1 - -#endif /* _RTE_DEVICE_H */ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/startup_MIMXRT1052.S b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/startup_MIMXRT1052.S deleted file mode 100644 index de291c6..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Device/MIMXRT1052DVL6B/startup_MIMXRT1052.S +++ /dev/null @@ -1,956 +0,0 @@ -/* ------------------------------------------------------------------------- */ -/* @file: startup_MIMXRT1052.s */ -/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ -/* MIMXRT1052 */ -/* @version: 1.3 */ -/* @date: 2019-4-29 */ -/* @build: b210419 */ -/* ------------------------------------------------------------------------- */ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2021 NXP */ -/* All rights reserved. */ -/* */ -/* SPDX-License-Identifier: BSD-3-Clause */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/ - .long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/ - .long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/ - .long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/ - .long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/ - .long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/ - .long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/ - .long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/ - .long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/ - .long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/ - .long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/ - .long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/ - .long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/ - .long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/ - .long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/ - .long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/ - .long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/ - .long CTI0_ERROR_IRQHandler /* CTI0_Error*/ - .long CTI1_ERROR_IRQHandler /* CTI1_Error*/ - .long CORE_IRQHandler /* CorePlatform exception IRQ*/ - .long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/ - .long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/ - .long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/ - .long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/ - .long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/ - .long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/ - .long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/ - .long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/ - .long LPI2C1_IRQHandler /* LPI2C1 interrupt*/ - .long LPI2C2_IRQHandler /* LPI2C2 interrupt*/ - .long LPI2C3_IRQHandler /* LPI2C3 interrupt*/ - .long LPI2C4_IRQHandler /* LPI2C4 interrupt*/ - .long LPSPI1_IRQHandler /* LPSPI1 single interrupt vector for all sources*/ - .long LPSPI2_IRQHandler /* LPSPI2 single interrupt vector for all sources*/ - .long LPSPI3_IRQHandler /* LPSPI3 single interrupt vector for all sources*/ - .long LPSPI4_IRQHandler /* LPSPI4 single interrupt vector for all sources*/ - .long CAN1_IRQHandler /* CAN1 interrupt*/ - .long CAN2_IRQHandler /* CAN2 interrupt*/ - .long FLEXRAM_IRQHandler /* FlexRAM address out of range Or access hit IRQ*/ - .long KPP_IRQHandler /* Keypad nterrupt*/ - .long TSC_DIG_IRQHandler /* TSC interrupt*/ - .long GPR_IRQ_IRQHandler /* GPR interrupt*/ - .long LCDIF_IRQHandler /* LCDIF interrupt*/ - .long CSI_IRQHandler /* CSI interrupt*/ - .long PXP_IRQHandler /* PXP interrupt*/ - .long WDOG2_IRQHandler /* WDOG2 interrupt*/ - .long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/ - .long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/ - .long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/ - .long CSU_IRQHandler /* CSU interrupt*/ - .long DCP_IRQHandler /* DCP_IRQ interrupt*/ - .long DCP_VMI_IRQHandler /* DCP_VMI_IRQ interrupt*/ - .long Reserved68_IRQHandler /* Reserved interrupt*/ - .long TRNG_IRQHandler /* TRNG interrupt*/ - .long SJC_IRQHandler /* SJC interrupt*/ - .long BEE_IRQHandler /* BEE interrupt*/ - .long SAI1_IRQHandler /* SAI1 interrupt*/ - .long SAI2_IRQHandler /* SAI1 interrupt*/ - .long SAI3_RX_IRQHandler /* SAI3 interrupt*/ - .long SAI3_TX_IRQHandler /* SAI3 interrupt*/ - .long SPDIF_IRQHandler /* SPDIF interrupt*/ - .long PMU_EVENT_IRQHandler /* Brown-out event interrupt*/ - .long Reserved78_IRQHandler /* Reserved interrupt*/ - .long TEMP_LOW_HIGH_IRQHandler /* TempSensor low/high interrupt*/ - .long TEMP_PANIC_IRQHandler /* TempSensor panic interrupt*/ - .long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/ - .long USB_PHY2_IRQHandler /* USBPHY (UTMI0), Interrupt*/ - .long ADC1_IRQHandler /* ADC1 interrupt*/ - .long ADC2_IRQHandler /* ADC2 interrupt*/ - .long DCDC_IRQHandler /* DCDC interrupt*/ - .long Reserved86_IRQHandler /* Reserved interrupt*/ - .long Reserved87_IRQHandler /* Reserved interrupt*/ - .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ - .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ - .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ - .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ - .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ - .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ - .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ - .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ - .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ - .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ - .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ - .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ - .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ - .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ - .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ - .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ - .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ - .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ - .long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/ - .long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/ - .long WDOG1_IRQHandler /* WDOG1 interrupt*/ - .long RTWDOG_IRQHandler /* RTWDOG interrupt*/ - .long EWM_IRQHandler /* EWM interrupt*/ - .long CCM_1_IRQHandler /* CCM IRQ1 interrupt*/ - .long CCM_2_IRQHandler /* CCM IRQ2 interrupt*/ - .long GPC_IRQHandler /* GPC interrupt*/ - .long SRC_IRQHandler /* SRC interrupt*/ - .long Reserved115_IRQHandler /* Reserved interrupt*/ - .long GPT1_IRQHandler /* GPT1 interrupt*/ - .long GPT2_IRQHandler /* GPT2 interrupt*/ - .long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/ - .long Reserved123_IRQHandler /* Reserved interrupt*/ - .long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/ - .long SEMC_IRQHandler /* Reserved interrupt*/ - .long USDHC1_IRQHandler /* USDHC1 interrupt*/ - .long USDHC2_IRQHandler /* USDHC2 interrupt*/ - .long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/ - .long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/ - .long ENET_IRQHandler /* ENET interrupt*/ - .long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/ - .long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/ - .long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/ - .long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/ - .long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/ - .long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/ - .long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/ - .long PIT_IRQHandler /* PIT interrupt*/ - .long ACMP1_IRQHandler /* ACMP interrupt*/ - .long ACMP2_IRQHandler /* ACMP interrupt*/ - .long ACMP3_IRQHandler /* ACMP interrupt*/ - .long ACMP4_IRQHandler /* ACMP interrupt*/ - .long Reserved143_IRQHandler /* Reserved interrupt*/ - .long Reserved144_IRQHandler /* Reserved interrupt*/ - .long ENC1_IRQHandler /* ENC1 interrupt*/ - .long ENC2_IRQHandler /* ENC2 interrupt*/ - .long ENC3_IRQHandler /* ENC3 interrupt*/ - .long ENC4_IRQHandler /* ENC4 interrupt*/ - .long TMR1_IRQHandler /* TMR1 interrupt*/ - .long TMR2_IRQHandler /* TMR2 interrupt*/ - .long TMR3_IRQHandler /* TMR3 interrupt*/ - .long TMR4_IRQHandler /* TMR4 interrupt*/ - .long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/ - .long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/ - .long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/ - .long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/ - .long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/ - .long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/ - .long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/ - .long DefaultISR /* 168*/ - .long DefaultISR /* 169*/ - .long DefaultISR /* 170*/ - .long DefaultISR /* 171*/ - .long DefaultISR /* 172*/ - .long DefaultISR /* 173*/ - .long DefaultISR /* 174*/ - .long DefaultISR /* 175*/ - .long DefaultISR /* 176*/ - .long DefaultISR /* 177*/ - .long DefaultISR /* 178*/ - .long DefaultISR /* 179*/ - .long DefaultISR /* 180*/ - .long DefaultISR /* 181*/ - .long DefaultISR /* 182*/ - .long DefaultISR /* 183*/ - .long DefaultISR /* 184*/ - .long DefaultISR /* 185*/ - .long DefaultISR /* 186*/ - .long DefaultISR /* 187*/ - .long DefaultISR /* 188*/ - .long DefaultISR /* 189*/ - .long DefaultISR /* 190*/ - .long DefaultISR /* 191*/ - .long DefaultISR /* 192*/ - .long DefaultISR /* 193*/ - .long DefaultISR /* 194*/ - .long DefaultISR /* 195*/ - .long DefaultISR /* 196*/ - .long DefaultISR /* 197*/ - .long DefaultISR /* 198*/ - .long DefaultISR /* 199*/ - .long DefaultISR /* 200*/ - .long DefaultISR /* 201*/ - .long DefaultISR /* 202*/ - .long DefaultISR /* 203*/ - .long DefaultISR /* 204*/ - .long DefaultISR /* 205*/ - .long DefaultISR /* 206*/ - .long DefaultISR /* 207*/ - .long DefaultISR /* 208*/ - .long DefaultISR /* 209*/ - .long DefaultISR /* 210*/ - .long DefaultISR /* 211*/ - .long DefaultISR /* 212*/ - .long DefaultISR /* 213*/ - .long DefaultISR /* 214*/ - .long DefaultISR /* 215*/ - .long DefaultISR /* 216*/ - .long DefaultISR /* 217*/ - .long DefaultISR /* 218*/ - .long DefaultISR /* 219*/ - .long DefaultISR /* 220*/ - .long DefaultISR /* 221*/ - .long DefaultISR /* 222*/ - .long DefaultISR /* 223*/ - .long DefaultISR /* 224*/ - .long DefaultISR /* 225*/ - .long DefaultISR /* 226*/ - .long DefaultISR /* 227*/ - .long DefaultISR /* 228*/ - .long DefaultISR /* 229*/ - .long DefaultISR /* 230*/ - .long DefaultISR /* 231*/ - .long DefaultISR /* 232*/ - .long DefaultISR /* 233*/ - .long DefaultISR /* 234*/ - .long DefaultISR /* 235*/ - .long DefaultISR /* 236*/ - .long DefaultISR /* 237*/ - .long DefaultISR /* 238*/ - .long DefaultISR /* 239*/ - .long DefaultISR /* 240*/ - .long DefaultISR /* 241*/ - .long DefaultISR /* 242*/ - .long DefaultISR /* 243*/ - .long DefaultISR /* 244*/ - .long DefaultISR /* 245*/ - .long DefaultISR /* 246*/ - .long DefaultISR /* 247*/ - .long DefaultISR /* 248*/ - .long DefaultISR /* 249*/ - .long DefaultISR /* 250*/ - .long DefaultISR /* 251*/ - .long DefaultISR /* 252*/ - .long DefaultISR /* 253*/ - .long DefaultISR /* 254*/ - .long 0xFFFFFFFF /* Reserved for user TRIM value*/ - - .size __Vectors, . - __Vectors - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__Vectors - str r1, [r0] - ldr r2, [r1] - msr msp, r2 - ldr r0,=SystemInit - blx r0 - cpsie i /* Unmask interrupts */ - ldr r0,=__main - bx r0 - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak DMA0_DMA16_IRQHandler - .type DMA0_DMA16_IRQHandler, %function -DMA0_DMA16_IRQHandler: - ldr r0,=DMA0_DMA16_DriverIRQHandler - bx r0 - .size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler - - .align 1 - .thumb_func - .weak DMA1_DMA17_IRQHandler - .type DMA1_DMA17_IRQHandler, %function -DMA1_DMA17_IRQHandler: - ldr r0,=DMA1_DMA17_DriverIRQHandler - bx r0 - .size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler - - .align 1 - .thumb_func - .weak DMA2_DMA18_IRQHandler - .type DMA2_DMA18_IRQHandler, %function -DMA2_DMA18_IRQHandler: - ldr r0,=DMA2_DMA18_DriverIRQHandler - bx r0 - .size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler - - .align 1 - .thumb_func - .weak DMA3_DMA19_IRQHandler - .type DMA3_DMA19_IRQHandler, %function -DMA3_DMA19_IRQHandler: - ldr r0,=DMA3_DMA19_DriverIRQHandler - bx r0 - .size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler - - .align 1 - .thumb_func - .weak DMA4_DMA20_IRQHandler - .type DMA4_DMA20_IRQHandler, %function -DMA4_DMA20_IRQHandler: - ldr r0,=DMA4_DMA20_DriverIRQHandler - bx r0 - .size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler - - .align 1 - .thumb_func - .weak DMA5_DMA21_IRQHandler - .type DMA5_DMA21_IRQHandler, %function -DMA5_DMA21_IRQHandler: - ldr r0,=DMA5_DMA21_DriverIRQHandler - bx r0 - .size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler - - .align 1 - .thumb_func - .weak DMA6_DMA22_IRQHandler - .type DMA6_DMA22_IRQHandler, %function -DMA6_DMA22_IRQHandler: - ldr r0,=DMA6_DMA22_DriverIRQHandler - bx r0 - .size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler - - .align 1 - .thumb_func - .weak DMA7_DMA23_IRQHandler - .type DMA7_DMA23_IRQHandler, %function -DMA7_DMA23_IRQHandler: - ldr r0,=DMA7_DMA23_DriverIRQHandler - bx r0 - .size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler - - .align 1 - .thumb_func - .weak DMA8_DMA24_IRQHandler - .type DMA8_DMA24_IRQHandler, %function -DMA8_DMA24_IRQHandler: - ldr r0,=DMA8_DMA24_DriverIRQHandler - bx r0 - .size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler - - .align 1 - .thumb_func - .weak DMA9_DMA25_IRQHandler - .type DMA9_DMA25_IRQHandler, %function -DMA9_DMA25_IRQHandler: - ldr r0,=DMA9_DMA25_DriverIRQHandler - bx r0 - .size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler - - .align 1 - .thumb_func - .weak DMA10_DMA26_IRQHandler - .type DMA10_DMA26_IRQHandler, %function -DMA10_DMA26_IRQHandler: - ldr r0,=DMA10_DMA26_DriverIRQHandler - bx r0 - .size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler - - .align 1 - .thumb_func - .weak DMA11_DMA27_IRQHandler - .type DMA11_DMA27_IRQHandler, %function -DMA11_DMA27_IRQHandler: - ldr r0,=DMA11_DMA27_DriverIRQHandler - bx r0 - .size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler - - .align 1 - .thumb_func - .weak DMA12_DMA28_IRQHandler - .type DMA12_DMA28_IRQHandler, %function -DMA12_DMA28_IRQHandler: - ldr r0,=DMA12_DMA28_DriverIRQHandler - bx r0 - .size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler - - .align 1 - .thumb_func - .weak DMA13_DMA29_IRQHandler - .type DMA13_DMA29_IRQHandler, %function -DMA13_DMA29_IRQHandler: - ldr r0,=DMA13_DMA29_DriverIRQHandler - bx r0 - .size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler - - .align 1 - .thumb_func - .weak DMA14_DMA30_IRQHandler - .type DMA14_DMA30_IRQHandler, %function -DMA14_DMA30_IRQHandler: - ldr r0,=DMA14_DMA30_DriverIRQHandler - bx r0 - .size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler - - .align 1 - .thumb_func - .weak DMA15_DMA31_IRQHandler - .type DMA15_DMA31_IRQHandler, %function -DMA15_DMA31_IRQHandler: - ldr r0,=DMA15_DMA31_DriverIRQHandler - bx r0 - .size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler - - .align 1 - .thumb_func - .weak DMA_ERROR_IRQHandler - .type DMA_ERROR_IRQHandler, %function -DMA_ERROR_IRQHandler: - ldr r0,=DMA_ERROR_DriverIRQHandler - bx r0 - .size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler - - .align 1 - .thumb_func - .weak LPUART1_IRQHandler - .type LPUART1_IRQHandler, %function -LPUART1_IRQHandler: - ldr r0,=LPUART1_DriverIRQHandler - bx r0 - .size LPUART1_IRQHandler, . - LPUART1_IRQHandler - - .align 1 - .thumb_func - .weak LPUART2_IRQHandler - .type LPUART2_IRQHandler, %function -LPUART2_IRQHandler: - ldr r0,=LPUART2_DriverIRQHandler - bx r0 - .size LPUART2_IRQHandler, . - LPUART2_IRQHandler - - .align 1 - .thumb_func - .weak LPUART3_IRQHandler - .type LPUART3_IRQHandler, %function -LPUART3_IRQHandler: - ldr r0,=LPUART3_DriverIRQHandler - bx r0 - .size LPUART3_IRQHandler, . - LPUART3_IRQHandler - - .align 1 - .thumb_func - .weak LPUART4_IRQHandler - .type LPUART4_IRQHandler, %function -LPUART4_IRQHandler: - ldr r0,=LPUART4_DriverIRQHandler - bx r0 - .size LPUART4_IRQHandler, . - LPUART4_IRQHandler - - .align 1 - .thumb_func - .weak LPUART5_IRQHandler - .type LPUART5_IRQHandler, %function -LPUART5_IRQHandler: - ldr r0,=LPUART5_DriverIRQHandler - bx r0 - .size LPUART5_IRQHandler, . - LPUART5_IRQHandler - - .align 1 - .thumb_func - .weak LPUART6_IRQHandler - .type LPUART6_IRQHandler, %function -LPUART6_IRQHandler: - ldr r0,=LPUART6_DriverIRQHandler - bx r0 - .size LPUART6_IRQHandler, . - LPUART6_IRQHandler - - .align 1 - .thumb_func - .weak LPUART7_IRQHandler - .type LPUART7_IRQHandler, %function -LPUART7_IRQHandler: - ldr r0,=LPUART7_DriverIRQHandler - bx r0 - .size LPUART7_IRQHandler, . - LPUART7_IRQHandler - - .align 1 - .thumb_func - .weak LPUART8_IRQHandler - .type LPUART8_IRQHandler, %function -LPUART8_IRQHandler: - ldr r0,=LPUART8_DriverIRQHandler - bx r0 - .size LPUART8_IRQHandler, . - LPUART8_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C1_IRQHandler - .type LPI2C1_IRQHandler, %function -LPI2C1_IRQHandler: - ldr r0,=LPI2C1_DriverIRQHandler - bx r0 - .size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C2_IRQHandler - .type LPI2C2_IRQHandler, %function -LPI2C2_IRQHandler: - ldr r0,=LPI2C2_DriverIRQHandler - bx r0 - .size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C3_IRQHandler - .type LPI2C3_IRQHandler, %function -LPI2C3_IRQHandler: - ldr r0,=LPI2C3_DriverIRQHandler - bx r0 - .size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler - - .align 1 - .thumb_func - .weak LPI2C4_IRQHandler - .type LPI2C4_IRQHandler, %function -LPI2C4_IRQHandler: - ldr r0,=LPI2C4_DriverIRQHandler - bx r0 - .size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI1_IRQHandler - .type LPSPI1_IRQHandler, %function -LPSPI1_IRQHandler: - ldr r0,=LPSPI1_DriverIRQHandler - bx r0 - .size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI2_IRQHandler - .type LPSPI2_IRQHandler, %function -LPSPI2_IRQHandler: - ldr r0,=LPSPI2_DriverIRQHandler - bx r0 - .size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI3_IRQHandler - .type LPSPI3_IRQHandler, %function -LPSPI3_IRQHandler: - ldr r0,=LPSPI3_DriverIRQHandler - bx r0 - .size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler - - .align 1 - .thumb_func - .weak LPSPI4_IRQHandler - .type LPSPI4_IRQHandler, %function -LPSPI4_IRQHandler: - ldr r0,=LPSPI4_DriverIRQHandler - bx r0 - .size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler - - .align 1 - .thumb_func - .weak CAN1_IRQHandler - .type CAN1_IRQHandler, %function -CAN1_IRQHandler: - ldr r0,=CAN1_DriverIRQHandler - bx r0 - .size CAN1_IRQHandler, . - CAN1_IRQHandler - - .align 1 - .thumb_func - .weak CAN2_IRQHandler - .type CAN2_IRQHandler, %function -CAN2_IRQHandler: - ldr r0,=CAN2_DriverIRQHandler - bx r0 - .size CAN2_IRQHandler, . - CAN2_IRQHandler - - .align 1 - .thumb_func - .weak SAI1_IRQHandler - .type SAI1_IRQHandler, %function -SAI1_IRQHandler: - ldr r0,=SAI1_DriverIRQHandler - bx r0 - .size SAI1_IRQHandler, . - SAI1_IRQHandler - - .align 1 - .thumb_func - .weak SAI2_IRQHandler - .type SAI2_IRQHandler, %function -SAI2_IRQHandler: - ldr r0,=SAI2_DriverIRQHandler - bx r0 - .size SAI2_IRQHandler, . - SAI2_IRQHandler - - .align 1 - .thumb_func - .weak SAI3_RX_IRQHandler - .type SAI3_RX_IRQHandler, %function -SAI3_RX_IRQHandler: - ldr r0,=SAI3_RX_DriverIRQHandler - bx r0 - .size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler - - .align 1 - .thumb_func - .weak SAI3_TX_IRQHandler - .type SAI3_TX_IRQHandler, %function -SAI3_TX_IRQHandler: - ldr r0,=SAI3_TX_DriverIRQHandler - bx r0 - .size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler - - .align 1 - .thumb_func - .weak SPDIF_IRQHandler - .type SPDIF_IRQHandler, %function -SPDIF_IRQHandler: - ldr r0,=SPDIF_DriverIRQHandler - bx r0 - .size SPDIF_IRQHandler, . - SPDIF_IRQHandler - - .align 1 - .thumb_func - .weak FLEXIO1_IRQHandler - .type FLEXIO1_IRQHandler, %function -FLEXIO1_IRQHandler: - ldr r0,=FLEXIO1_DriverIRQHandler - bx r0 - .size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXIO2_IRQHandler - .type FLEXIO2_IRQHandler, %function -FLEXIO2_IRQHandler: - ldr r0,=FLEXIO2_DriverIRQHandler - bx r0 - .size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXSPI_IRQHandler - .type FLEXSPI_IRQHandler, %function -FLEXSPI_IRQHandler: - ldr r0,=FLEXSPI_DriverIRQHandler - bx r0 - .size FLEXSPI_IRQHandler, . - FLEXSPI_IRQHandler - - .align 1 - .thumb_func - .weak USDHC1_IRQHandler - .type USDHC1_IRQHandler, %function -USDHC1_IRQHandler: - ldr r0,=USDHC1_DriverIRQHandler - bx r0 - .size USDHC1_IRQHandler, . - USDHC1_IRQHandler - - .align 1 - .thumb_func - .weak USDHC2_IRQHandler - .type USDHC2_IRQHandler, %function -USDHC2_IRQHandler: - ldr r0,=USDHC2_DriverIRQHandler - bx r0 - .size USDHC2_IRQHandler, . - USDHC2_IRQHandler - - .align 1 - .thumb_func - .weak ENET_IRQHandler - .type ENET_IRQHandler, %function -ENET_IRQHandler: - ldr r0,=ENET_DriverIRQHandler - bx r0 - .size ENET_IRQHandler, . - ENET_IRQHandler - - .align 1 - .thumb_func - .weak ENET_1588_Timer_IRQHandler - .type ENET_1588_Timer_IRQHandler, %function -ENET_1588_Timer_IRQHandler: - ldr r0,=ENET_1588_Timer_DriverIRQHandler - bx r0 - .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler - def_irq_handler DebugMon_Handler - def_irq_handler DMA0_DMA16_DriverIRQHandler - def_irq_handler DMA1_DMA17_DriverIRQHandler - def_irq_handler DMA2_DMA18_DriverIRQHandler - def_irq_handler DMA3_DMA19_DriverIRQHandler - def_irq_handler DMA4_DMA20_DriverIRQHandler - def_irq_handler DMA5_DMA21_DriverIRQHandler - def_irq_handler DMA6_DMA22_DriverIRQHandler - def_irq_handler DMA7_DMA23_DriverIRQHandler - def_irq_handler DMA8_DMA24_DriverIRQHandler - def_irq_handler DMA9_DMA25_DriverIRQHandler - def_irq_handler DMA10_DMA26_DriverIRQHandler - def_irq_handler DMA11_DMA27_DriverIRQHandler - def_irq_handler DMA12_DMA28_DriverIRQHandler - def_irq_handler DMA13_DMA29_DriverIRQHandler - def_irq_handler DMA14_DMA30_DriverIRQHandler - def_irq_handler DMA15_DMA31_DriverIRQHandler - def_irq_handler DMA_ERROR_DriverIRQHandler - def_irq_handler CTI0_ERROR_IRQHandler - def_irq_handler CTI1_ERROR_IRQHandler - def_irq_handler CORE_IRQHandler - def_irq_handler LPUART1_DriverIRQHandler - def_irq_handler LPUART2_DriverIRQHandler - def_irq_handler LPUART3_DriverIRQHandler - def_irq_handler LPUART4_DriverIRQHandler - def_irq_handler LPUART5_DriverIRQHandler - def_irq_handler LPUART6_DriverIRQHandler - def_irq_handler LPUART7_DriverIRQHandler - def_irq_handler LPUART8_DriverIRQHandler - def_irq_handler LPI2C1_DriverIRQHandler - def_irq_handler LPI2C2_DriverIRQHandler - def_irq_handler LPI2C3_DriverIRQHandler - def_irq_handler LPI2C4_DriverIRQHandler - def_irq_handler LPSPI1_DriverIRQHandler - def_irq_handler LPSPI2_DriverIRQHandler - def_irq_handler LPSPI3_DriverIRQHandler - def_irq_handler LPSPI4_DriverIRQHandler - def_irq_handler CAN1_DriverIRQHandler - def_irq_handler CAN2_DriverIRQHandler - def_irq_handler FLEXRAM_IRQHandler - def_irq_handler KPP_IRQHandler - def_irq_handler TSC_DIG_IRQHandler - def_irq_handler GPR_IRQ_IRQHandler - def_irq_handler LCDIF_IRQHandler - def_irq_handler CSI_IRQHandler - def_irq_handler PXP_IRQHandler - def_irq_handler WDOG2_IRQHandler - def_irq_handler SNVS_HP_WRAPPER_IRQHandler - def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler - def_irq_handler SNVS_LP_WRAPPER_IRQHandler - def_irq_handler CSU_IRQHandler - def_irq_handler DCP_IRQHandler - def_irq_handler DCP_VMI_IRQHandler - def_irq_handler Reserved68_IRQHandler - def_irq_handler TRNG_IRQHandler - def_irq_handler SJC_IRQHandler - def_irq_handler BEE_IRQHandler - def_irq_handler SAI1_DriverIRQHandler - def_irq_handler SAI2_DriverIRQHandler - def_irq_handler SAI3_RX_DriverIRQHandler - def_irq_handler SAI3_TX_DriverIRQHandler - def_irq_handler SPDIF_DriverIRQHandler - def_irq_handler PMU_EVENT_IRQHandler - def_irq_handler Reserved78_IRQHandler - def_irq_handler TEMP_LOW_HIGH_IRQHandler - def_irq_handler TEMP_PANIC_IRQHandler - def_irq_handler USB_PHY1_IRQHandler - def_irq_handler USB_PHY2_IRQHandler - def_irq_handler ADC1_IRQHandler - def_irq_handler ADC2_IRQHandler - def_irq_handler DCDC_IRQHandler - def_irq_handler Reserved86_IRQHandler - def_irq_handler Reserved87_IRQHandler - def_irq_handler GPIO1_INT0_IRQHandler - def_irq_handler GPIO1_INT1_IRQHandler - def_irq_handler GPIO1_INT2_IRQHandler - def_irq_handler GPIO1_INT3_IRQHandler - def_irq_handler GPIO1_INT4_IRQHandler - def_irq_handler GPIO1_INT5_IRQHandler - def_irq_handler GPIO1_INT6_IRQHandler - def_irq_handler GPIO1_INT7_IRQHandler - def_irq_handler GPIO1_Combined_0_15_IRQHandler - def_irq_handler GPIO1_Combined_16_31_IRQHandler - def_irq_handler GPIO2_Combined_0_15_IRQHandler - def_irq_handler GPIO2_Combined_16_31_IRQHandler - def_irq_handler GPIO3_Combined_0_15_IRQHandler - def_irq_handler GPIO3_Combined_16_31_IRQHandler - def_irq_handler GPIO4_Combined_0_15_IRQHandler - def_irq_handler GPIO4_Combined_16_31_IRQHandler - def_irq_handler GPIO5_Combined_0_15_IRQHandler - def_irq_handler GPIO5_Combined_16_31_IRQHandler - def_irq_handler FLEXIO1_DriverIRQHandler - def_irq_handler FLEXIO2_DriverIRQHandler - def_irq_handler WDOG1_IRQHandler - def_irq_handler RTWDOG_IRQHandler - def_irq_handler EWM_IRQHandler - def_irq_handler CCM_1_IRQHandler - def_irq_handler CCM_2_IRQHandler - def_irq_handler GPC_IRQHandler - def_irq_handler SRC_IRQHandler - def_irq_handler Reserved115_IRQHandler - def_irq_handler GPT1_IRQHandler - def_irq_handler GPT2_IRQHandler - def_irq_handler PWM1_0_IRQHandler - def_irq_handler PWM1_1_IRQHandler - def_irq_handler PWM1_2_IRQHandler - def_irq_handler PWM1_3_IRQHandler - def_irq_handler PWM1_FAULT_IRQHandler - def_irq_handler Reserved123_IRQHandler - def_irq_handler FLEXSPI_DriverIRQHandler - def_irq_handler SEMC_IRQHandler - def_irq_handler USDHC1_DriverIRQHandler - def_irq_handler USDHC2_DriverIRQHandler - def_irq_handler USB_OTG2_IRQHandler - def_irq_handler USB_OTG1_IRQHandler - def_irq_handler ENET_DriverIRQHandler - def_irq_handler ENET_1588_Timer_DriverIRQHandler - def_irq_handler XBAR1_IRQ_0_1_IRQHandler - def_irq_handler XBAR1_IRQ_2_3_IRQHandler - def_irq_handler ADC_ETC_IRQ0_IRQHandler - def_irq_handler ADC_ETC_IRQ1_IRQHandler - def_irq_handler ADC_ETC_IRQ2_IRQHandler - def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler - def_irq_handler PIT_IRQHandler - def_irq_handler ACMP1_IRQHandler - def_irq_handler ACMP2_IRQHandler - def_irq_handler ACMP3_IRQHandler - def_irq_handler ACMP4_IRQHandler - def_irq_handler Reserved143_IRQHandler - def_irq_handler Reserved144_IRQHandler - def_irq_handler ENC1_IRQHandler - def_irq_handler ENC2_IRQHandler - def_irq_handler ENC3_IRQHandler - def_irq_handler ENC4_IRQHandler - def_irq_handler TMR1_IRQHandler - def_irq_handler TMR2_IRQHandler - def_irq_handler TMR3_IRQHandler - def_irq_handler TMR4_IRQHandler - def_irq_handler PWM2_0_IRQHandler - def_irq_handler PWM2_1_IRQHandler - def_irq_handler PWM2_2_IRQHandler - def_irq_handler PWM2_3_IRQHandler - def_irq_handler PWM2_FAULT_IRQHandler - def_irq_handler PWM3_0_IRQHandler - def_irq_handler PWM3_1_IRQHandler - def_irq_handler PWM3_2_IRQHandler - def_irq_handler PWM3_3_IRQHandler - def_irq_handler PWM3_FAULT_IRQHandler - def_irq_handler PWM4_0_IRQHandler - def_irq_handler PWM4_1_IRQHandler - def_irq_handler PWM4_2_IRQHandler - def_irq_handler PWM4_3_IRQHandler - def_irq_handler PWM4_FAULT_IRQHandler - - .end diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config.c deleted file mode 100644 index 6946e8f..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config.c +++ /dev/null @@ -1,173 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V7.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Network System Settings -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "SockServer" - -// Memory Pool Size <1536-262144:4> -// This is the size of a memory pool in bytes. Buffers for -// network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_POOL_SIZE 16384 - -// Start System Services -// If enabled, the system will automatically start server services -// (HTTP, FTP, TFTP server, ...) when initializing the network system. -// Default: Enabled -#define NET_START_SERVICE 1 - -// OS Resource Settings -// These settings are used to optimize usage of OS resources. -// Core Thread Stack Size <512-65535:4> -// Default: 1024 bytes -#define NET_THREAD_STACK_SIZE 1024 - -// Core Thread Priority -#define NET_THREAD_PRIORITY osPriorityNormal - -// -// - -//------------- <<< end of configuration section >>> --------------------------- - -#include "RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_WiFi_0 -#include "Net_Config_WiFi_0.h" -#endif - -#ifdef RTE_Network_Interface_WiFi_1 -#include "Net_Config_WiFi_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP -#include "Net_Config_PPP.h" -#endif - -#ifdef RTE_Network_Interface_SLIP -#include "Net_Config_SLIP.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (NET_ERROR error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (NET_ERROR error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case NET_ERROR_MEM_ALLOC: - /* Out of memory */ - break; - - case NET_ERROR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case NET_ERROR_MEM_CORRUPT: - /* Memory Link pointer corrupted */ - /* More data written than the size of allocated memory block */ - break; - - case NET_ERROR_CONFIG: - /* Network configuration error detected */ - break; - - case NET_ERROR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case NET_ERROR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case NET_ERROR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_BSD.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index 8b7ba1b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,38 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration for BSD Sockets - * Rev.: V5.0.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 9 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 5 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_ETH_0.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index 8f91e69..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,265 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration for ETH Interface - * Rev.: V7.4.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 0 - -// MAC Address -// Ethernet MAC Address in text representation -// Value FF-FF-FF-FF-FF-FF is not allowed, -// LSB of first byte must be 0 (an ethernet Multicast bit). -// Default: "1E-30-6C-A2-45-5E" -#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5A" - -// VLAN -// Enable or disable Virtual LAN -#define ETH0_VLAN_ENABLE 0 - -// VLAN Identifier <1-4093> -// A unique 12-bit numeric value -// Default: 1 -#define ETH0_VLAN_ID 1 -// - -// IPv4 -// Enable IPv4 Protocol for Network Interface -#define ETH0_IP4_ENABLE 1 - -// IP Address -// Static IPv4 Address in text representation -// Default: "192.168.0.100" -#define ETH0_IP4_ADDR "192.168.0.100" - -// Subnet mask -// Local Subnet mask in text representation -// Default: "255.255.255.0" -#define ETH0_IP4_MASK "255.255.255.0" - -// Default Gateway -// IP Address of Default Gateway in text representation -// Default: "192.168.0.254" -#define ETH0_IP4_GATEWAY "192.168.0.254" - -// Primary DNS Server -// IP Address of Primary DNS Server in text representation -// Default: "8.8.8.8" -#define ETH0_IP4_PRIMARY_DNS "8.8.8.8" - -// Secondary DNS Server -// IP Address of Secondary DNS Server in text representation -// Default: "8.8.4.4" -#define ETH0_IP4_SECONDARY_DNS "8.8.4.4" - -// IP Fragmentation -// This option enables fragmentation of outgoing IP datagrams, -// and reassembling the fragments of incoming IP datagrams. -// Default: enabled -#define ETH0_IP4_FRAG_ENABLE 1 - -// MTU size <576-1500> -// Maximum Transmission Unit in bytes -// Default: 1500 -#define ETH0_IP4_MTU 1500 -// - -// ARP Address Resolution -// ARP cache and node address resolver settings -// Cache Table size <5-100> -// Number of cached MAC/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by its name on local LAN using NBNS protocol. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -#define ETH0_DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// - -// Disable ICMP Echo response -#define ETH0_ICMP_NO_ECHO 0 -// - -// IPv6 -// Enable IPv6 Protocol for Network Interface -#define ETH0_IP6_ENABLE 1 - -// IPv6 Address -// Static IPv6 Address in text representation -// Use unspecified address "::" when static -// IPv6 address is not used. -// Default: "fec0::2" -#define ETH0_IP6_ADDR "fec0::2" - -// Subnet prefix-length <1-128> -// Number of bits that define network address -// Default: 64 -#define ETH0_IP6_PREFIX_LEN 64 - -// Default Gateway -// Default Gateway IPv6 Address in text representation -// Default: "fec0::1" -#define ETH0_IP6_GATEWAY "fec0::1" - -// Primary DNS Server -// Primary DNS Server IPv6 Address in text representation -// Default: "2001:4860:4860::8888" -#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888" - -// Secondary DNS Server -// Secondary DNS Server IPv6 Address in text representation -// Default: "2001:4860:4860::8844" -#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844" - -// IPv6 Fragmentation -// This option enables fragmentation of outgoing IPv6 datagrams, -// and reassembling the fragments of incoming IPv6 datagrams. -// Default: enabled -#define ETH0_IP6_FRAG_ENABLE 1 - -// MTU size <1280-1500> -// Maximum Transmission Unit in bytes -// Default: 1500 -#define ETH0_IP6_MTU 1500 -// - -// Neighbor Discovery -// Neighbor cache and node address resolver settings -// Cache Table size <5-100> -// Number of cached node addresses -// Default: 5 -#define ETH0_NDP_TAB_SIZE 5 - -// Cache Timeout in seconds <5-255> -// Timeout for cached node addresses -// Default: 150 -#define ETH0_NDP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of retries to resolve an IP address -// before NDP module gives up -// Default: 4 -#define ETH0_NDP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend Neighbor Solicitation -// Default: 2 -#define ETH0_NDP_RESEND_TOUT 2 -// - -// Dynamic Host Configuration -// When this option is enabled, local IPv6 address is -// automatically configured. -#define ETH0_DHCP6_ENABLE 1 - -// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode -// Stateless DHCPv6 Client uses router advertisements -// for IPv6 address autoconfiguration (SLAAC). -// Statefull DHCPv6 Client connects to DHCPv6 server for a -// leased IPv6 address and DNS server IPv6 addresses. -#define ETH0_DHCP6_MODE 1 - -// Vendor Class Option -// If enabled, Vendor Class option is added to DHCPv6 -// request message, identifying vendor type. -// Default: disabled -#define ETH0_DHCP6_VCLASS_ENABLE 0 - -// Enterprise ID -// Enterprise-number as registered with IANA. -// Default: 0 (Reserved) -#define ETH0_DHCP6_VCLASS_EID 0 - -// Vendor Class Data -// This string identifies vendor type. -// Default: "" -#define ETH0_DHCP6_VCLASS_DATA "" -// -// - -// Disable ICMP6 Echo response -#define ETH0_ICMP6_NO_ECHO 0 -// - -// OS Resource Settings -// These settings are used to optimize usage of OS resources. -// Interface Thread Stack Size <512-65535:4> -// Default: 512 bytes -#define ETH0_THREAD_STACK_SIZE 512 - -// Interface Thread Priority -#define ETH0_THREAD_PRIORITY osPriorityAboveNormal - -// -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_TCP.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index 5a5de02..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,69 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration for TCP Sockets - * Rev.: V7.1.1 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 6 -#define TCP_NUM_SOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-65535> -// If no TCP data frame has been exchanged during this time, -// the TCP connection is either closed or a keep-alive frame -// is sent to verify that the connection still exists. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1440> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1440 -#define TCP_MAX_SEG_SIZE 1440 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4320 -#define TCP_RECEIVE_WIN_SIZE 4320 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - -// Dynamic port start (default 49152) -#define TCP_DYN_PORT_START 49152 - -// Dynamic port end (default 65535) -#define TCP_DYN_PORT_END 65535 - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_Telnet_Server.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_Telnet_Server.h deleted file mode 100644 index f5cf924..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_Telnet_Server.h +++ /dev/null @@ -1,58 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_Telnet_Server.h - * Purpose: Network Configuration for Telnet Server - * Rev.: V7.0.1 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Telnet Server -#define TELNET_SERVER_ENABLE 1 - -// Number of Connections <1-10> -// Number of simultaneously active Telnet Connections. -// Default: 1 -#define TELNET_SERVER_NUM_SESSIONS 1 - -// Port Number <1-65535> -// Listening port number. -// Default: 23 -#define TELNET_SERVER_PORT_NUM 23 - -// Idle Connection Timeout in seconds <0-3600> -// When timeout expires, the connection is closed. -// A value of 0 disables disconnection on timeout. -// Default: 120 -#define TELNET_SERVER_TOUT 120 - -// Disable Echo -// When disabled, the server will not echo characters it receives. -// Default: Not disabled -#define TELNET_SERVER_NO_ECHO 0 - -// Enable User Authentication -// When enabled, requires authentication of the user through -// the credentials to access the server. -#define TELNET_SERVER_AUTH_ENABLE 0 - -// Built-in Administrator Account -// Enable the built-in Administrator account on the server -// Default: Enabled -#define TELNET_SERVER_AUTH_ADMIN 1 - -// Administrator Username -// Default: "admin" -#define TELNET_SERVER_AUTH_USER "admin" - -// Administrator Password -// Default: "" -#define TELNET_SERVER_AUTH_PASS "" -// -// - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_UDP.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index b6b2172..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,28 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration for UDP Sockets - * Rev.: V5.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 11 - -// - -// Dynamic port start (default 49152) -#define UDP_DYN_PORT_START 49152 - -// Dynamic port end (default 65535) -#define UDP_DYN_PORT_END 65535 - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/SockServer.uvguix b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/SockServer.uvguix deleted file mode 100644 index 73dc35f..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/SockServer.uvguix +++ /dev/null @@ -1,1878 +0,0 @@ - - - - -6.1 - -
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
- - - - IMXRT1050-EVKB - 0x4 - ARM-ADS - 6160000::V6.16::ARMCLANG - 1 - - - MIMXRT1052DVL6B - NXP - NXP.MIMXRT1052_DFP.14.0.0 - https://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) XRAM(0x20200000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - - - - 0 - $$Device:MIMXRT1052DVL6B$fsl_device_registers.h - - - - - - - - - - $$Device:MIMXRT1052DVL6B$MIMXRT1052.xml - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - image - 1 - 0 - 0 - 1 - 0 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 1 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM7 - SARMCM3.DLL - - TCM.DLL - -pCM7 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - -1 - - 1 - - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M7" - - 1 - 0 - 0 - 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- - --predefine="-DXIP_BOOT_HEADER_ENABLE=1" - - 6314,6329 - - - - - - App - - - app_main.c - 1 - .\app_main.c - - - - - Board - - - main.c - 1 - .\main.c - - - main.h - 5 - .\main.h - - - - - Board IO - - - retarget_stdio.c - 1 - .\Board_IO\retarget_stdio.c - - - - - MCUXpresso - - - IMXRT1050-EVKB.mex - 5 - .\IMXRT1050-EVKB.mex - - - - - Documentation - - - Abstract.txt - 5 - .\Abstract.txt - - - - - SockServer - - - SockServer.c - 1 - ..\..\Source\SockServer.c - - - Telnet_Server_UIF.c - 1 - ..\..\Source\Telnet_Server_UIF.c - - - - - ::Board Support - - - ::CMSIS - - - ::CMSIS Driver - - - ::Compiler - - - ::Device - - - ::Network - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ETH_PHY_REF_CLK_50M=1 - - - - - - - - - - - - - - - - - - - - - - VIO_SENSOR_DISABLE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - RTE\Board_Support\MIMXRT1052DVL6B\peripherals.h - - - - - - - - RTE\Board_Support\MIMXRT1052DVL6B\pin_mux.c - - - - - - - - RTE\Board_Support\MIMXRT1052DVL6B\pin_mux.h - - - - - - - - RTE\CMSIS\RTX_Config.c - - - - - - - - RTE\CMSIS\RTX_Config.h - - - - - - - - RTE\Compiler\EventRecorderConf.h - - - - - - - - RTE\Device\MIMXRT1052DVL6B\MIMXRT1052xxxxx_flexspi_nor.scf - - - - - - - - RTE\Device\MIMXRT1052DVL6B\MIMXRT1052xxxxx_flexspi_nor_sdram.scf - - - - - - - - RTE\Device\MIMXRT1052DVL6B\MIMXRT1052xxxxx_ram.scf - - - - - - - - RTE\Device\MIMXRT1052DVL6B\MIMXRT1052xxxxx_sdram.scf - - - - - - - - RTE\Device\MIMXRT1052DVL6B\MIMXRT1052xxxxx_sdram_txt.scf - - - - - - - - RTE\Device\MIMXRT1052DVL6B\RTE_Device.h - - - - - - - - RTE\Device\MIMXRT1052DVL6B\startup_MIMXRT1052.S - - - - - - - - RTE\Network\Net_Config.c - - - - - - - - RTE\Network\Net_Config_BSD.h - - - - - - - - RTE\Network\Net_Config_ETH_0.h - - - - - - - - RTE\Network\Net_Config_TCP.h - - - - - - - - RTE\Network\Net_Config_Telnet_Server.h - - - - - - - - RTE\Network\Net_Config_UDP.h - - - - - - - - - - - - - Platform - 1 - - - App - Platform - Platform is a simple CMSIS RTOS2 example skeleton - Platform - Apache 2.0 - - - - - - Board - IMXRT1050-EVKB - Board setup with interfaces - Board - BSD 3-Clause, Apache 2.0 - - - - - - - - - - - - 1 - - - RTOS - RTX - Keil RTX5 open-source real-time operating system with CMSIS-RTOS v2 API - https://www2.keil.com/mdk5/cmsis/rtx - RTOS - Apache 2.0 - - - - - - - - 2 - .\main.c - Board - - - 2 - .\main.h - Board - - - 2 - .\Board_IO\retarget_stdio.c - Board - - - 1 - NXP::Board Support:SDK Project Template:project_template - Board - - - 1 - ARM::CMSIS:RTOS2:Keil RTX5 - RTOS - - - 1 - ARM::CMSIS:CORE - Board - - - 1 - Keil::CMSIS Driver:Ethernet PHY:KSZ8081RNA - Board - - - 1 - Keil::CMSIS Driver:Ethernet MAC - Board - - - 1 - Keil::CMSIS Driver:MCI - Board - - - 1 - NXP::CMSIS Driver:USART:lpuart_cmsis - Board - - - 1 - Keil::CMSIS Driver:VIO:Board - Board - - - 1 - Keil.ARM Compiler::Compiler:Event Recorder - Board - - - 1 - Keil.ARM Compiler::Compiler:I/O:STDERR - Board - - - 1 - Keil.ARM Compiler::Compiler:I/O:STDIN - Board - - - 1 - Keil.ARM Compiler::Compiler:I/O:STDOUT - Board - - - 1 - NXP::Device:CMSIS:MIMXRT1052_header - Board - - - 1 - NXP::Device:CMSIS:MIMXRT1052_system - Board - - - 1 - NXP::Device:SDK Drivers:clock - Board - - - 1 - NXP::Device:SDK Drivers:common - Board - - - 1 - NXP::Device:SDK Drivers:dmamux - Board - - - 1 - NXP::Device:SDK Drivers:edma - Board - - - 1 - NXP::Device:SDK Drivers:enet - Board - - - 1 - NXP::Device:SDK Drivers:fxos8700cq - Board - - - 1 - NXP::Device:SDK Drivers:gpio - Board - - - 1 - NXP::Device:SDK Drivers:i2c - Board - - - 1 - NXP::Device:SDK Drivers:iomuxc - Board - - - 1 - NXP::Device:SDK Drivers:lists - Board - - - 1 - NXP::Device:SDK Drivers:lpuart - Board - - - 1 - NXP::Device:SDK Drivers:lpuart_adapter - Board - - - 1 - NXP::Device:SDK Drivers:lpuart_edma - Board - - - 1 - NXP::Device:SDK Drivers:sdhc - Board - - - 1 - NXP::Device:SDK Drivers:xip_device - Board - - - 1 - NXP::Device:SDK Project Template:RTE_Device - Board - - - 1 - NXP::Device:SDK Utilities:debug_console - Board - - - 1 - NXP::Device:SDK Utilities:serial_manager - Board - - - 1 - NXP::Device:SDK Utilities:serial_manager_uart - Board - - - 2 - .\IMXRT1050-EVKB.mex - Board - - - 1 - NXP::Device:Startup - Board - - - 1 - NXP::Device:SDK Drivers:nic301 - Board - - - 1 - NXP::Board Support:SDK Drivers:evkbimxrt1050 - Board - - - 1 - ARM::CMSIS Driver:USART:Custom - Board - - - 1 - NXP::Device:SDK Drivers:codec - Board - - - 1 - NXP::Device:SDK Drivers:codec_i2c - Board - - - 1 - NXP::Device:SDK Drivers:lpi2c_adapter - Board - - - 1 - NXP::Device:SDK Drivers:sai - Board - - - 1 - NXP::Device:SDK Drivers:sai_edma - Board - - - 1 - NXP::Device:SDK Drivers:wm8960 - Board - - - 1 - NXP::Device:SDK Drivers:wm8960_adapter - Board - - - 1 - NXP::Device:SDK Drivers:cache - Board - - - - - diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/app_main.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/app_main.c deleted file mode 100644 index 7bc3913..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/app_main.c +++ /dev/null @@ -1,95 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: app_main.c - * Purpose: Application main template - * - *---------------------------------------------------------------------------*/ - -#include -#include "main.h" - -#include "cmsis_os2.h" - -#include "rl_net.h" -#include "SockServer.h" - -static const osThreadAttr_t app_main_attr = { - .stack_size = 4096U -}; - -static osThreadId_t NetStatus_id; - -// IP address change notification -void netDHCP_Notify (uint32_t if_num, uint8_t opt, const uint8_t *val, uint32_t len) { - if (opt == NET_DHCP_OPTION_IP_ADDRESS) { - osThreadFlagsSet (NetStatus_id, 0x01); - } -} - -// Network status output thread -static void NetStatus (void *argument) { - uint8_t ip_addr[NET_ADDR_IP4_LEN]; - static char ip_ascii[16]; - static char buf[32]; - - printf ("Socket test server is UP!\r\n\r\n"); - printf ("Services\r\n"); - printf (" ECHO: port 7\r\n"); - printf (" CHARGEN: port 19\r\n"); - printf (" DISCARD: port 9\r\n\r\n"); - - osDelay (100); - - while(1) { - osThreadFlagsWait (0x01, osFlagsWaitAll, osWaitForever); - - netIF_GetOption (NET_IF_CLASS_ETH | 0, netIF_OptionIP4_Address, ip_addr, sizeof(ip_addr)); - netIP_ntoa (NET_ADDR_IP4, ip_addr, ip_ascii, sizeof(ip_ascii)); - - /* Printf out server listen IP */ - sprintf (buf, "Server IP=%-15s",ip_ascii); - printf ("%s\r\n", buf); - } -} - -/*--------------------------------------------------------------------------- - * Application main thread - *---------------------------------------------------------------------------*/ -static void app_main (void *argument) { - (void)argument; - - netInitialize(); - osDelay(500U); - - osThreadNew(DgramServer, NULL, NULL); - osThreadNew(StreamServer, NULL, NULL); - osThreadNew(TestAssistant, NULL, NULL); - - NetStatus_id = osThreadNew (NetStatus, NULL, NULL); - osThreadFlagsSet (NetStatus_id, 0x01); - - // Add user code here: - for (;;) {} -} - -/*--------------------------------------------------------------------------- - * Application initialization - *---------------------------------------------------------------------------*/ -void app_initialize (void) { - osThreadNew(app_main, NULL, &app_main_attr); -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/main.c b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/main.c deleted file mode 100644 index c1e6ea5..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/main.c +++ /dev/null @@ -1,82 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *---------------------------------------------------------------------------*/ - -#include "RTE_Components.h" -#include CMSIS_device_header -#include "cmsis_os2.h" -#ifdef RTE_VIO_BOARD -#include "cmsis_vio.h" -#endif -#ifdef RTE_Compiler_EventRecorder -#include "EventRecorder.h" -#endif - -#include "clock_config.h" -#include "board.h" -#include "pin_mux.h" -#include "fsl_iomuxc.h" -#include "fsl_dmamux.h" -#include "fsl_sai_edma.h" -#include "main.h" - -// Callbacks for LPUART1 Driver -uint32_t LPUART1_GetFreq (void) { return BOARD_BOOTCLOCKRUN_UART_CLK_ROOT; } -void LPUART1_InitPins (void) { /* Done in BOARD_InitDEBUG_UART function */ } -void LPUART1_DeinitPins(void) { /* Not implemented */ } - -// Callbacks for LPUART3 Driver -uint32_t LPUART3_GetFreq (void) { return BOARD_BOOTCLOCKRUN_UART_CLK_ROOT; } -void LPUART3_InitPins (void) { /* Done in BOARD_InitARDUINO_UART function */ } -void LPUART3_DeinitPins(void) { /* Not implemented */ } - -int main (void) { - edma_config_t DmaConfig; - - BOARD_InitBootPins(); - BOARD_InitBootClocks(); - BOARD_InitDebugConsole(); - - NVIC_SetPriority(ENET_IRQn, 8U); - NVIC_SetPriority(USDHC1_IRQn, 8U); - NVIC_SetPriority(LPUART3_IRQn, 8U); - - /* Initialize DMAMUX */ - DMAMUX_Init (DMAMUX); - - /* Initialize EDMA */ - EDMA_GetDefaultConfig (&DmaConfig); - EDMA_Init (DMA0, &DmaConfig); - - SystemCoreClockUpdate(); - -#ifdef RTE_VIO_BOARD - vioInit(); // Initialize Virtual I/O -#endif - -#if defined(RTE_Compiler_EventRecorder) && \ - (defined(__MICROLIB) || \ - !(defined(RTE_CMSIS_RTOS2_RTX5) || defined(RTE_CMSIS_RTOS2_FreeRTOS))) - EventRecorderInitialize(EventRecordAll, 1U); -#endif - - osKernelInitialize(); // Initialize CMSIS-RTOS2 - app_initialize(); // Initialize application - osKernelStart(); // Start thread execution - - for (;;) {} -} diff --git a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/main.h b/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/main.h deleted file mode 100644 index ab7c71d..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/IMXRT1050-EVKB/main.h +++ /dev/null @@ -1,34 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2020-2021 Arm Limited (or its affiliates). - * All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - *---------------------------------------------------------------------------*/ - -#ifndef MAIN_H__ -#define MAIN_H__ - -#include - -/* Prototypes */ -extern uint32_t LPUART1_GetFreq (void); -extern void LPUART1_InitPins (void); -extern void LPUART1_DeinitPins (void); -extern uint32_t LPUART3_GetFreq (void); -extern void LPUART3_InitPins (void); -extern void LPUART3_DeinitPins (void); - -extern void app_initialize (void); - -#endif diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/Abstract.txt b/Tools/SockServer/Embedded/MDK/Board/MCB4300/Abstract.txt deleted file mode 100644 index b9c5684..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/Abstract.txt +++ /dev/null @@ -1,67 +0,0 @@ -This is socket test server for the Keil MCB4300 evaluation board. -The example runs both CHARGEN and ECHO servers for TCP and UDP. -It is based on MW-Network and uses BSD sockets for the implementation. - -The SockServer is able to accept 7 connections simultaneously: -- 2 concurrent TCP echo sessions, -- 2 concurrent TCP chargen sessions, -- 1 concurrent TCP discard session, -- 1 socket UDP echo session, -- 1 socket UDP chargen session, -- 1 socket TCP test assistant session. - -Note: -- Use Network system viewer to see the assigned IP address of the server. -- Character ESC (0x1b) terminates TCP session. - - -ECHO -==== -Open a telnet session to your test platform at port 7. -For example: - -telnet 192.168.1.100 7 - -Then, enter in the telnet a few characters and you will see that the characters -are echoed back to you. In telnet you will see all duplicate characters: - -aabbccddee -kkwwaa -tteesstt - - -CHARGEN -======= - -Open a telnet session to your test platform at port 19. -For example: - -telnet 192.168.1.100 19 - -You will see a pattern similar to the following on streaming by on your -screen: - -ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01 -BCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012 -CDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123 -DEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01234 -EFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012345 -FGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456 -GHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01234567 -HIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012345678 -IJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789 -JKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789: -KLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:; -LMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:;< -MNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:;<= - - -DISCARD -======= - -Open a telnet session to your test platform at port 9. -For example: - -telnet 192.168.1.100 9 - -The service discards all received characters. diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/CMSIS/RTX_Config.c b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/CMSIS/RTX_Config.c deleted file mode 100644 index e487101..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/CMSIS/RTX_Config.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.1.0 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration - * - * ----------------------------------------------------------------------------- - */ - -#include "cmsis_compiler.h" -#include "rtx_os.h" - -// OS Idle Thread -__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { - (void)argument; - - for (;;) {} -} - -// OS Error Callback function -__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { - (void)object_id; - - switch (code) { - case osRtxErrorStackUnderflow: - // Stack overflow detected for thread (thread_id=object_id) - break; - case osRtxErrorISRQueueOverflow: - // ISR Queue overflow detected when inserting object (object_id) - break; - case osRtxErrorTimerQueueOverflow: - // User Timer Callback Queue overflow detected for timer (timer_id=object_id) - break; - case osRtxErrorClibSpace: - // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM - break; - case osRtxErrorClibMutex: - // Standard C/C++ library mutex initialization failed - break; - default: - // Reserved - break; - } - for (;;) {} -//return 0U; -} diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/CMSIS/RTX_Config.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/CMSIS/RTX_Config.h deleted file mode 100644 index 89e82f9..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/CMSIS/RTX_Config.h +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Copyright (c) 2013-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.5.0 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration definitions - * - * ----------------------------------------------------------------------------- - */ - -#ifndef RTX_CONFIG_H_ -#define RTX_CONFIG_H_ - -#ifdef _RTE_ -#include "RTE_Components.h" -#ifdef RTE_RTX_CONFIG_H -#include RTE_RTX_CONFIG_H -#endif -#endif - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Configuration -// ======================= - -// Global Dynamic Memory size [bytes] <0-1073741824:8> -// Defines the combined global dynamic memory size. -// Default: 4096 -#ifndef OS_DYNAMIC_MEM_SIZE -#define OS_DYNAMIC_MEM_SIZE 4096 -#endif - -// Kernel Tick Frequency [Hz] <1-1000000> -// Defines base time unit for delays and timeouts. -// Default: 1000 (1ms tick) -#ifndef OS_TICK_FREQ -#define OS_TICK_FREQ 1000 -#endif - -// Round-Robin Thread switching -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN_ENABLE -#define OS_ROBIN_ENABLE 1 -#endif - -// Round-Robin Timeout <1-1000> -// Defines how many ticks a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBIN_TIMEOUT -#define OS_ROBIN_TIMEOUT 5 -#endif - -// - -// ISR FIFO Queue -// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries -// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries -// RTOS Functions called from ISR store requests to this buffer. -// Default: 16 entries -#ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 16 -#endif - -// Object Memory usage counters -// Enables object memory usage counters (requires RTX source variant). -#ifndef OS_OBJ_MEM_USAGE -#define OS_OBJ_MEM_USAGE 0 -#endif - -// - -// Thread Configuration -// ======================= - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_THREAD_OBJ_MEM -#define OS_THREAD_OBJ_MEM 0 -#endif - -// Number of user Threads <1-1000> -// Defines maximum number of user threads that can be active at the same time. -// Applies to user threads with system provided memory for control blocks. -#ifndef OS_THREAD_NUM -#define OS_THREAD_NUM 1 -#endif - -// Number of user Threads with default Stack size <0-1000> -// Defines maximum number of user threads with default stack size. -// Applies to user threads with zero stack size specified. -#ifndef OS_THREAD_DEF_STACK_NUM -#define OS_THREAD_DEF_STACK_NUM 0 -#endif - -// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> -// Defines the combined stack size for user threads with user-provided stack size. -// Applies to user threads with user-provided stack size and system provided memory for stack. -// Default: 0 -#ifndef OS_THREAD_USER_STACK_SIZE -#define OS_THREAD_USER_STACK_SIZE 0 -#endif - -// - -// Default Thread Stack size [bytes] <96-1073741824:8> -// Defines stack size for threads with zero stack size specified. -// Default: 256 -#ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 400 -#endif - -// Idle Thread Stack size [bytes] <72-1073741824:8> -// Defines stack size for Idle thread. -// Default: 256 -#ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 256 -#endif - -// Idle Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_IDLE_THREAD_TZ_MOD_ID -#define OS_IDLE_THREAD_TZ_MOD_ID 0 -#endif - -// Stack overrun checking -// Enables stack overrun check at thread switch. -// Enabling this option increases slightly the execution time of a thread switch. -#ifndef OS_STACK_CHECK -#define OS_STACK_CHECK 1 -#endif - -// Stack usage watermark -// Initializes thread stack with watermark pattern for analyzing stack usage. -// Enabling this option increases significantly the execution time of thread creation. -#ifndef OS_STACK_WATERMARK -#define OS_STACK_WATERMARK 0 -#endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_PRIVILEGE_MODE -#define OS_PRIVILEGE_MODE 1 -#endif - -// - -// Timer Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_TIMER_OBJ_MEM -#define OS_TIMER_OBJ_MEM 0 -#endif - -// Number of Timer objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_TIMER_NUM -#define OS_TIMER_NUM 1 -#endif - -// - -// Timer Thread Priority -// <8=> Low -// <16=> Below Normal <24=> Normal <32=> Above Normal -// <40=> High -// <48=> Realtime -// Defines priority for timer thread -// Default: High -#ifndef OS_TIMER_THREAD_PRIO -#define OS_TIMER_THREAD_PRIO 40 -#endif - -// Timer Thread Stack size [bytes] <0-1073741824:8> -// Defines stack size for Timer thread. -// May be set to 0 when timers are not used. -// Default: 256 -#ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 256 -#endif - -// Timer Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_TIMER_THREAD_TZ_MOD_ID -#define OS_TIMER_THREAD_TZ_MOD_ID 0 -#endif - -// Timer Callback Queue entries <0-256> -// Number of concurrent active timer callback functions. -// May be set to 0 when timers are not used. -// Default: 4 -#ifndef OS_TIMER_CB_QUEUE -#define OS_TIMER_CB_QUEUE 4 -#endif - -// - -// Event Flags Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_EVFLAGS_OBJ_MEM -#define OS_EVFLAGS_OBJ_MEM 0 -#endif - -// Number of Event Flags objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_EVFLAGS_NUM -#define OS_EVFLAGS_NUM 1 -#endif - -// - -// - -// Mutex Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MUTEX_OBJ_MEM -#define OS_MUTEX_OBJ_MEM 0 -#endif - -// Number of Mutex objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MUTEX_NUM -#define OS_MUTEX_NUM 1 -#endif - -// - -// - -// Semaphore Configuration -// ========================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_SEMAPHORE_OBJ_MEM -#define OS_SEMAPHORE_OBJ_MEM 0 -#endif - -// Number of Semaphore objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_SEMAPHORE_NUM -#define OS_SEMAPHORE_NUM 1 -#endif - -// - -// - -// Memory Pool Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MEMPOOL_OBJ_MEM -#define OS_MEMPOOL_OBJ_MEM 0 -#endif - -// Number of Memory Pool objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MEMPOOL_NUM -#define OS_MEMPOOL_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MEMPOOL_DATA_SIZE -#define OS_MEMPOOL_DATA_SIZE 0 -#endif - -// - -// - -// Message Queue Configuration -// ============================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MSGQUEUE_OBJ_MEM -#define OS_MSGQUEUE_OBJ_MEM 0 -#endif - -// Number of Message Queue objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MSGQUEUE_NUM -#define OS_MSGQUEUE_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MSGQUEUE_DATA_SIZE -#define OS_MSGQUEUE_DATA_SIZE 0 -#endif - -// - -// - -// Event Recorder Configuration -// =============================== - -// Global Initialization -// Initialize Event Recorder during 'osKernelInitialize'. -#ifndef OS_EVR_INIT -#define OS_EVR_INIT 0 -#endif - -// Start recording -// Start event recording after initialization. -#ifndef OS_EVR_START -#define OS_EVR_START 1 -#endif - -// Global Event Filter Setup -// Initial recording level applied to all components. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_LEVEL -#define OS_EVR_LEVEL 0x00U -#endif - -// RTOS Event Filter Setup -// Recording levels for RTX components. -// Only applicable if events for the respective component are generated. - -// Memory Management -// Recording level for Memory Management events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMORY_LEVEL -#define OS_EVR_MEMORY_LEVEL 0x01U -#endif - -// Kernel -// Recording level for Kernel events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_KERNEL_LEVEL -#define OS_EVR_KERNEL_LEVEL 0x01U -#endif - -// Thread -// Recording level for Thread events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THREAD_LEVEL -#define OS_EVR_THREAD_LEVEL 0x05U -#endif - -// Generic Wait -// Recording level for Generic Wait events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_WAIT_LEVEL -#define OS_EVR_WAIT_LEVEL 0x01U -#endif - -// Thread Flags -// Recording level for Thread Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THFLAGS_LEVEL -#define OS_EVR_THFLAGS_LEVEL 0x01U -#endif - -// Event Flags -// Recording level for Event Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_EVFLAGS_LEVEL -#define OS_EVR_EVFLAGS_LEVEL 0x01U -#endif - -// Timer -// Recording level for Timer events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_TIMER_LEVEL -#define OS_EVR_TIMER_LEVEL 0x01U -#endif - -// Mutex -// Recording level for Mutex events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MUTEX_LEVEL -#define OS_EVR_MUTEX_LEVEL 0x01U -#endif - -// Semaphore -// Recording level for Semaphore events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_SEMAPHORE_LEVEL -#define OS_EVR_SEMAPHORE_LEVEL 0x01U -#endif - -// Memory Pool -// Recording level for Memory Pool events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMPOOL_LEVEL -#define OS_EVR_MEMPOOL_LEVEL 0x01U -#endif - -// Message Queue -// Recording level for Message Queue events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MSGQUEUE_LEVEL -#define OS_EVR_MSGQUEUE_LEVEL 0x01U -#endif - -// - -// - -// RTOS Event Generation -// Enables event generation for RTX components (requires RTX source variant). - -// Memory Management -// Enables Memory Management event generation. -#ifndef OS_EVR_MEMORY -#define OS_EVR_MEMORY 1 -#endif - -// Kernel -// Enables Kernel event generation. -#ifndef OS_EVR_KERNEL -#define OS_EVR_KERNEL 1 -#endif - -// Thread -// Enables Thread event generation. -#ifndef OS_EVR_THREAD -#define OS_EVR_THREAD 1 -#endif - -// Generic Wait -// Enables Generic Wait event generation. -#ifndef OS_EVR_WAIT -#define OS_EVR_WAIT 1 -#endif - -// Thread Flags -// Enables Thread Flags event generation. -#ifndef OS_EVR_THFLAGS -#define OS_EVR_THFLAGS 1 -#endif - -// Event Flags -// Enables Event Flags event generation. -#ifndef OS_EVR_EVFLAGS -#define OS_EVR_EVFLAGS 1 -#endif - -// Timer -// Enables Timer event generation. -#ifndef OS_EVR_TIMER -#define OS_EVR_TIMER 1 -#endif - -// Mutex -// Enables Mutex event generation. -#ifndef OS_EVR_MUTEX -#define OS_EVR_MUTEX 1 -#endif - -// Semaphore -// Enables Semaphore event generation. -#ifndef OS_EVR_SEMAPHORE -#define OS_EVR_SEMAPHORE 1 -#endif - -// Memory Pool -// Enables Memory Pool event generation. -#ifndef OS_EVR_MEMPOOL -#define OS_EVR_MEMPOOL 1 -#endif - -// Message Queue -// Enables Message Queue event generation. -#ifndef OS_EVR_MSGQUEUE -#define OS_EVR_MSGQUEUE 1 -#endif - -// - -// - -// Number of Threads which use standard C/C++ library libspace -// (when thread specific memory allocation is not used). -#if (OS_THREAD_OBJ_MEM == 0) -#define OS_THREAD_LIBSPACE_NUM 4 -#else -#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM -#endif - -//------------- <<< end of configuration section >>> --------------------------- - -#endif // RTX_CONFIG_H_ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/RTE_Device.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/RTE_Device.h deleted file mode 100644 index b33687b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/RTE_Device.h +++ /dev/null @@ -1,2484 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V2.2.1 - * - * Project: RTE Device Configuration for NXP LPC43xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -// USB0 Controller [Driver_USBD0 and Driver_USBH0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host -#define RTE_USB_USB0 0 - -// Pin Configuration -// USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3 -// VBUS drive signal (towards external charge pump or power management unit). -#define RTE_USB0_PPWR_ID 1 -#if (RTE_USB0_PPWR_ID == 0) - #define RTE_USB0_PPWR_PIN_EN 0 -#elif (RTE_USB0_PPWR_ID == 1) - #define RTE_USB0_PPWR_PORT 1 - #define RTE_USB0_PPWR_BIT 7 - #define RTE_USB0_PPWR_FUNC 4 -#elif (RTE_USB0_PPWR_ID == 2) - #define RTE_USB0_PPWR_PORT 2 - #define RTE_USB0_PPWR_BIT 0 - #define RTE_USB0_PPWR_FUNC 3 -#elif (RTE_USB0_PPWR_ID == 3) - #define RTE_USB0_PPWR_PORT 2 - #define RTE_USB0_PPWR_BIT 3 - #define RTE_USB0_PPWR_FUNC 7 -#elif (RTE_USB0_PPWR_ID == 4) - #define RTE_USB0_PPWR_PORT 6 - #define RTE_USB0_PPWR_BIT 3 - #define RTE_USB0_PPWR_FUNC 1 -#else - #error "Invalid RTE_USB0_PPWR Pin Configuration!" -#endif -#ifndef RTE_USB0_PPWR_PIN_EN - #define RTE_USB0_PPWR_PIN_EN 1 -#endif -// USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0 -// Port power fault signal indicating overcurrent condition. -// This signal monitors over-current on the USB bus -// (external circuitry required to detect over-current condition). -#define RTE_USB0_PWR_FAULT_ID 1 -#if (RTE_USB0_PWR_FAULT_ID == 0) - #define RTE_USB0_PWR_FAULT_PIN_EN 0 -#elif (RTE_USB0_PWR_FAULT_ID == 1) - #define RTE_USB0_PWR_FAULT_PORT 1 - #define RTE_USB0_PWR_FAULT_BIT 5 - #define RTE_USB0_PWR_FAULT_FUNC 4 -#elif (RTE_USB0_PWR_FAULT_ID == 2) - #define RTE_USB0_PWR_FAULT_PORT 2 - #define RTE_USB0_PWR_FAULT_BIT 1 - #define RTE_USB0_PWR_FAULT_FUNC 3 -#elif (RTE_USB0_PWR_FAULT_ID == 3) - #define RTE_USB0_PWR_FAULT_PORT 2 - #define RTE_USB0_PWR_FAULT_BIT 4 - #define RTE_USB0_PWR_FAULT_FUNC 7 -#elif (RTE_USB0_PWR_FAULT_ID == 4) - #define RTE_USB0_PWR_FAULT_PORT 6 - #define RTE_USB0_PWR_FAULT_BIT 6 - #define RTE_USB0_PWR_FAULT_FUNC 3 -#elif (RTE_USB0_PWR_FAULT_ID == 5) - #define RTE_USB0_PWR_FAULT_PORT 8 - #define RTE_USB0_PWR_FAULT_BIT 0 - #define RTE_USB0_PWR_FAULT_FUNC 1 -#else - #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!" -#endif -#ifndef RTE_USB0_PWR_FAULT_PIN_EN - #define RTE_USB0_PWR_FAULT_PIN_EN 1 -#endif -// USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2 -// USB0 port indicator LED control output 0 -#define RTE_USB0_IND0_ID 1 -#if (RTE_USB0_IND0_ID == 0) - #define RTE_USB0_IND0_PIN_EN 0 -#elif (RTE_USB0_IND0_ID == 1) - #define RTE_USB0_IND0_PORT 1 - #define RTE_USB0_IND0_BIT 4 - #define RTE_USB0_IND0_FUNC 4 -#elif (RTE_USB0_IND0_ID == 2) - #define RTE_USB0_IND0_PORT 2 - #define RTE_USB0_IND0_BIT 5 - #define RTE_USB0_IND0_FUNC 7 -#elif (RTE_USB0_IND0_ID == 3) - #define RTE_USB0_IND0_PORT 2 - #define RTE_USB0_IND0_BIT 6 - #define RTE_USB0_IND0_FUNC 3 -#elif (RTE_USB0_IND0_ID == 4) - #define RTE_USB0_IND0_PORT 6 - #define RTE_USB0_IND0_BIT 8 - #define RTE_USB0_IND0_FUNC 3 -#elif (RTE_USB0_IND0_ID == 5) - #define RTE_USB0_IND0_PORT 8 - #define RTE_USB0_IND0_BIT 2 - #define RTE_USB0_IND0_FUNC 1 -#else - #error "Invalid RTE_USB0_IND0 Pin Configuration!" -#endif -#ifndef RTE_USB0_IND0_PIN_EN - #define RTE_USB0_IND0_PIN_EN 1 -#endif -// USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1 -// USB0 port indicator LED control output 1 -#define RTE_USB0_IND1_ID 1 -#if (RTE_USB0_IND1_ID == 0) - #define RTE_USB0_IND1_PIN_EN 0 -#elif (RTE_USB0_IND1_ID == 1) - #define RTE_USB0_IND1_PORT 1 - #define RTE_USB0_IND1_BIT 3 - #define RTE_USB0_IND1_FUNC 4 -#elif (RTE_USB0_IND1_ID == 2) - #define RTE_USB0_IND1_PORT 2 - #define RTE_USB0_IND1_BIT 2 - #define RTE_USB0_IND1_FUNC 3 -#elif (RTE_USB0_IND1_ID == 3) - #define RTE_USB0_IND1_PORT 6 - #define RTE_USB0_IND1_BIT 7 - #define RTE_USB0_IND1_FUNC 3 -#elif (RTE_USB0_IND1_ID == 4) - #define RTE_USB0_IND1_PORT 8 - #define RTE_USB0_IND1_BIT 1 - #define RTE_USB0_IND1_FUNC 1 -#else - #error "Invalid RTE_USB0_IND1 Pin Configuration!" -#endif -#ifndef RTE_USB0_IND1_PIN_EN - #define RTE_USB0_IND1_PIN_EN 1 -#endif -// Pin Configuration - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -// High-speed -// Enable high-speed functionality -#define RTE_USB_USB0_HS_EN 0 -// Device [Driver_USBD0] -// USB0 Controller [Driver_USBD0 and Driver_USBH0] - -// USB1 Controller [Driver_USBD1 and Driver_USBH1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_USB1 0 - -// Pin Configuration -// USB1_PPWR (Host) <0=>Not used <1=>P9_5 -// VBUS drive signal (towards external charge pump or power management unit). -#define RTE_USB1_PPWR_ID 1 -#if (RTE_USB1_PPWR_ID == 0) - #define RTE_USB1_PPWR_PIN_EN 0 -#elif (RTE_USB1_PPWR_ID == 1) - #define RTE_USB1_PPWR_PORT 9 - #define RTE_USB1_PPWR_BIT 5 - #define RTE_USB1_PPWR_FUNC 2 -#else - #error "Invalid RTE_USB1_PPWR Pin Configuration!" -#endif -#ifndef RTE_USB1_PPWR_PIN_EN - #define RTE_USB1_PPWR_PIN_EN 1 -#endif -// USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6 -// Port power fault signal indicating overcurrent condition. -// This signal monitors over-current on the USB bus -// (external circuitry required to detect over-current condition). -#define RTE_USB1_PWR_FAULT_ID 1 -#if (RTE_USB1_PWR_FAULT_ID == 0) - #define RTE_USB1_PWR_FAULT_PIN_EN 0 -#elif (RTE_USB1_PWR_FAULT_ID == 1) - #define RTE_USB1_PWR_FAULT_PORT 9 - #define RTE_USB1_PWR_FAULT_BIT 6 - #define RTE_USB1_PWR_FAULT_FUNC 2 -#else - #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!" -#endif -#ifndef RTE_USB1_PWR_FAULT_PIN_EN - #define RTE_USB1_PWR_FAULT_PIN_EN 1 -#endif -// USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4 -// USB1 port indicator LED control output 0 -#define RTE_USB1_IND0_ID 1 -#if (RTE_USB1_IND0_ID == 0) - #define RTE_USB1_IND0_PIN_EN 0 -#elif (RTE_USB1_IND0_ID == 1) - #define RTE_USB1_IND0_PORT 3 - #define RTE_USB1_IND0_BIT 2 - #define RTE_USB1_IND0_FUNC 3 -#elif (RTE_USB1_IND0_ID == 2) - #define RTE_USB1_IND0_PORT 9 - #define RTE_USB1_IND0_BIT 4 - #define RTE_USB1_IND0_FUNC 2 -#else - #error "Invalid RTE_USB1_IND0 Pin Configuration!" -#endif -#ifndef RTE_USB1_IND0_PIN_EN - #define RTE_USB1_IND0_PIN_EN 1 -#endif -// USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3 -// USB1 port indicator LED control output 1 -#define RTE_USB1_IND1_ID 1 -#if (RTE_USB1_IND1_ID == 0) - #define RTE_USB1_IND1_PIN_EN 0 -#elif (RTE_USB1_IND1_ID == 1) - #define RTE_USB1_IND1_PORT 3 - #define RTE_USB1_IND1_BIT 1 - #define RTE_USB1_IND1_FUNC 3 -#elif (RTE_USB1_IND1_ID == 2) - #define RTE_USB1_IND1_PORT 9 - #define RTE_USB1_IND1_BIT 3 - #define RTE_USB1_IND1_FUNC 2 -#else - #error "Invalid RTE_USB1_IND1 Pin Configuration!" -#endif -#ifndef RTE_USB1_IND1_PIN_EN - #define RTE_USB1_IND1_PIN_EN 1 -#endif - -// On-chip full-speed PHY -#define RTE_USB_USB1_FS_PHY_EN 1 - -// USB1_VBUS (Device) <0=>Not used <1=>P2_5 -// Monitors the presence of USB1 bus power. -#define RTE_USB1_VBUS_ID 1 -#if (RTE_USB1_VBUS_ID == 0) - #define RTE_USB1_VBUS_PIN_EN 0 -#elif (RTE_USB1_VBUS_ID == 1) - #define RTE_USB1_VBUS_PORT 2 - #define RTE_USB1_VBUS_BIT 5 - #define RTE_USB1_VBUS_FUNC 2 -#else - #error "Invalid RTE_USB1_VBUS Pin Configuration!" -#endif -#ifndef RTE_USB1_VBUS_PIN_EN - #define RTE_USB1_VBUS_PIN_EN 1 -#endif -// On-chip full-speed PHY - -// External high-speed ULPI PHY (UTMI+ Low Pin Interface) -#define RTE_USB_USB1_HS_PHY_EN 0 - -// USB1_ULPI_CLK <0=>P8_8 <1=>PC_0 -// USB1 ULPI link CLK signal. -// 60 MHz clock generated by the PHY. -#define RTE_USB1_ULPI_CLK_ID 0 -#if (RTE_USB1_ULPI_CLK_ID == 0) - #define RTE_USB1_ULPI_CLK_PORT 8 - #define RTE_USB1_ULPI_CLK_BIT 8 - #define RTE_USB1_ULPI_CLK_FUNC 1 -#elif (RTE_USB1_ULPI_CLK_ID == 1) - #define RTE_USB1_ULPI_CLK_PORT 0xC - #define RTE_USB1_ULPI_CLK_BIT 0 - #define RTE_USB1_ULPI_CLK_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!" -#endif -// USB1_ULPI_DIR <0=>PB_1 <1=>PC_11 -// USB1 ULPI link DIR signal. -// Controls the ULPI data line direction. -#define RTE_USB1_ULPI_DIR_ID 0 -#if (RTE_USB1_ULPI_DIR_ID == 0) - #define RTE_USB1_ULPI_DIR_PORT 0xB - #define RTE_USB1_ULPI_DIR_BIT 1 - #define RTE_USB1_ULPI_DIR_FUNC 1 -#elif (RTE_USB1_ULPI_DIR_ID == 1) - #define RTE_USB1_ULPI_DIR_PORT 0xC - #define RTE_USB1_ULPI_DIR_BIT 11 - #define RTE_USB1_ULPI_DIR_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!" -#endif -// USB1_ULPI_STP <0=>P8_7 <1=>PC_10 -// USB1 ULPI link STP signal. -// Asserted to end or interrupt transfers to the PHY. -#define RTE_USB1_ULPI_STP_ID 0 -#if (RTE_USB1_ULPI_STP_ID == 0) - #define RTE_USB1_ULPI_STP_PORT 8 - #define RTE_USB1_ULPI_STP_BIT 7 - #define RTE_USB1_ULPI_STP_FUNC 1 -#elif (RTE_USB1_ULPI_STP_ID == 1) - #define RTE_USB1_ULPI_STP_PORT 0xC - #define RTE_USB1_ULPI_STP_BIT 10 - #define RTE_USB1_ULPI_STP_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!" -#endif -// USB1_ULPI_NXT <0=>P8_6 <1=>PC_9 -// USB1 ULPI link NXT signal. -// Data flow control signal from the PHY. -#define RTE_USB1_ULPI_NXT_ID 0 -#if (RTE_USB1_ULPI_NXT_ID == 0) - #define RTE_USB1_ULPI_NXT_PORT 8 - #define RTE_USB1_ULPI_NXT_BIT 6 - #define RTE_USB1_ULPI_NXT_FUNC 1 -#elif (RTE_USB1_ULPI_NXT_ID == 1) - #define RTE_USB1_ULPI_NXT_PORT 0xC - #define RTE_USB1_ULPI_NXT_BIT 9 - #define RTE_USB1_ULPI_NXT_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!" -#endif -// USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11 -// USB1 ULPI link bidirectional data line 0. -#define RTE_USB1_ULPI_D0_ID 0 -#if (RTE_USB1_ULPI_D0_ID == 0) - #define RTE_USB1_ULPI_D0_PORT 8 - #define RTE_USB1_ULPI_D0_BIT 5 - #define RTE_USB1_ULPI_D0_FUNC 1 -#elif (RTE_USB1_ULPI_D0_ID == 1) - #define RTE_USB1_ULPI_D0_PORT 0xC - #define RTE_USB1_ULPI_D0_BIT 8 - #define RTE_USB1_ULPI_D0_FUNC 1 -#elif (RTE_USB1_ULPI_D0_ID == 2) - #define RTE_USB1_ULPI_D0_PORT 0xD - #define RTE_USB1_ULPI_D0_BIT 11 - #define RTE_USB1_ULPI_D0_FUNC 5 -#else - #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!" -#endif -// USB1_ULPI_D1 <0=>P8_4 <1=>PC_7 -// USB1 ULPI link bidirectional data line 1. -#define RTE_USB1_ULPI_D1_ID 0 -#if (RTE_USB1_ULPI_D1_ID == 0) - #define RTE_USB1_ULPI_D1_PORT 8 - #define RTE_USB1_ULPI_D1_BIT 4 - #define RTE_USB1_ULPI_D1_FUNC 1 -#elif (RTE_USB1_ULPI_D1_ID == 1) - #define RTE_USB1_ULPI_D1_PORT 0xC - #define RTE_USB1_ULPI_D1_BIT 7 - #define RTE_USB1_ULPI_D1_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!" -#endif -// USB1_ULPI_D2 <0=>P8_3 <1=>PC_6 -// USB1 ULPI link bidirectional data line 2. -#define RTE_USB1_ULPI_D2_ID 0 -#if (RTE_USB1_ULPI_D2_ID == 0) - #define RTE_USB1_ULPI_D2_PORT 8 - #define RTE_USB1_ULPI_D2_BIT 3 - #define RTE_USB1_ULPI_D2_FUNC 1 -#elif (RTE_USB1_ULPI_D2_ID == 1) - #define RTE_USB1_ULPI_D2_PORT 0xC - #define RTE_USB1_ULPI_D2_BIT 6 - #define RTE_USB1_ULPI_D2_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!" -#endif -// USB1_ULPI_D3 <0=>PB_6 <1=>PC_5 -// USB1 ULPI link bidirectional data line 3. -#define RTE_USB1_ULPI_D3_ID 0 -#if (RTE_USB1_ULPI_D3_ID == 0) - #define RTE_USB1_ULPI_D3_PORT 0xB - #define RTE_USB1_ULPI_D3_BIT 6 - #define RTE_USB1_ULPI_D3_FUNC 1 -#elif (RTE_USB1_ULPI_D3_ID == 1) - #define RTE_USB1_ULPI_D3_PORT 0xC - #define RTE_USB1_ULPI_D3_BIT 5 - #define RTE_USB1_ULPI_D3_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!" -#endif -// USB1_ULPI_D4 <0=>PB_5 <1=>PC_4 -// USB1 ULPI link bidirectional data line 4. -#define RTE_USB1_ULPI_D4_ID 0 -#if (RTE_USB1_ULPI_D4_ID == 0) - #define RTE_USB1_ULPI_D4_PORT 0xB - #define RTE_USB1_ULPI_D4_BIT 5 - #define RTE_USB1_ULPI_D4_FUNC 1 -#elif (RTE_USB1_ULPI_D4_ID == 1) - #define RTE_USB1_ULPI_D4_PORT 0xC - #define RTE_USB1_ULPI_D4_BIT 4 - #define RTE_USB1_ULPI_D4_FUNC 1 -#else - #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!" -#endif -// USB1_ULPI_D5 <0=>PB_4 <1=>PC_3 -// USB1 ULPI link bidirectional data line 5. -#define RTE_USB1_ULPI_D5_ID 0 -#if (RTE_USB1_ULPI_D5_ID == 0) - #define RTE_USB1_ULPI_D5_PORT 0xB - #define RTE_USB1_ULPI_D5_BIT 4 - #define RTE_USB1_ULPI_D5_FUNC 1 -#elif (RTE_USB1_ULPI_D5_ID == 1) - #define RTE_USB1_ULPI_D5_PORT 0xC - #define RTE_USB1_ULPI_D5_BIT 3 - #define RTE_USB1_ULPI_D5_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!" -#endif -// USB1_ULPI_D6 <0=>PB_3 <1=>PC_2 -// USB1 ULPI link bidirectional data line 6. -#define RTE_USB1_ULPI_D6_ID 0 -#if (RTE_USB1_ULPI_D6_ID == 0) - #define RTE_USB1_ULPI_D6_PORT 0xB - #define RTE_USB1_ULPI_D6_BIT 3 - #define RTE_USB1_ULPI_D6_FUNC 1 -#elif (RTE_USB1_ULPI_D6_ID == 1) - #define RTE_USB1_ULPI_D6_PORT 0xC - #define RTE_USB1_ULPI_D6_BIT 2 - #define RTE_USB1_ULPI_D6_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!" -#endif -// USB1_ULPI_D7 <0=>PB_2 <1=>PC_1 -// USB1 ULPI link bidirectional data line 7. -#define RTE_USB1_ULPI_D7_ID 0 -#if (RTE_USB1_ULPI_D7_ID == 0) - #define RTE_USB1_ULPI_D7_PORT 0xB - #define RTE_USB1_ULPI_D7_BIT 2 - #define RTE_USB1_ULPI_D7_FUNC 1 -#elif (RTE_USB1_ULPI_D7_ID == 1) - #define RTE_USB1_ULPI_D7_PORT 0xC - #define RTE_USB1_ULPI_D7_BIT 1 - #define RTE_USB1_ULPI_D7_FUNC 0 -#else - #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!" -#endif -// External high-speed ULPI PHY (UTMI+ Low Pin Interface) -// Pin Configuration -// USB1 Controller [Driver_USBD1 and Driver_USBH1] - -// ENET (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ENET 1 - -// MII (Media Independent Interface) -#define RTE_ENET_MII 0 - -// ENET_TXD0 Pin <0=>P1_18 -#define RTE_ENET_MII_TXD0_PORT_ID 0 -#if (RTE_ENET_MII_TXD0_PORT_ID == 0) - #define RTE_ENET_MII_TXD0_PORT 1 - #define RTE_ENET_MII_TXD0_PIN 18 - #define RTE_ENET_MII_TXD0_FUNC 3 -#else - #error "Invalid ENET_TXD0 Pin Configuration!" -#endif -// ENET_TXD1 Pin <0=>P1_20 -#define RTE_ENET_MII_TXD1_PORT_ID 0 -#if (RTE_ENET_MII_TXD1_PORT_ID == 0) - #define RTE_ENET_MII_TXD1_PORT 1 - #define RTE_ENET_MII_TXD1_PIN 20 - #define RTE_ENET_MII_TXD1_FUNC 3 -#else - #error "Invalid ENET_TXD1 Pin Configuration!" -#endif -// ENET_TXD2 Pin <0=>P9_4 <1=>PC_2 -#define RTE_ENET_MII_TXD2_PORT_ID 0 -#if (RTE_ENET_MII_TXD2_PORT_ID == 0) - #define RTE_ENET_MII_TXD2_PORT 9 - #define RTE_ENET_MII_TXD2_PIN 4 - #define RTE_ENET_MII_TXD2_FUNC 5 -#elif (RTE_ENET_MII_TXD2_PORT_ID == 1) - #define RTE_ENET_MII_TXD2_PORT 0xC - #define RTE_ENET_MII_TXD2_PIN 2 - #define RTE_ENET_MII_TXD2_FUNC 3 -#else - #error "Invalid ENET_TXD2 Pin Configuration!" -#endif -// ENET_TXD3 Pin <0=>P9_5 <1=>PC_3 -#define RTE_ENET_MII_TXD3_PORT_ID 0 -#if (RTE_ENET_MII_TXD3_PORT_ID == 0) - #define RTE_ENET_MII_TXD3_PORT 9 - #define RTE_ENET_MII_TXD3_PIN 5 - #define RTE_ENET_MII_TXD3_FUNC 5 -#elif (RTE_ENET_MII_TXD3_PORT_ID == 1) - #define RTE_ENET_MII_TXD3_PORT 0xC - #define RTE_ENET_MII_TXD3_PIN 3 - #define RTE_ENET_MII_TXD3_FUNC 3 -#else - #error "Invalid ENET_TXD3 Pin Configuration!" -#endif -// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 -#define RTE_ENET_MII_TX_EN_PORT_ID 0 -#if (RTE_ENET_MII_TX_EN_PORT_ID == 0) - #define RTE_ENET_MII_TX_EN_PORT 0 - #define RTE_ENET_MII_TX_EN_PIN 1 - #define RTE_ENET_MII_TX_EN_FUNC 6 -#elif (RTE_ENET_MII_TX_EN_PORT_ID == 1) - #define RTE_ENET_MII_TX_EN_PORT 0xC - #define RTE_ENET_MII_TX_EN_PIN 4 - #define RTE_ENET_MII_TX_EN_FUNC 3 -#else - #error "Invalid ENET_TX_EN Pin Configuration!" -#endif -// ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0 -#define RTE_ENET_MII_TX_CLK_PORT_ID 0 -#if (RTE_ENET_MII_TX_CLK_PORT_ID == 0) - #define RTE_ENET_MII_TX_CLK_PORT 1 - #define RTE_ENET_MII_TX_CLK_PIN 19 - #define RTE_ENET_MII_TX_CLK_FUNC 0 -#elif (RTE_ENET_MII_TX_CLK_PORT_ID == 1) - #define RTE_ENET_MII_TX_CLK_PORT 0x10 - #define RTE_ENET_MII_TX_CLK_PIN 0 - #define RTE_ENET_MII_TX_CLK_FUNC 7 -#else - #error "Invalid ENET_TX_CLK Pin Configuration!" -#endif -// ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14 -// Optional signal, rarely used -#define RTE_ENET_MII_TX_ER_PORT_ID 0 -#if (RTE_ENET_MII_TX_ER_PORT_ID == 0) - #define RTE_ENET_MII_TX_ER_PIN_EN 0 -#elif (RTE_ENET_MII_TX_ER_PORT_ID == 1) - #define RTE_ENET_MII_TX_ER_PORT 0xC - #define RTE_ENET_MII_TX_ER_PIN 5 - #define RTE_ENET_MII_TX_ER_FUNC 3 -#elif (RTE_ENET_MII_TX_ER_PORT_ID == 2) - #define RTE_ENET_MII_TX_ER_PORT 0xC - #define RTE_ENET_MII_TX_ER_PIN 14 - #define RTE_ENET_MII_TX_ER_FUNC 6 -#else - #error "Invalid ENET_TX_ER Pin Configuration!" -#endif -#ifndef RTE_ENET_MII_TX_ER_PIN_EN - #define RTE_ENET_MII_TX_ER_PIN_EN 1 -#endif -// ENET_RXD0 Pin <0=>P1_15 -#define RTE_ENET_MII_RXD0_PORT_ID 0 -#if (RTE_ENET_MII_RXD0_PORT_ID == 0) - #define RTE_ENET_MII_RXD0_PORT 1 - #define RTE_ENET_MII_RXD0_PIN 15 - #define RTE_ENET_MII_RXD0_FUNC 3 -#else - #error "Invalid ENET_RXD0 Pin Configuration!" -#endif -// ENET_RXD1 Pin <0=>P0_0 -#define RTE_ENET_MII_RXD1_PORT_ID 0 -#if (RTE_ENET_MII_RXD1_PORT_ID == 0) - #define RTE_ENET_MII_RXD1_PORT 0 - #define RTE_ENET_MII_RXD1_PIN 0 - #define RTE_ENET_MII_RXD1_FUNC 2 -#else - #error "Invalid ENET_RXD1 Pin Configuration!" -#endif -// ENET_RXD2 Pin <0=>P9_3 <1=>PC_6 -#define RTE_ENET_MII_RXD2_PORT_ID 0 -#if (RTE_ENET_MII_RXD2_PORT_ID == 0) - #define RTE_ENET_MII_RXD2_PORT 9 - #define RTE_ENET_MII_RXD2_PIN 3 - #define RTE_ENET_MII_RXD2_FUNC 5 -#elif (RTE_ENET_MII_RXD2_PORT_ID == 1) - #define RTE_ENET_MII_RXD2_PORT 0xC - #define RTE_ENET_MII_RXD2_PIN 6 - #define RTE_ENET_MII_RXD2_FUNC 3 -#else - #error "Invalid ENET_RXD2 Pin Configuration!" -#endif -// ENET_RXD3 Pin <0=>P9_2 <1=>PC_7 -#define RTE_ENET_MII_RXD3_PORT_ID 0 -#if (RTE_ENET_MII_RXD3_PORT_ID == 0) - #define RTE_ENET_MII_RXD3_PORT 9 - #define RTE_ENET_MII_RXD3_PIN 2 - #define RTE_ENET_MII_RXD3_FUNC 5 -#elif (RTE_ENET_MII_RXD3_PORT_ID == 1) - #define RTE_ENET_MII_RXD3_PORT 0xC - #define RTE_ENET_MII_RXD3_PIN 7 - #define RTE_ENET_MII_RXD3_FUNC 3 -#else - #error "Invalid ENET_RXD3 Pin Configuration!" -#endif -// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 -#define RTE_ENET_MII_RX_DV_PORT_ID 0 -#if (RTE_ENET_MII_RX_DV_PORT_ID == 0) - #define RTE_ENET_MII_RX_DV_PORT 1 - #define RTE_ENET_MII_RX_DV_PIN 16 - #define RTE_ENET_MII_RX_DV_FUNC 7 -#elif (RTE_ENET_MII_RX_DV_PORT_ID == 1) - #define RTE_ENET_MII_RX_DV_PORT 0xC - #define RTE_ENET_MII_RX_DV_PIN 8 - #define RTE_ENET_MII_RX_DV_FUNC 3 -#else - #error "Invalid ENET_RX_DV Pin Configuration!" -#endif -// ENET_RX_CLK Pin <0=>PC_0 -#define RTE_ENET_MII_RX_CLK_PORT_ID 0 -#if (RTE_ENET_MII_RX_CLK_PORT_ID == 0) - #define RTE_ENET_MII_RX_CLK_PORT 0xC - #define RTE_ENET_MII_RX_CLK_PIN 0 - #define RTE_ENET_MII_RX_CLK_FUNC 3 -#else - #error "Invalid ENET_RX_CLK Pin Configuration!" -#endif -// ENET_RX_ER Pin <0=>P9_1 <1=>PC_9 -#define RTE_ENET_MII_RX_ER_PORT_ID 0 -#if (RTE_ENET_MII_RX_ER_PORT_ID == 0) - #define RTE_ENET_MII_RX_ER_PORT 9 - #define RTE_ENET_MII_RX_ER_PIN 1 - #define RTE_ENET_MII_RX_ER_FUNC 5 -#elif (RTE_ENET_MII_RX_ER_PORT_ID == 1) - #define RTE_ENET_MII_RX_ER_PORT 0xC - #define RTE_ENET_MII_RX_ER_PIN 9 - #define RTE_ENET_MII_RX_ER_FUNC 3 -#else - #error "Invalid ENET_RX_ER Pin Configuration!" -#endif -// ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6 -#define RTE_ENET_MII_COL_PORT_ID 0 -#if (RTE_ENET_MII_COL_PORT_ID == 0) - #define RTE_ENET_MII_COL_PORT 0 - #define RTE_ENET_MII_COL_PIN 1 - #define RTE_ENET_MII_COL_FUNC 2 -#elif (RTE_ENET_MII_COL_PORT_ID == 1) - #define RTE_ENET_MII_COL_PORT 4 - #define RTE_ENET_MII_COL_PIN 1 - #define RTE_ENET_MII_COL_FUNC 7 -#elif (RTE_ENET_MII_COL_PORT_ID == 2) - #define RTE_ENET_MII_COL_PORT 9 - #define RTE_ENET_MII_COL_PIN 6 - #define RTE_ENET_MII_COL_FUNC 5 -#else - #error "Invalid ENET_COL Pin Configuration!" -#endif -// ENET_CRS Pin <0=>P1_16 <1=>P9_0 -#define RTE_ENET_MII_CRS_PORT_ID 0 -#if (RTE_ENET_MII_CRS_PORT_ID == 0) - #define RTE_ENET_MII_CRS_PORT 1 - #define RTE_ENET_MII_CRS_PIN 16 - #define RTE_ENET_MII_CRS_FUNC 3 -#elif (RTE_ENET_MII_CRS_PORT_ID == 1) - #define RTE_ENET_MII_CRS_PORT 9 - #define RTE_ENET_MII_CRS_PIN 0 - #define RTE_ENET_MII_CRS_FUNC 5 -#else - #error "Invalid ENET_CRS Pin Configuration!" -#endif -// MII (Media Independent Interface) - -// RMII (Reduced Media Independent Interface) -#define RTE_ENET_RMII 1 - -// ENET_TXD0 Pin <0=>P1_18 -#define RTE_ENET_RMII_TXD0_PORT_ID 0 -#if (RTE_ENET_RMII_TXD0_PORT_ID == 0) - #define RTE_ENET_RMII_TXD0_PORT 1 - #define RTE_ENET_RMII_TXD0_PIN 18 - #define RTE_ENET_RMII_TXD0_FUNC 3 -#else - #error "Invalid ENET_TXD0 Pin Configuration!" -#endif -// ENET_TXD1 Pin <0=>P1_20 -#define RTE_ENET_RMII_TXD1_PORT_ID 0 -#if (RTE_ENET_RMII_TXD1_PORT_ID == 0) - #define RTE_ENET_RMII_TXD1_PORT 1 - #define RTE_ENET_RMII_TXD1_PIN 20 - #define RTE_ENET_RMII_TXD1_FUNC 3 -#else - #error "Invalid ENET_TXD1 Pin Configuration!" -#endif -// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 -#define RTE_ENET_RMII_TX_EN_PORT_ID 0 -#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0) - #define RTE_ENET_RMII_TX_EN_PORT 0 - #define RTE_ENET_RMII_TX_EN_PIN 1 - #define RTE_ENET_RMII_TX_EN_FUNC 6 -#elif (RTE_ENET_RMII_TX_EN_PORT_ID == 1) - #define RTE_ENET_RMII_TX_EN_PORT 0xC - #define RTE_ENET_RMII_TX_EN_PIN 4 - #define RTE_ENET_RMII_TX_EN_FUNC 3 -#else - #error "Invalid ENET_TX_EN Pin Configuration!" -#endif -// ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0 -#define RTE_ENET_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0) - #define RTE_ENET_RMII_REF_CLK_PORT 1 - #define RTE_ENET_RMII_REF_CLK_PIN 19 - #define RTE_ENET_RMII_REF_CLK_FUNC 0 -#elif (RTE_ENET_RMII_REF_CLK_PORT_ID == 1) - #define RTE_ENET_RMII_REF_CLK_PORT 0x10 - #define RTE_ENET_RMII_REF_CLK_PIN 0 - #define RTE_ENET_RMII_REF_CLK_FUNC 7 -#else - #error "Invalid ENET_REF_CLK Pin Configuration!" -#endif -// ENET_RXD0 Pin <0=>P1_15 -#define RTE_ENET_RMII_RXD0_PORT_ID 0 -#if (RTE_ENET_RMII_RXD0_PORT_ID == 0) - #define RTE_ENET_RMII_RXD0_PORT 1 - #define RTE_ENET_RMII_RXD0_PIN 15 - #define RTE_ENET_RMII_RXD0_FUNC 3 -#else - #error "Invalid ENET_RXD0 Pin Configuration!" -#endif -// ENET_RXD1 Pin <0=>P0_0 -#define RTE_ENET_RMII_RXD1_PORT_ID 0 -#if (RTE_ENET_RMII_RXD1_PORT_ID == 0) - #define RTE_ENET_RMII_RXD1_PORT 0 - #define RTE_ENET_RMII_RXD1_PIN 0 - #define RTE_ENET_RMII_RXD1_FUNC 2 -#else - #error "Invalid ENET_RXD1 Pin Configuration!" -#endif -// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 -#define RTE_ENET_RMII_RX_DV_PORT_ID 0 -#if (RTE_ENET_RMII_RX_DV_PORT_ID == 0) - #define RTE_ENET_RMII_RX_DV_PORT 1 - #define RTE_ENET_RMII_RX_DV_PIN 16 - #define RTE_ENET_RMII_RX_DV_FUNC 7 -#elif (RTE_ENET_RMII_RX_DV_PORT_ID == 1) - #define RTE_ENET_RMII_RX_DV_PORT 0xC - #define RTE_ENET_RMII_RX_DV_PIN 8 - #define RTE_ENET_RMII_RX_DV_FUNC 3 -#else - #error "Invalid ENET_RX_DV Pin Configuration!" -#endif -// RMII (Reduced Media Independent Interface) - -// MIIM (Management Data Interface) -// ENET_MDIO Pin <0=>P1_17 -#define RTE_ENET_MDI_MDIO_PORT_ID 0 -#if (RTE_ENET_MDI_MDIO_PORT_ID == 0) - #define RTE_ENET_MDI_MDIO_PORT 1 - #define RTE_ENET_MDI_MDIO_PIN 17 - #define RTE_ENET_MDI_MDIO_FUNC 3 -#else - #error "Invalid ENET_MDIO Pin Configuration!" -#endif -// ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1 -#define RTE_ENET_MDI_MDC_PORT_ID 2 -#if (RTE_ENET_MDI_MDC_PORT_ID == 0) - #define RTE_ENET_MDI_MDC_PORT 2 - #define RTE_ENET_MDI_MDC_PIN 0 - #define RTE_ENET_MDI_MDC_FUNC 7 -#elif (RTE_ENET_MDI_MDC_PORT_ID == 1) - #define RTE_ENET_MDI_MDC_PORT 7 - #define RTE_ENET_MDI_MDC_PIN 7 - #define RTE_ENET_MDI_MDC_FUNC 6 -#elif (RTE_ENET_MDI_MDC_PORT_ID == 2) - #define RTE_ENET_MDI_MDC_PORT 0xC - #define RTE_ENET_MDI_MDC_PIN 1 - #define RTE_ENET_MDI_MDC_FUNC 3 -#else - #error "Invalid ENET_MDC Pin Configuration!" -#endif -// MIIM (Management Data Interface) -// ENET (Ethernet Interface) [Driver_ETH_MAC0] - -// SD/MMC Interface [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDMMC 0 - -// SD/MMC Peripheral Bus -// SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2 -#define RTE_SD_CLK_PORT_ID 0 -#if (RTE_SD_CLK_PORT_ID == 0) - #define RTE_SD_CLK_PORT 0xC - #define RTE_SD_CLK_PIN 0 - #define RTE_SD_CLK_FUNC 7 -#elif (RTE_SD_CLK_PORT_ID == 1) - #define RTE_SD_CLK_PORT 0x10 - #define RTE_SD_CLK_PIN 0 - #define RTE_SD_CLK_FUNC 4 -#elif (RTE_SD_CLK_PORT_ID == 2) - #define RTE_SD_CLK_PORT 0x10 - #define RTE_SD_CLK_PIN 2 - #define RTE_SD_CLK_FUNC 4 -#else - #error "Invalid SD_CLK Pin Configuration!" -#endif -// SD_CMD Pin <0=>P1_6 <1=>PC_10 -#define RTE_SD_CMD_PORT_ID 0 -#if (RTE_SD_CMD_PORT_ID == 0) - #define RTE_SD_CMD_PORT 1 - #define RTE_SD_CMD_PIN 6 - #define RTE_SD_CMD_FUNC 7 -#elif (RTE_SD_CMD_PORT_ID == 1) - #define RTE_SD_CMD_PORT 0xC - #define RTE_SD_CMD_PIN 10 - #define RTE_SD_CMD_FUNC 7 -#else - #error "Invalid SD_CMD Pin Configuration!" -#endif -// SD_DAT0 Pin <0=>P1_9 <1=>PC_4 -#define RTE_SD_DAT0_PORT_ID 0 -#if (RTE_SD_DAT0_PORT_ID == 0) - #define RTE_SD_DAT0_PORT 1 - #define RTE_SD_DAT0_PIN 9 - #define RTE_SD_DAT0_FUNC 7 -#elif (RTE_SD_DAT0_PORT_ID == 1) - #define RTE_SD_DAT0_PORT 0xC - #define RTE_SD_DAT0_PIN 4 - #define RTE_SD_DAT0_FUNC 7 -#else - #error "Invalid SD_DAT0 Pin Configuration!" -#endif -// SD_DAT[1 .. 3] -#define RTE_SDMMC_BUS_WIDTH_4 0 -// SD_DAT1 Pin <0=>P1_10 <1=>PC_5 -#define RTE_SD_DAT1_PORT_ID 0 -#if (RTE_SD_DAT1_PORT_ID == 0) - #define RTE_SD_DAT1_PORT 1 - #define RTE_SD_DAT1_PIN 10 - #define RTE_SD_DAT1_FUNC 7 -#elif (RTE_SD_DAT1_PORT_ID == 1) - #define RTE_SD_DAT1_PORT 0xC - #define RTE_SD_DAT1_PIN 5 - #define RTE_SD_DAT1_FUNC 7 -#else - #error "Invalid SD_DAT1 Pin Configuration!" -#endif -// SD_DAT2 Pin <0=>P1_11 <1=>PC_6 -#define RTE_SD_DAT2_PORT_ID 0 -#if (RTE_SD_DAT2_PORT_ID == 0) - #define RTE_SD_DAT2_PORT 1 - #define RTE_SD_DAT2_PIN 11 - #define RTE_SD_DAT2_FUNC 7 -#elif (RTE_SD_DAT2_PORT_ID == 1) - #define RTE_SD_DAT2_PORT 0xC - #define RTE_SD_DAT2_PIN 6 - #define RTE_SD_DAT2_FUNC 7 -#else - #error "Invalid SD_DAT2 Pin Configuration!" -#endif -// SD_DAT3 Pin <0=>P1_12 <1=>PC_7 -#define RTE_SD_DAT3_PORT_ID 0 -#if (RTE_SD_DAT3_PORT_ID == 0) - #define RTE_SD_DAT3_PORT 1 - #define RTE_SD_DAT3_PIN 12 - #define RTE_SD_DAT3_FUNC 7 -#elif (RTE_SD_DAT3_PORT_ID == 1) - #define RTE_SD_DAT3_PORT 0xC - #define RTE_SD_DAT3_PIN 7 - #define RTE_SD_DAT3_FUNC 7 -#else - #error "Invalid SD_DAT3 Pin Configuration!" -#endif -// SD_DAT[1 .. 3] -// SD_DAT[4 .. 7] -#define RTE_SDMMC_BUS_WIDTH_8 0 -// SD_DAT4 Pin <0=>PC_11 -#define RTE_SD_DAT4_PORT_ID 0 -#if (RTE_SD_DAT4_PORT_ID == 0) - #define RTE_SD_DAT4_PORT 0xC - #define RTE_SD_DAT4_PIN 11 - #define RTE_SD_DAT4_FUNC 7 -#else - #error "Invalid SD_DAT4 Pin Configuration!" -#endif -// SD_DAT5 Pin <0=>PC_12 -#define RTE_SD_DAT5_PORT_ID 0 -#if (RTE_SD_DAT5_PORT_ID == 0) - #define RTE_SD_DAT5_PORT 0xC - #define RTE_SD_DAT5_PIN 12 - #define RTE_SD_DAT5_FUNC 7 -#else - #error "Invalid SD_DAT5 Pin Configuration!" -#endif -// SD_DAT6 Pin <0=>PC_13 -#define RTE_SD_DAT6_PORT_ID 0 -#if (RTE_SD_DAT6_PORT_ID == 0) - #define RTE_SD_DAT6_PORT 0xC - #define RTE_SD_DAT6_PIN 13 - #define RTE_SD_DAT6_FUNC 7 -#else - #error "Invalid SD_DAT6 Pin Configuration!" -#endif -// SD_DAT7 Pin <0=>PC_14 -#define RTE_SD_DAT7_PORT_ID 0 -#if (RTE_SD_DAT7_PORT_ID == 0) - #define RTE_SD_DAT7_PORT 0xC - #define RTE_SD_DAT7_PIN 14 - #define RTE_SD_DAT7_FUNC 7 -#else - #error "Invalid SD_DAT7 Pin Configuration!" -#endif -// SD_DAT[4 .. 7] -// SD/MMC Peripheral Bus - -// SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8 -// Configure Pin if exists -#define RTE_SD_CD_PORT_ID 0 -#if (RTE_SD_CD_PORT_ID == 0) - #define RTE_SD_CD_PIN_EN 0 -#elif (RTE_SD_CD_PORT_ID == 1) - #define RTE_SD_CD_PORT 1 - #define RTE_SD_CD_PIN 13 - #define RTE_SD_CD_FUNC 7 -#elif (RTE_SD_CD_PORT_ID == 2) - #define RTE_SD_CD_PORT 0xC - #define RTE_SD_CD_PIN 8 - #define RTE_SD_CD_FUNC 7 -#else - #error "Invalid SD_CD Pin Configuration!" -#endif -#ifndef RTE_SD_CD_PIN_EN - #define RTE_SD_CD_PIN_EN 1 -#endif -// SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10 -// Configure Pin if exists -#define RTE_SD_WP_PORT_ID 0 -#if (RTE_SD_WP_PORT_ID == 0) - #define RTE_SD_WP_PIN_EN 0 -#elif (RTE_SD_WP_PORT_ID == 1) - #define RTE_SD_WP_PORT 0xD - #define RTE_SD_WP_PIN 15 - #define RTE_SD_WP_FUNC 5 -#elif (RTE_SD_WP_PORT_ID == 2) - #define RTE_SD_WP_PORT 0xF - #define RTE_SD_WP_PIN 10 - #define RTE_SD_WP_FUNC 6 -#else - #error "Invalid SD_WP Pin Configuration!" -#endif -#ifndef RTE_SD_WP_PIN_EN - #define RTE_SD_WP_PIN_EN 1 -#endif -// SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1 -// Configure Pin if exists -#define RTE_SD_POW_PORT_ID 0 -#if (RTE_SD_POW_PORT_ID == 0) - #define RTE_SD_POW_PIN_EN 0 -#elif (RTE_SD_POW_PORT_ID == 1) - #define RTE_SD_POW_PORT 1 - #define RTE_SD_POW_PIN 5 - #define RTE_SD_POW_FUNC 7 -#elif (RTE_SD_POW_PORT_ID == 2) - #define RTE_SD_POW_PORT 0xC - #define RTE_SD_POW_PIN 9 - #define RTE_SD_POW_FUNC 7 -#elif (RTE_SD_POW_PORT_ID == 3) - #define RTE_SD_POW_PORT 0xD - #define RTE_SD_POW_PIN 1 - #define RTE_SD_POW_FUNC 5 -#else - #error "Invalid SD_POW Pin Configuration!" -#endif -#ifndef RTE_SD_POW_PIN_EN - #define RTE_SD_POW_PIN_EN 1 -#endif -// SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2 -// Configure Pin if exists -#define RTE_SD_RST_PORT_ID 0 -#if (RTE_SD_RST_PORT_ID == 0) - #define RTE_SD_RST_PIN_EN 0 -#elif (RTE_SD_RST_PORT_ID == 1) - #define RTE_SD_RST_PORT 1 - #define RTE_SD_RST_PIN 3 - #define RTE_SD_RST_FUNC 7 -#elif (RTE_SD_RST_PORT_ID == 2) - #define RTE_SD_RST_PORT 0xC - #define RTE_SD_RST_PIN 2 - #define RTE_SD_RST_FUNC 7 -#else - #error "Invalid SD_RST Pin Configuration!" -#endif -#ifndef RTE_SD_RST_PIN_EN - #define RTE_SD_RST_PIN_EN 1 -#endif -// SD/MMC Interface [Driver_MCI0] - -// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] -// Configuration settings for Driver_I2C0 in component ::Drivers:I2C -// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] -#define RTE_I2C0 0 - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>P2_4 <1=>PE_15 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) - #define RTE_I2C1_SCL_PORT 2 - #define RTE_I2C1_SCL_PIN 4 - #define RTE_I2C1_SCL_FUNC 1 -#elif (RTE_I2C1_SCL_PORT_ID == 1) - #define RTE_I2C1_SCL_PORT 0xE - #define RTE_I2C1_SCL_PIN 15 - #define RTE_I2C1_SCL_FUNC 2 -#else - #error "Invalid I2C1_SCL Pin Configuration!" -#endif -// I2C1_SDA Pin <0=>P2_3 <1=>PE_13 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) - #define RTE_I2C1_SDA_PORT 2 - #define RTE_I2C1_SDA_PIN 3 - #define RTE_I2C1_SDA_FUNC 1 -#elif (RTE_I2C1_SDA_PORT_ID == 1) - #define RTE_I2C1_SDA_PORT 0xE - #define RTE_I2C1_SDA_PIN 13 - #define RTE_I2C1_SDA_FUNC 2 -#else - #error "Invalid I2C1_SDA Pin Configuration!" -#endif -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -#define RTE_USART0 0 - -// Pin Configuration -// TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10 -// USART0 Serial Output pin -#define RTE_USART0_TX_ID 0 -#if (RTE_USART0_TX_ID == 0) - #define RTE_USART0_TX_PIN_EN 0 -#elif (RTE_USART0_TX_ID == 1) - #define RTE_USART0_TX_PORT 2 - #define RTE_USART0_TX_BIT 0 - #define RTE_USART0_TX_FUNC 1 -#elif (RTE_USART0_TX_ID == 2) - #define RTE_USART0_TX_PORT 6 - #define RTE_USART0_TX_BIT 4 - #define RTE_USART0_TX_FUNC 2 -#elif (RTE_USART0_TX_ID == 3) - #define RTE_USART0_TX_PORT 9 - #define RTE_USART0_TX_BIT 5 - #define RTE_USART0_TX_FUNC 7 -#elif (RTE_USART0_TX_ID == 4) - #define RTE_USART0_TX_PORT 0xF - #define RTE_USART0_TX_BIT 10 - #define RTE_USART0_TX_FUNC 1 -#else - #error "Invalid USART0_TX Pin Configuration!" -#endif -#ifndef RTE_USART0_TX_PIN_EN - #define RTE_USART0_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11 -// USART0 Serial Input pin -#define RTE_USART0_RX_ID 0 -#if (RTE_USART0_RX_ID == 0) - #define RTE_USART0_RX_PIN_EN 0 -#elif (RTE_USART0_RX_ID == 1) - #define RTE_USART0_RX_PORT 2 - #define RTE_USART0_RX_BIT 1 - #define RTE_USART0_RX_FUNC 1 -#elif (RTE_USART0_RX_ID == 2) - #define RTE_USART0_RX_PORT 6 - #define RTE_USART0_RX_BIT 5 - #define RTE_USART0_RX_FUNC 2 -#elif (RTE_USART0_RX_ID == 3) - #define RTE_USART0_RX_PORT 9 - #define RTE_USART0_RX_BIT 6 - #define RTE_USART0_RX_FUNC 7 -#elif (RTE_USART0_RX_ID == 4) - #define RTE_USART0_RX_PORT 0xF - #define RTE_USART0_RX_BIT 11 - #define RTE_USART0_RX_FUNC 1 -#else - #error "Invalid USART0_RX Pin Configuration!" -#endif -#ifndef RTE_USART0_RX_PIN_EN - #define RTE_USART0_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8 -// USART0 Serial Clock input/output synchronous mode -#define RTE_USART0_UCLK_ID 0 -#if (RTE_USART0_UCLK_ID == 0) - #define RTE_USART0_UCLK_PIN_EN 0 -#elif (RTE_USART0_UCLK_ID == 1) - #define RTE_USART0_UCLK_PORT 2 - #define RTE_USART0_UCLK_BIT 2 - #define RTE_USART0_UCLK_FUNC 1 -#elif (RTE_USART0_UCLK_ID == 2) - #define RTE_USART0_UCLK_PORT 6 - #define RTE_USART0_UCLK_BIT 1 - #define RTE_USART0_UCLK_FUNC 2 -#elif (RTE_USART0_UCLK_ID == 3) - #define RTE_USART0_UCLK_PORT 0xF - #define RTE_USART0_UCLK_BIT 8 - #define RTE_USART0_UCLK_FUNC 1 -#else - #error "Invalid USART0_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART0_UCLK_PIN_EN - #define RTE_USART0_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>1 (DMAMUXPER1) <1=>11 (DMAMUXPER11) -// -#define RTE_USART0_DMA_TX_EN 0 -#define RTE_USART0_DMA_TX_CH 0 -#define RTE_USART0_DMA_TX_PERI_ID 0 -#if (RTE_USART0_DMA_TX_PERI_ID == 0) - #define RTE_USART0_DMA_TX_PERI 1 - #define RTE_USART0_DMA_TX_PERI_SEL 1 -#elif (RTE_USART0_DMA_TX_PERI_ID == 1) - #define RTE_USART0_DMA_TX_PERI 11 - #define RTE_USART0_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>2 (DMAMUXPER2) <1=>12 (DMAMUXPER12) -// -#define RTE_USART0_DMA_RX_EN 0 -#define RTE_USART0_DMA_RX_CH 1 -#define RTE_USART0_DMA_RX_PERI_ID 0 -#if (RTE_USART0_DMA_RX_PERI_ID == 0) - #define RTE_USART0_DMA_RX_PERI 2 - #define RTE_USART0_DMA_RX_PERI_SEL 1 -#elif (RTE_USART0_DMA_RX_PERI_ID == 1) - #define RTE_USART0_DMA_RX_PERI 12 - #define RTE_USART0_DMA_RX_PERI_SEL 2 -#endif -// DMA -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] - -// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] -#define RTE_UART1 0 - -// Pin Configuration -// TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11 -// UART0 Serial Output pin -#define RTE_UART1_TX_ID 2 -#if (RTE_UART1_TX_ID == 0) - #define RTE_UART1_TX_PIN_EN 0 -#elif (RTE_UART1_TX_ID == 1) - #define RTE_UART1_TX_PORT 1 - #define RTE_UART1_TX_BIT 13 - #define RTE_UART1_TX_FUNC 1 -#elif (RTE_UART1_TX_ID == 2) - #define RTE_UART1_TX_PORT 3 - #define RTE_UART1_TX_BIT 4 - #define RTE_UART1_TX_FUNC 4 -#elif (RTE_UART1_TX_ID == 3) - #define RTE_UART1_TX_PORT 5 - #define RTE_UART1_TX_BIT 6 - #define RTE_UART1_TX_FUNC 4 -#elif (RTE_UART1_TX_ID == 4) - #define RTE_UART1_TX_PORT 0xC - #define RTE_UART1_TX_BIT 13 - #define RTE_UART1_TX_FUNC 2 -#elif (RTE_UART1_TX_ID == 5) - #define RTE_UART1_TX_PORT 0xE - #define RTE_UART1_TX_BIT 11 - #define RTE_UART1_TX_FUNC 2 -#else - #error "Invalid UART1_TX Pin Configuration!" -#endif -#ifndef RTE_UART1_TX_PIN_EN - #define RTE_UART1_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12 -// UART1 Serial Input pin -#define RTE_UART1_RX_ID 0 -#if (RTE_UART1_RX_ID == 0) - #define RTE_UART1_RX_PIN_EN 0 -#elif (RTE_UART1_RX_ID == 1) - #define RTE_UART1_RX_PORT 1 - #define RTE_UART1_RX_BIT 14 - #define RTE_UART1_RX_FUNC 1 -#elif (RTE_UART1_RX_ID == 2) - #define RTE_UART1_RX_PORT 3 - #define RTE_UART1_RX_BIT 5 - #define RTE_UART1_RX_FUNC 4 -#elif (RTE_UART1_RX_ID == 3) - #define RTE_UART1_RX_PORT 5 - #define RTE_UART1_RX_BIT 7 - #define RTE_UART1_RX_FUNC 4 -#elif (RTE_UART1_RX_ID == 4) - #define RTE_UART1_RX_PORT 0xC - #define RTE_UART1_RX_BIT 14 - #define RTE_UART1_RX_FUNC 2 -#elif (RTE_UART1_RX_ID == 5) - #define RTE_UART1_RX_PORT 0xE - #define RTE_UART1_RX_BIT 12 - #define RTE_UART1_RX_FUNC 2 -#else - #error "Invalid UART1_RX Pin Configuration!" -#endif -#ifndef RTE_UART1_RX_PIN_EN - #define RTE_UART1_RX_PIN_EN 1 -#endif - -// Modem Lines -// CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7 -#define RTE_UART1_CTS_ID 1 -#if (RTE_UART1_CTS_ID == 0) - #define RTE_UART1_CTS_PIN_EN 0 -#elif (RTE_UART1_CTS_ID == 1) - #define RTE_UART1_CTS_PORT 1 - #define RTE_UART1_CTS_BIT 11 - #define RTE_UART1_CTS_FUNC 1 -#elif (RTE_UART1_CTS_ID == 2) - #define RTE_UART1_CTS_PORT 5 - #define RTE_UART1_CTS_BIT 4 - #define RTE_UART1_CTS_FUNC 4 -#elif (RTE_UART1_CTS_ID == 3) - #define RTE_UART1_CTS_PORT 0xC - #define RTE_UART1_CTS_BIT 2 - #define RTE_UART1_CTS_FUNC 2 -#elif (RTE_UART1_CTS_ID == 4) - #define RTE_UART1_CTS_PORT 0xE - #define RTE_UART1_CTS_BIT 7 - #define RTE_UART1_CTS_FUNC 2 -#else - #error "Invalid UART1_CTS Pin Configuration!" -#endif -#ifndef RTE_UART1_CTS_PIN_EN - #define RTE_UART1_CTS_PIN_EN 1 -#endif -// RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5 -#define RTE_UART1_RTS_ID 1 -#if (RTE_UART1_RTS_ID == 0) - #define RTE_UART1_RTS_PIN_EN 0 -#elif (RTE_UART1_RTS_ID == 1) - #define RTE_UART1_RTS_PORT 1 - #define RTE_UART1_RTS_BIT 9 - #define RTE_UART1_RTS_FUNC 1 -#elif (RTE_UART1_RTS_ID == 2) - #define RTE_UART1_RTS_PORT 5 - #define RTE_UART1_RTS_BIT 2 - #define RTE_UART1_RTS_FUNC 4 -#elif (RTE_UART1_RTS_ID == 3) - #define RTE_UART1_RTS_PORT 0xC - #define RTE_UART1_RTS_BIT 3 - #define RTE_UART1_RTS_FUNC 2 -#elif (RTE_UART1_RTS_ID == 4) - #define RTE_UART1_RTS_PORT 0xE - #define RTE_UART1_RTS_BIT 5 - #define RTE_UART1_RTS_FUNC 2 -#else - #error "Invalid UART1_RTS Pin Configuration!" -#endif -#ifndef RTE_UART1_RTS_PIN_EN - #define RTE_UART1_RTS_PIN_EN 1 -#endif -// DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9 -#define RTE_UART1_DCD_ID 1 -#if (RTE_UART1_DCD_ID == 0) - #define RTE_UART1_DCD_PIN_EN 0 -#elif (RTE_UART1_DCD_ID == 1) - #define RTE_UART1_DCD_PORT 1 - #define RTE_UART1_DCD_BIT 12 - #define RTE_UART1_DCD_FUNC 1 -#elif (RTE_UART1_DCD_ID == 2) - #define RTE_UART1_DCD_PORT 5 - #define RTE_UART1_DCD_BIT 5 - #define RTE_UART1_DCD_FUNC 4 -#elif (RTE_UART1_DCD_ID == 3) - #define RTE_UART1_DCD_PORT 0xC - #define RTE_UART1_DCD_BIT 11 - #define RTE_UART1_DCD_FUNC 2 -#elif (RTE_UART1_DCD_ID == 4) - #define RTE_UART1_DCD_PORT 0xE - #define RTE_UART1_DCD_BIT 9 - #define RTE_UART1_DCD_FUNC 2 -#else - #error "Invalid UART1_DCD Pin Configuration!" -#endif -#ifndef RTE_UART1_DCD_PIN_EN - #define RTE_UART1_DCD_PIN_EN 1 -#endif -// DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8 -#define RTE_UART1_DSR_ID 1 -#if (RTE_UART1_DSR_ID == 0) - #define RTE_UART1_DSR_PIN_EN 0 -#elif (RTE_UART1_DSR_ID == 1) - #define RTE_UART1_DSR_PORT 1 - #define RTE_UART1_DSR_BIT 7 - #define RTE_UART1_DSR_FUNC 1 -#elif (RTE_UART1_DSR_ID == 2) - #define RTE_UART1_DSR_PORT 5 - #define RTE_UART1_DSR_BIT 0 - #define RTE_UART1_DSR_FUNC 4 -#elif (RTE_UART1_DSR_ID == 3) - #define RTE_UART1_DSR_PORT 0xC - #define RTE_UART1_DSR_BIT 10 - #define RTE_UART1_DSR_FUNC 2 -#elif (RTE_UART1_DSR_ID == 4) - #define RTE_UART1_DSR_PORT 0xE - #define RTE_UART1_DSR_BIT 8 - #define RTE_UART1_DSR_FUNC 2 -#else - #error "Invalid UART1_DSR Pin Configuration!" -#endif -#ifndef RTE_UART1_DSR_PIN_EN - #define RTE_UART1_DSR_PIN_EN 1 -#endif -// DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10 -#define RTE_UART1_DTR_ID 1 -#if (RTE_UART1_DTR_ID == 0) - #define RTE_UART1_DTR_PIN_EN 0 -#elif (RTE_UART1_DTR_ID == 1) - #define RTE_UART1_DTR_PORT 1 - #define RTE_UART1_DTR_BIT 8 - #define RTE_UART1_DTR_FUNC 1 -#elif (RTE_UART1_DTR_ID == 2) - #define RTE_UART1_DTR_PORT 5 - #define RTE_UART1_DTR_BIT 1 - #define RTE_UART1_DTR_FUNC 4 -#elif (RTE_UART1_DTR_ID == 3) - #define RTE_UART1_DTR_PORT 0xC - #define RTE_UART1_DTR_BIT 12 - #define RTE_UART1_DTR_FUNC 2 -#elif (RTE_UART1_DTR_ID == 4) - #define RTE_UART1_DTR_PORT 0xE - #define RTE_UART1_DTR_BIT 10 - #define RTE_UART1_DTR_FUNC 2 -#else - #error "Invalid UART1_DTR Pin Configuration!" -#endif -#ifndef RTE_UART1_DTR_PIN_EN - #define RTE_UART1_DTR_PIN_EN 1 -#endif -// RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6 -#define RTE_UART1_RI_ID 1 -#if (RTE_UART1_RI_ID == 0) - #define RTE_UART1_RI_PIN_EN 0 -#elif (RTE_UART1_RI_ID == 1) - #define RTE_UART1_RI_PORT 1 - #define RTE_UART1_RI_BIT 10 - #define RTE_UART1_RI_FUNC 1 -#elif (RTE_UART1_RI_ID == 2) - #define RTE_UART1_RI_PORT 5 - #define RTE_UART1_RI_BIT 3 - #define RTE_UART1_RI_FUNC 4 -#elif (RTE_UART1_RI_ID == 3) - #define RTE_UART1_RI_PORT 0xC - #define RTE_UART1_RI_BIT 1 - #define RTE_UART1_RI_FUNC 2 -#elif (RTE_UART1_RI_ID == 4) - #define RTE_UART1_RI_PORT 0xE - #define RTE_UART1_RI_BIT 6 - #define RTE_UART1_RI_FUNC 2 -#else - #error "Invalid UART1_RI Pin Configuration!" -#endif -#ifndef RTE_UART1_RI_PIN_EN - #define RTE_UART1_RI_PIN_EN 1 -#endif -// Modem Lines -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) -// -#define RTE_UART1_DMA_TX_EN 0 -#define RTE_UART1_DMA_TX_CH 0 -#define RTE_UART1_DMA_TX_PERI_ID 0 -#if (RTE_UART1_DMA_TX_PERI_ID == 0) - #define RTE_UART1_DMA_TX_PERI 3 - #define RTE_UART1_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) -// -#define RTE_UART1_DMA_RX_EN 0 -#define RTE_UART1_DMA_RX_CH 1 -#define RTE_UART1_DMA_RX_PERI_ID 0 -#if (RTE_UART1_DMA_RX_PERI_ID == 0) - #define RTE_UART1_DMA_RX_PERI 4 - #define RTE_UART1_DMA_RX_PERI_SEL 1 -#endif -// DMA -// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -#define RTE_USART2 0 - -// Pin Configuration -// TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1 -// USART2 Serial Output pin -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) - #define RTE_USART2_TX_PIN_EN 0 -#elif (RTE_USART2_TX_ID == 1) - #define RTE_USART2_TX_PORT 1 - #define RTE_USART2_TX_BIT 15 - #define RTE_USART2_TX_FUNC 1 -#elif (RTE_USART2_TX_ID == 2) - #define RTE_USART2_TX_PORT 2 - #define RTE_USART2_TX_BIT 10 - #define RTE_USART2_TX_FUNC 2 -#elif (RTE_USART2_TX_ID == 3) - #define RTE_USART2_TX_PORT 7 - #define RTE_USART2_TX_BIT 1 - #define RTE_USART2_TX_FUNC 6 -#elif (RTE_USART2_TX_ID == 4) - #define RTE_USART2_TX_PORT 0xA - #define RTE_USART2_TX_BIT 1 - #define RTE_USART2_TX_FUNC 3 -#else - #error "Invalid USART2_TX Pin Configuration!" -#endif -#ifndef RTE_USART2_TX_PIN_EN - #define RTE_USART2_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2 -// USART2 Serial Input pin -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) - #define RTE_USART2_RX_PIN_EN 0 -#elif (RTE_USART2_RX_ID == 1) - #define RTE_USART2_RX_PORT 1 - #define RTE_USART2_RX_BIT 16 - #define RTE_USART2_RX_FUNC 1 -#elif (RTE_USART2_RX_ID == 2) - #define RTE_USART2_RX_PORT 2 - #define RTE_USART2_RX_BIT 11 - #define RTE_USART2_RX_FUNC 2 -#elif (RTE_USART2_RX_ID == 3) - #define RTE_USART2_RX_PORT 7 - #define RTE_USART2_RX_BIT 2 - #define RTE_USART2_RX_FUNC 6 -#elif (RTE_USART2_RX_ID == 4) - #define RTE_USART2_RX_PORT 0xA - #define RTE_USART2_RX_BIT 2 - #define RTE_USART2_RX_FUNC 3 -#else - #error "Invalid USART2_RX Pin Configuration!" -#endif -#ifndef RTE_USART2_RX_PIN_EN - #define RTE_USART2_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12 -// USART2 Serial Clock input/output synchronous mode -#define RTE_USART2_UCLK_ID 0 -#if (RTE_USART2_UCLK_ID == 0) - #define RTE_USART2_UCLK_PIN_EN 0 -#elif (RTE_USART2_UCLK_ID == 1) - #define RTE_USART2_UCLK_PORT 1 - #define RTE_USART2_UCLK_BIT 17 - #define RTE_USART2_UCLK_FUNC 1 -#elif (RTE_USART2_UCLK_ID == 2) - #define RTE_USART2_UCLK_PORT 2 - #define RTE_USART2_UCLK_BIT 12 - #define RTE_USART2_UCLK_FUNC 7 -#else - #error "Invalid USART2_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART2_UCLK_PIN_EN - #define RTE_USART2_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>5 (DMAMUXPER5) -// -#define RTE_USART2_DMA_TX_EN 0 -#define RTE_USART2_DMA_TX_CH 0 -#define RTE_USART2_DMA_TX_PERI_ID 0 -#if (RTE_USART2_DMA_TX_PERI_ID == 0) - #define RTE_USART2_DMA_TX_PERI 5 - #define RTE_USART2_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>6 (DMAMUXPER6) -// -#define RTE_USART2_DMA_RX_EN 0 -#define RTE_USART2_DMA_RX_CH 1 -#define RTE_USART2_DMA_RX_PERI_ID 0 -#if (RTE_USART2_DMA_RX_PERI_ID == 0) - #define RTE_USART2_DMA_RX_PERI 6 - #define RTE_USART2_DMA_RX_PERI_SEL 1 -#endif -// DMA -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -#define RTE_USART3 0 - -// Pin Configuration -// TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2 -// USART3 Serial Output pin -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) - #define RTE_USART3_TX_PIN_EN 0 -#elif (RTE_USART3_TX_ID == 1) - #define RTE_USART3_TX_PORT 2 - #define RTE_USART3_TX_BIT 3 - #define RTE_USART3_TX_FUNC 2 -#elif (RTE_USART3_TX_ID == 2) - #define RTE_USART3_TX_PORT 4 - #define RTE_USART3_TX_BIT 1 - #define RTE_USART3_TX_FUNC 6 -#elif (RTE_USART3_TX_ID == 3) - #define RTE_USART3_TX_PORT 9 - #define RTE_USART3_TX_BIT 3 - #define RTE_USART3_TX_FUNC 7 -#elif (RTE_USART3_TX_ID == 4) - #define RTE_USART3_TX_PORT 0xF - #define RTE_USART3_TX_BIT 2 - #define RTE_USART3_TX_FUNC 1 -#else - #error "Invalid USART3_TX Pin Configuration!" -#endif -#ifndef RTE_USART3_TX_PIN_EN - #define RTE_USART3_TX_PIN_EN 1 -#endif -// RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3 -// USART3 Serial Input pin -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) - #define RTE_USART3_RX_PIN_EN 0 -#elif (RTE_USART3_RX_ID == 1) - #define RTE_USART3_RX_PORT 2 - #define RTE_USART3_RX_BIT 4 - #define RTE_USART3_RX_FUNC 2 -#elif (RTE_USART3_RX_ID == 2) - #define RTE_USART3_RX_PORT 4 - #define RTE_USART3_RX_BIT 2 - #define RTE_USART3_RX_FUNC 6 -#elif (RTE_USART3_RX_ID == 3) - #define RTE_USART3_RX_PORT 9 - #define RTE_USART3_RX_BIT 4 - #define RTE_USART3_RX_FUNC 7 -#elif (RTE_USART3_RX_ID == 4) - #define RTE_USART3_RX_PORT 0xF - #define RTE_USART3_RX_BIT 3 - #define RTE_USART3_RX_FUNC 1 -#else - #error "Invalid USART3_RX Pin Configuration!" -#endif -#ifndef RTE_USART3_RX_PIN_EN - #define RTE_USART3_RX_PIN_EN 1 -#endif -// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5 -// USART3 Serial Clock input/output synchronous mode -#define RTE_USART3_UCLK_ID 0 -#if (RTE_USART3_UCLK_ID == 0) - #define RTE_USART3_UCLK_PIN_EN 0 -#elif (RTE_USART3_UCLK_ID == 1) - #define RTE_USART3_UCLK_PORT 2 - #define RTE_USART3_UCLK_BIT 7 - #define RTE_USART3_UCLK_FUNC 2 -#elif (RTE_USART3_UCLK_ID == 2) - #define RTE_USART3_UCLK_PORT 4 - #define RTE_USART3_UCLK_BIT 0 - #define RTE_USART3_UCLK_FUNC 6 -#elif (RTE_USART3_UCLK_ID == 3) - #define RTE_USART3_UCLK_PORT 0xF - #define RTE_USART3_UCLK_BIT 5 - #define RTE_USART3_UCLK_FUNC 1 -#else - #error "Invalid USART3_UCLK Pin Configuration!" -#endif -#ifndef RTE_USART3_UCLK_PIN_EN - #define RTE_USART3_UCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>7 (DMAMUXPER7) <1=>14 (DMAMUXPER14) -// -#define RTE_USART3_DMA_TX_EN 0 -#define RTE_USART3_DMA_TX_CH 0 -#define RTE_USART3_DMA_TX_PERI_ID 0 -#if (RTE_USART3_DMA_TX_PERI_ID == 0) - #define RTE_USART3_DMA_TX_PERI 7 - #define RTE_USART3_DMA_TX_PERI_SEL 1 -#elif (RTE_USART3_DMA_TX_PERI_ID == 1) - #define RTE_USART3_DMA_TX_PERI 14 - #define RTE_USART3_DMA_TX_PERI_SEL 3 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>8 (DMAMUXPER8) <1=>13 (DMAMUXPER13) -// -#define RTE_USART3_DMA_RX_EN 0 -#define RTE_USART3_DMA_RX_CH 1 -#define RTE_USART3_DMA_RX_PERI_ID 0 -#if (RTE_USART3_DMA_RX_PERI_ID == 0) - #define RTE_USART3_DMA_RX_PERI 8 - #define RTE_USART3_DMA_RX_PERI_SEL 1 -#elif (RTE_USART3_DMA_RX_PERI_ID == 1) - #define RTE_USART3_DMA_RX_PERI 13 - #define RTE_USART3_DMA_RX_PERI_SEL 3 -#endif -// DMA -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] - -// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] -// Configuration settings for Driver_SPI0 in component ::Drivers:SPI -#define RTE_SSP0 1 - -// Pin Configuration -// SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1 -// Slave Select for SSP0 -#define RTE_SSP0_SSEL_PIN_SEL 5 -#if (RTE_SSP0_SSEL_PIN_SEL == 0) -#define RTE_SSP0_SSEL_PIN_EN 0 -#elif (RTE_SSP0_SSEL_PIN_SEL == 1) - #define RTE_SSP0_SSEL_PORT 1 - #define RTE_SSP0_SSEL_BIT 0 - #define RTE_SSP0_SSEL_FUNC 5 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 0 - #define RTE_SSP0_SSEL_GPIO_BIT 4 -#elif (RTE_SSP0_SSEL_PIN_SEL == 2) - #define RTE_SSP0_SSEL_PORT 3 - #define RTE_SSP0_SSEL_BIT 6 - #define RTE_SSP0_SSEL_FUNC 2 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 0 - #define RTE_SSP0_SSEL_GPIO_BIT 6 -#elif (RTE_SSP0_SSEL_PIN_SEL == 3) - #define RTE_SSP0_SSEL_PORT 3 - #define RTE_SSP0_SSEL_BIT 8 - #define RTE_SSP0_SSEL_FUNC 5 - #define RTE_SSP0_SSEL_GPIO_FUNC 4 - #define RTE_SSP0_SSEL_GPIO_PORT 5 - #define RTE_SSP0_SSEL_GPIO_BIT 11 -#elif (RTE_SSP0_SSEL_PIN_SEL == 4) - #define RTE_SSP0_SSEL_PORT 9 - #define RTE_SSP0_SSEL_BIT 0 - #define RTE_SSP0_SSEL_FUNC 7 - #define RTE_SSP0_SSEL_GPIO_FUNC 0 - #define RTE_SSP0_SSEL_GPIO_PORT 4 - #define RTE_SSP0_SSEL_GPIO_BIT 12 -#elif (RTE_SSP0_SSEL_PIN_SEL == 5) - #define RTE_SSP0_SSEL_PORT 0xF - #define RTE_SSP0_SSEL_BIT 1 - #define RTE_SSP0_SSEL_FUNC 2 - #define RTE_SSP0_SSEL_GPIO_FUNC 4 - #define RTE_SSP0_SSEL_GPIO_PORT 7 - #define RTE_SSP0_SSEL_GPIO_BIT 16 -#else - #error "Invalid SSP0 SSP0_SSEL Pin Configuration!" -#endif -#ifndef RTE_SSP0_SSEL_PIN_EN -#define RTE_SSP0_SSEL_PIN_EN 1 -#endif -// SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0 -// Serial clock for SSP0 -#define RTE_SSP0_SCK_PIN_SEL 2 -#if (RTE_SSP0_SCK_PIN_SEL == 0) - #define RTE_SSP0_SCK_PORT 3 - #define RTE_SSP0_SCK_BIT 0 - #define RTE_SSP0_SCK_FUNC 4 -#elif (RTE_SSP0_SCK_PIN_SEL == 1) - #define RTE_SSP0_SCK_PORT 3 - #define RTE_SSP0_SCK_BIT 3 - #define RTE_SSP0_SCK_FUNC 2 -#elif (RTE_SSP0_SCK_PIN_SEL == 2) - #define RTE_SSP0_SCK_PORT 0xF - #define RTE_SSP0_SCK_BIT 0 - #define RTE_SSP0_SCK_FUNC 0 -#else - #error "Invalid SSP0 SSP0_SCK Pin Configuration!" -#endif -// SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2 -// Master In Slave Out for SSP0 -#define RTE_SSP0_MISO_PIN_SEL 5 -#if (RTE_SSP0_MISO_PIN_SEL == 0) - #define RTE_SSP0_MISO_PIN_EN 0 -#elif (RTE_SSP0_MISO_PIN_SEL == 1) - #define RTE_SSP0_MISO_PORT 1 - #define RTE_SSP0_MISO_BIT 1 - #define RTE_SSP0_MISO_FUNC 5 -#elif (RTE_SSP0_MISO_PIN_SEL == 2) - #define RTE_SSP0_MISO_PORT 3 - #define RTE_SSP0_MISO_BIT 6 - #define RTE_SSP0_MISO_FUNC 5 -#elif (RTE_SSP0_MISO_PIN_SEL == 3) - #define RTE_SSP0_MISO_PORT 3 - #define RTE_SSP0_MISO_BIT 7 - #define RTE_SSP0_MISO_FUNC 2 -#elif (RTE_SSP0_MISO_PIN_SEL == 4) - #define RTE_SSP0_MISO_PORT 9 - #define RTE_SSP0_MISO_BIT 1 - #define RTE_SSP0_MISO_FUNC 7 -#elif (RTE_SSP0_MISO_PIN_SEL == 5) - #define RTE_SSP0_MISO_PORT 0xF - #define RTE_SSP0_MISO_BIT 2 - #define RTE_SSP0_MISO_FUNC 2 -#else - #error "Invalid SSP0 SSP0_MISO Pin Configuration!" -#endif -#ifndef RTE_SSP0_MISO_PIN_EN - #define RTE_SSP0_MISO_PIN_EN 1 -#endif -// SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3 -// Master Out Slave In for SSP0 -#define RTE_SSP0_MOSI_PIN_SEL 5 -#if (RTE_SSP0_MOSI_PIN_SEL == 0) - #define RTE_SSP0_MOSI_PIN_EN 0 -#elif (RTE_SSP0_MOSI_PIN_SEL == 1) - #define RTE_SSP0_MOSI_PORT 1 - #define RTE_SSP0_MOSI_BIT 2 - #define RTE_SSP0_MOSI_FUNC 5 -#elif (RTE_SSP0_MOSI_PIN_SEL == 2) - #define RTE_SSP0_MOSI_PORT 3 - #define RTE_SSP0_MOSI_BIT 7 - #define RTE_SSP0_MOSI_FUNC 5 -#elif (RTE_SSP0_MOSI_PIN_SEL == 3) - #define RTE_SSP0_MOSI_PORT 3 - #define RTE_SSP0_MOSI_BIT 8 - #define RTE_SSP0_MOSI_FUNC 2 -#elif (RTE_SSP0_MOSI_PIN_SEL == 4) - #define RTE_SSP0_MOSI_PORT 9 - #define RTE_SSP0_MOSI_BIT 2 - #define RTE_SSP0_MOSI_FUNC 7 -#elif (RTE_SSP0_MOSI_PIN_SEL == 5) - #define RTE_SSP0_MOSI_PORT 0xF - #define RTE_SSP0_MOSI_BIT 3 - #define RTE_SSP0_MOSI_FUNC 2 -#else - #error "Invalid SSP0 SSP0_MOSI Pin Configuration!" -#endif -#ifndef RTE_SSP0_MOSI_PIN_EN - #define RTE_SSP0_MOSI_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>10 (DMAMUXPER10) -// -#define RTE_SSP0_DMA_TX_EN 0 -#define RTE_SSP0_DMA_TX_CH 0 -#define RTE_SSP0_DMA_TX_PERI_ID 0 -#if (RTE_SSP0_DMA_TX_PERI_ID == 0) - #define RTE_SSP0_DMA_TX_PERI 10 - #define RTE_SSP0_DMA_TX_PERI_SEL 0 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>9 (DMAMUXPER9) -// -#define RTE_SSP0_DMA_RX_EN 0 -#define RTE_SSP0_DMA_RX_CH 1 -#define RTE_SSP0_DMA_RX_PERI_ID 0 -#if (RTE_SSP0_DMA_RX_PERI_ID == 0) - #define RTE_SSP0_DMA_RX_PERI 9 - #define RTE_SSP0_DMA_RX_PERI_SEL 0 -#endif -// DMA -// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] - -// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SSP1 0 - -// Pin Configuration -// SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5 -// Slave Select for SSP1 -#define RTE_SSP1_SSEL_PIN_SEL 1 -#if (RTE_SSP1_SSEL_PIN_SEL == 0) - #define RTE_SSP1_SSEL_PIN_EN 0 -#elif (RTE_SSP1_SSEL_PIN_SEL == 1) - #define RTE_SSP1_SSEL_PORT 1 - #define RTE_SSP1_SSEL_BIT 5 - #define RTE_SSP1_SSEL_FUNC 5 - #define RTE_SSP1_SSEL_GPIO_FUNC 0 - #define RTE_SSP1_SSEL_GPIO_PORT 1 - #define RTE_SSP1_SSEL_GPIO_BIT 8 -#elif (RTE_SSP1_SSEL_PIN_SEL == 2) - #define RTE_SSP1_SSEL_PORT 1 - #define RTE_SSP1_SSEL_BIT 20 - #define RTE_SSP1_SSEL_FUNC 1 - #define RTE_SSP1_SSEL_GPIO_FUNC 0 - #define RTE_SSP1_SSEL_GPIO_PORT 0 - #define RTE_SSP1_SSEL_GPIO_BIT 15 -#elif (RTE_SSP1_SSEL_PIN_SEL == 3) - #define RTE_SSP1_SSEL_PORT 0xF - #define RTE_SSP1_SSEL_BIT 5 - #define RTE_SSP1_SSEL_FUNC 2 - #define RTE_SSP1_SSEL_GPIO_FUNC 4 - #define RTE_SSP1_SSEL_GPIO_PORT 7 - #define RTE_SSP1_SSEL_GPIO_BIT 19 -#else - #error "Invalid SSP1 SSP1_SSEL Pin Configuration!" -#endif -#ifndef RTE_SSP1_SSEL_PIN_EN -#define RTE_SSP1_SSEL_PIN_EN 1 -#endif -// SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0 -// Serial clock for SSP1 -#define RTE_SSP1_SCK_PIN_SEL 0 -#if (RTE_SSP1_SCK_PIN_SEL == 0) - #define RTE_SSP1_SCK_PORT 1 - #define RTE_SSP1_SCK_BIT 19 - #define RTE_SSP1_SCK_FUNC 1 -#elif (RTE_SSP1_SCK_PIN_SEL == 1) - #define RTE_SSP1_SCK_PORT 0xF - #define RTE_SSP1_SCK_BIT 4 - #define RTE_SSP1_SCK_FUNC 0 -#elif (RTE_SSP1_SCK_PIN_SEL == 2) - #define RTE_SSP1_SCK_PORT 0x10 - #define RTE_SSP1_SCK_BIT 0 - #define RTE_SSP1_SCK_FUNC 6 -#else - #error "Invalid SSP1 SSP1_SCK Pin Configuration!" -#endif -// SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6 -// Master In Slave Out for SSP1 -#define RTE_SSP1_MISO_PIN_SEL 0 -#if (RTE_SSP1_MISO_PIN_SEL == 0) - #define RTE_SSP1_MISO_PIN_EN 0 -#elif (RTE_SSP1_MISO_PIN_SEL == 1) - #define RTE_SSP1_MISO_PORT 0 - #define RTE_SSP1_MISO_BIT 0 - #define RTE_SSP1_MISO_FUNC 1 -#elif (RTE_SSP1_MISO_PIN_SEL == 2) - #define RTE_SSP1_MISO_PORT 1 - #define RTE_SSP1_MISO_BIT 3 - #define RTE_SSP1_MISO_FUNC 5 -#elif (RTE_SSP1_MISO_PIN_SEL == 3) - #define RTE_SSP1_MISO_PORT 0xF - #define RTE_SSP1_MISO_BIT 6 - #define RTE_SSP1_MISO_FUNC 2 -#else - #error "Invalid SSP1 SSP1_MISO Pin Configuration!" -#endif -#ifndef RTE_SSP1_MISO_PIN_EN - #define RTE_SSP1_MISO_PIN_EN 1 -#endif -// SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7 -// Master Out Slave In for SSP1 -#define RTE_SSP1_MOSI_PIN_SEL 0 -#if (RTE_SSP1_MOSI_PIN_SEL == 0) - #define RTE_SSP1_MOSI_PIN_EN 0 -#elif (RTE_SSP1_MOSI_PIN_SEL == 1) - #define RTE_SSP1_MOSI_PORT 0 - #define RTE_SSP1_MOSI_BIT 1 - #define RTE_SSP1_MOSI_FUNC 1 -#elif (RTE_SSP1_MOSI_PIN_SEL == 2) - #define RTE_SSP1_MOSI_PORT 1 - #define RTE_SSP1_MOSI_BIT 4 - #define RTE_SSP1_MOSI_FUNC 5 -#elif (RTE_SSP1_MOSI_PIN_SEL == 3) - #define RTE_SSP1_MOSI_PORT 0xF - #define RTE_SSP1_MOSI_BIT 7 - #define RTE_SSP1_MOSI_FUNC 2 -#else - #error "Invalid SSP1 SSP1_MOSI Pin Configuration!" -#endif -#ifndef RTE_SSP1_MOSI_PIN_EN - #define RTE_SSP1_MOSI_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14) -// -#define RTE_SSP1_DMA_TX_EN 0 -#define RTE_SSP1_DMA_TX_CH 0 -#define RTE_SSP1_DMA_TX_PERI_ID 0 -#if (RTE_SSP1_DMA_TX_PERI_ID == 0) - #define RTE_SSP1_DMA_TX_PERI 3 - #define RTE_SSP1_DMA_TX_PERI_SEL 3 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 1) - #define RTE_SSP1_DMA_TX_PERI 5 - #define RTE_SSP1_DMA_TX_PERI_SEL 2 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 2) - #define RTE_SSP1_DMA_TX_PERI 12 - #define RTE_SSP1_DMA_TX_PERI_SEL 0 -#elif (RTE_SSP1_DMA_TX_PERI_ID == 3) - #define RTE_SSP1_DMA_TX_PERI 14 - #define RTE_SSP1_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13) -// -#define RTE_SSP1_DMA_RX_EN 0 -#define RTE_SSP1_DMA_RX_CH 1 -#define RTE_SSP1_DMA_RX_PERI_ID 0 -#if (RTE_SSP1_DMA_RX_PERI_ID == 0) - #define RTE_SSP1_DMA_RX_PERI 4 - #define RTE_SSP1_DMA_RX_PERI_SEL 3 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 1) - #define RTE_SSP1_DMA_RX_PERI 6 - #define RTE_SSP1_DMA_RX_PERI_SEL 2 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 2) - #define RTE_SSP1_DMA_RX_PERI 11 - #define RTE_SSP1_DMA_RX_PERI_SEL 0 -#elif (RTE_SSP1_DMA_RX_PERI_ID == 3) - #define RTE_SSP1_DMA_RX_PERI 13 - #define RTE_SSP1_DMA_RX_PERI_SEL 2 -#endif -// DMA -// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] - -// SPI (Serial Peripheral Interface) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI 0 - -// Pin Configuration -// SPI_SSEL <0=>Not used <1=>P3_8 -// Slave Select for SPI -#define RTE_SPI_SSEL_PIN_SEL 0 -#if (RTE_SPI_SSEL_PIN_SEL == 0) -#define RTE_SPI_SSEL_PIN_EN 0 -#elif (RTE_SPI_SSEL_PIN_SEL == 1) - #define RTE_SPI_SSEL_PORT 3 - #define RTE_SPI_SSEL_BIT 8 - #define RTE_SPI_SSEL_FUNC 1 - #define RTE_SPI_SSEL_GPIO_FUNC 4 - #define RTE_SPI_SSEL_GPIO_PORT 5 - #define RTE_SPI_SSEL_GPIO_BIT 11 -#else - #error "Invalid SPI SPI_SSEL Pin Configuration!" -#endif -#ifndef RTE_SPI_SSEL_PIN_EN -#define RTE_SPI_SSEL_PIN_EN 1 -#endif -// SPI_SCK <0=>P3_3 -// Serial clock for SPI -#define RTE_SPI_SCK_PIN_SEL 0 -#if (RTE_SPI_SCK_PIN_SEL == 0) - #define RTE_SPI_SCK_PORT 3 - #define RTE_SPI_SCK_BIT 3 - #define RTE_SPI_SCK_FUNC 1 -#else - #error "Invalid SPI SPI_SCK Pin Configuration!" -#endif -// SPI_MISO <0=>Not used <1=>P3_6 -// Master In Slave Out for SPI -#define RTE_SPI_MISO_PIN_SEL 0 -#if (RTE_SPI_MISO_PIN_SEL == 0) - #define RTE_SPI_MISO_PIN_EN 0 -#elif (RTE_SPI_MISO_PIN_SEL == 1) - #define RTE_SPI_MISO_PORT 3 - #define RTE_SPI_MISO_BIT 6 - #define RTE_SPI_MISO_FUNC 1 -#else - #error "Invalid SPI SPI_MISO Pin Configuration!" -#endif -#ifndef RTE_SPI_MISO_PIN_EN - #define RTE_SPI_MISO_PIN_EN 1 -#endif -// SPI_MOSI <0=>Not used <1=>P3_7 -// Master Out Slave In for SPI -#define RTE_SPI_MOSI_PIN_SEL 0 -#if (RTE_SPI_MOSI_PIN_SEL == 0) - #define RTE_SPI_MOSI_PIN_EN 0 -#elif (RTE_SPI_MOSI_PIN_SEL == 1) - #define RTE_SPI_MOSI_PORT 3 - #define RTE_SPI_MOSI_BIT 7 - #define RTE_SPI_MOSI_FUNC 1 -#else - #error "Invalid SPI SPI_MOSI Pin Configuration!" -#endif -#ifndef RTE_SPI_MOSI_PIN_EN - #define RTE_SPI_MOSI_PIN_EN 1 -#endif -// Pin Configuration -// SPI (Serial Peripheral Interface) [Driver_SPI2] - -// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] -// Configuration settings for Driver_SAI0 in component ::Drivers:SAI -#define RTE_I2S0 0 - -// Pin Configuration -// I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4 -// Receive clock for I2S0 -#define RTE_I2S0_RX_SCK_PIN_SEL 2 -#if (RTE_I2S0_RX_SCK_PIN_SEL == 0) -#define RTE_I2S0_RX_SCK_PIN_EN 0 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1) - #define RTE_I2S0_RX_SCK_PORT 3 - #define RTE_I2S0_RX_SCK_BIT 0 - #define RTE_I2S0_RX_SCK_FUNC 0 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2) - #define RTE_I2S0_RX_SCK_PORT 6 - #define RTE_I2S0_RX_SCK_BIT 0 - #define RTE_I2S0_RX_SCK_FUNC 4 -#elif (RTE_I2S0_RX_SCK_PIN_SEL == 3) - #define RTE_I2S0_RX_SCK_PORT 0xF - #define RTE_I2S0_RX_SCK_BIT 4 - #define RTE_I2S0_RX_SCK_FUNC 7 -#else - #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_SCK_PIN_EN -#define RTE_I2S0_RX_SCK_PIN_EN 1 -#endif -// I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1 -// Receive word select for I2S0 -#define RTE_I2S0_RX_WS_PIN_SEL 2 -#if (RTE_I2S0_RX_WS_PIN_SEL == 0) -#define RTE_I2S0_RX_WS_PIN_EN 0 -#elif (RTE_I2S0_RX_WS_PIN_SEL == 1) - #define RTE_I2S0_RX_WS_PORT 3 - #define RTE_I2S0_RX_WS_BIT 1 - #define RTE_I2S0_RX_WS_FUNC 1 -#elif (RTE_I2S0_RX_WS_PIN_SEL == 2) - #define RTE_I2S0_RX_WS_PORT 6 - #define RTE_I2S0_RX_WS_BIT 1 - #define RTE_I2S0_RX_WS_FUNC 3 -#else - #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_WS_PIN_EN -#define RTE_I2S0_RX_WS_PIN_EN 1 -#endif -// I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2 -// Receive master clock for I2S0 -#define RTE_I2S0_RX_SDA_PIN_SEL 2 -#if (RTE_I2S0_RX_SDA_PIN_SEL == 0) -#define RTE_I2S0_RX_SDA_PIN_EN 0 -#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1) - #define RTE_I2S0_RX_SDA_PORT 3 - #define RTE_I2S0_RX_SDA_BIT 2 - #define RTE_I2S0_RX_SDA_FUNC 1 -#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2) - #define RTE_I2S0_RX_SDA_PORT 6 - #define RTE_I2S0_RX_SDA_BIT 2 - #define RTE_I2S0_RX_SDA_FUNC 3 -#else - #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_SDA_PIN_EN -#define RTE_I2S0_RX_SDA_PIN_EN 1 -#endif -// I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0 -// Receive master clock for I2S0 -#define RTE_I2S0_RX_MCLK_PIN_SEL 0 -#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0) -#define RTE_I2S0_RX_MCLK_PIN_EN 0 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1) - #define RTE_I2S0_RX_MCLK_PORT 1 - #define RTE_I2S0_RX_MCLK_BIT 19 - #define RTE_I2S0_RX_MCLK_FUNC 6 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 2) - #define RTE_I2S0_RX_MCLK_PORT 3 - #define RTE_I2S0_RX_MCLK_BIT 0 - #define RTE_I2S0_RX_MCLK_FUNC 1 -#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 3) - #define RTE_I2S0_RX_MCLK_PORT 6 - #define RTE_I2S0_RX_MCLK_BIT 0 - #define RTE_I2S0_RX_MCLK_FUNC 1 -#else - #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S0_RX_MCLK_PIN_EN -#define RTE_I2S0_RX_MCLK_PIN_EN 1 -#endif -// I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7 -// Transmit clock for I2S0 -#define RTE_I2S0_TX_SCK_PIN_SEL 1 -#if (RTE_I2S0_TX_SCK_PIN_SEL == 0) -#define RTE_I2S0_TX_SCK_PIN_EN 0 -#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1) - #define RTE_I2S0_TX_SCK_PORT 3 - #define RTE_I2S0_TX_SCK_BIT 0 - #define RTE_I2S0_TX_SCK_FUNC 2 -#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2) - #define RTE_I2S0_TX_SCK_PORT 4 - #define RTE_I2S0_TX_SCK_BIT 7 - #define RTE_I2S0_TX_SCK_FUNC 7 -#else - #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_SCK_PIN_EN -#define RTE_I2S0_TX_SCK_PIN_EN 1 -#endif -// I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13 -// Transmit word select for I2S0 -#define RTE_I2S0_TX_WS_PIN_SEL 4 -#if (RTE_I2S0_TX_WS_PIN_SEL == 0) -#define RTE_I2S0_TX_WS_PIN_EN 0 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 1) - #define RTE_I2S0_TX_WS_PORT 0 - #define RTE_I2S0_TX_WS_BIT 0 - #define RTE_I2S0_TX_WS_FUNC 6 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 2) - #define RTE_I2S0_TX_WS_PORT 3 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 0 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 3) - #define RTE_I2S0_TX_WS_PORT 3 - #define RTE_I2S0_TX_WS_BIT 4 - #define RTE_I2S0_TX_WS_FUNC 5 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 4) - #define RTE_I2S0_TX_WS_PORT 7 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 2 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 5) - #define RTE_I2S0_TX_WS_PORT 9 - #define RTE_I2S0_TX_WS_BIT 1 - #define RTE_I2S0_TX_WS_FUNC 4 -#elif (RTE_I2S0_TX_WS_PIN_SEL == 6) - #define RTE_I2S0_TX_WS_PORT 0xC - #define RTE_I2S0_TX_WS_BIT 13 - #define RTE_I2S0_TX_WS_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_WS_PIN_EN -#define RTE_I2S0_TX_WS_PIN_EN 1 -#endif -// I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2 <5=>PC_12 -// Transmit data for I2S0 -#define RTE_I2S0_TX_SDA_PIN_SEL 3 -#if (RTE_I2S0_TX_SDA_PIN_SEL == 0) -#define RTE_I2S0_TX_SDA_PIN_EN 0 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1) - #define RTE_I2S0_TX_SDA_PORT 3 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 0 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2) - #define RTE_I2S0_TX_SDA_PORT 3 - #define RTE_I2S0_TX_SDA_BIT 5 - #define RTE_I2S0_TX_SDA_FUNC 5 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 3) - #define RTE_I2S0_TX_SDA_PORT 7 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 2 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 4) - #define RTE_I2S0_TX_SDA_PORT 9 - #define RTE_I2S0_TX_SDA_BIT 2 - #define RTE_I2S0_TX_SDA_FUNC 4 -#elif (RTE_I2S0_TX_SDA_PIN_SEL == 5) - #define RTE_I2S0_TX_SDA_PORT 0xC - #define RTE_I2S0_TX_SDA_BIT 12 - #define RTE_I2S0_TX_SDA_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_SDA_PIN_EN -#define RTE_I2S0_TX_SDA_PIN_EN 1 -#endif -// I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2 -// Transmit master clock for I2S0 -#define RTE_I2S0_TX_MCLK_PIN_SEL 2 -#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0) -#define RTE_I2S0_TX_MCLK_PIN_EN 0 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1) - #define RTE_I2S0_TX_MCLK_PORT 3 - #define RTE_I2S0_TX_MCLK_BIT 0 - #define RTE_I2S0_TX_MCLK_FUNC 3 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 2) - #define RTE_I2S0_TX_MCLK_PORT 3 - #define RTE_I2S0_TX_MCLK_BIT 3 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 3) - #define RTE_I2S0_TX_MCLK_PORT 0xf - #define RTE_I2S0_TX_MCLK_BIT 4 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 4) - #define RTE_I2S0_TX_MCLK_PORT 0x10 - #define RTE_I2S0_TX_MCLK_BIT 2 - #define RTE_I2S0_TX_MCLK_FUNC 6 -#else - #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S0_TX_MCLK_PIN_EN -#define RTE_I2S0_TX_MCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>9 (DMAMUXPER9) -// -#define RTE_I2S0_DMA_TX_EN 0 -#define RTE_I2S0_DMA_TX_CH 0 -#define RTE_I2S0_DMA_TX_PERI_ID 0 -#if (RTE_I2S0_DMA_TX_PERI_ID == 0) - #define RTE_I2S0_DMA_TX_PERI 9 - #define RTE_I2S0_DMA_TX_PERI_SEL 1 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>10 (DMAMUXPER10) -// -#define RTE_I2S0_DMA_RX_EN 0 -#define RTE_I2S0_DMA_RX_CH 1 -#define RTE_I2S0_DMA_RX_PERI_ID 0 -#if (RTE_I2S0_DMA_RX_PERI_ID == 0) - #define RTE_I2S0_DMA_RX_PERI 10 - #define RTE_I2S0_DMA_RX_PERI_SEL 1 -#endif -// DMA -// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] - -// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] -// Configuration settings for Driver_I2S1 in component ::Drivers:SAI -#define RTE_I2S1 0 - -// Pin Configuration -// I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3 -// Receive clock for I2S1 -#define RTE_I2S1_RX_SCK_PIN_SEL 0 -#if (RTE_I2S1_RX_SCK_PIN_SEL == 0) -#define RTE_I2S1_RX_SCK_PIN_EN 0 -#elif (RTE_I2S1_RX_SCK_PIN_SEL == 1) - #define RTE_I2S1_RX_SCK_PORT 0x10 - #define RTE_I2S1_RX_SCK_BIT 2 - #define RTE_I2S1_RX_SCK_FUNC 7 -#elif (RTE_I2S1_RX_SCK_PIN_SEL == 2) - #define RTE_I2S1_RX_SCK_PORT 0x10 - #define RTE_I2S1_RX_SCK_BIT 3 - #define RTE_I2S1_RX_SCK_FUNC 7 -#else - #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_SCK_PIN_EN -#define RTE_I2S1_RX_SCK_PIN_EN 1 -#endif -// I2S1_RX_WS <0=>Not used <1=>P3_5 -// Receive word select for I2S1 -#define RTE_I2S1_RX_WS_PIN_SEL 0 -#if (RTE_I2S1_RX_WS_PIN_SEL == 0) -#define RTE_I2S1_RX_WS_PIN_EN 0 -#elif (RTE_I2S1_RX_WS_PIN_SEL == 1) - #define RTE_I2S1_RX_WS_PORT 3 - #define RTE_I2S1_RX_WS_BIT 5 - #define RTE_I2S1_RX_WS_FUNC 6 -#else - #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_WS_PIN_EN -#define RTE_I2S1_RX_WS_PIN_EN 1 -#endif -// I2S1_RX_SDA <0=>Not used <1=>P3_4 -// Receive master clock for I2S1 -#define RTE_I2S1_RX_SDA_PIN_SEL 0 -#if (RTE_I2S1_RX_SDA_PIN_SEL == 0) -#define RTE_I2S1_RX_SDA_PIN_EN 0 -#elif (RTE_I2S1_RX_SDA_PIN_SEL == 1) - #define RTE_I2S1_RX_SDA_PORT 3 - #define RTE_I2S1_RX_SDA_BIT 4 - #define RTE_I2S1_RX_SDA_FUNC 6 -#else - #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_SDA_PIN_EN -#define RTE_I2S1_RX_SDA_PIN_EN 1 -#endif -// I2S1_RX_MCLK <0=>Not used <1=>PA_0 -// Receive master clock for I2S1 -#define RTE_I2S1_RX_MCLK_PIN_SEL 0 -#if (RTE_I2S1_RX_MCLK_PIN_SEL == 0) -#define RTE_I2S1_RX_MCLK_PIN_EN 0 -#elif (RTE_I2S1_RX_MCLK_PIN_SEL == 1) - #define RTE_I2S1_RX_MCLK_PORT 0x0A - #define RTE_I2S1_RX_MCLK_BIT 0 - #define RTE_I2S1_RX_MCLK_FUNC 5 -#else - #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S1_RX_MCLK_PIN_EN -#define RTE_I2S1_RX_MCLK_PIN_EN 1 -#endif -// I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7 -// Transmit clock for I2S1 -#define RTE_I2S1_TX_SCK_PIN_SEL 0 -#if (RTE_I2S1_TX_SCK_PIN_SEL == 0) -#define RTE_I2S1_TX_SCK_PIN_EN 0 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 1) - #define RTE_I2S1_TX_SCK_PORT 1 - #define RTE_I2S1_TX_SCK_BIT 19 - #define RTE_I2S1_TX_SCK_FUNC 7 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 2) - #define RTE_I2S1_TX_SCK_PORT 3 - #define RTE_I2S1_TX_SCK_BIT 3 - #define RTE_I2S1_TX_SCK_FUNC 7 -#elif (RTE_I2S1_TX_SCK_PIN_SEL == 3) - #define RTE_I2S1_TX_SCK_PORT 4 - #define RTE_I2S1_TX_SCK_BIT 7 - #define RTE_I2S1_TX_SCK_FUNC 6 -#else - #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_SCK_PIN_EN -#define RTE_I2S1_TX_SCK_PIN_EN 1 -#endif -// I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7 -// Transmit word select for I2S1 -#define RTE_I2S1_TX_WS_PIN_SEL 0 -#if (RTE_I2S1_TX_WS_PIN_SEL == 0) -#define RTE_I2S1_TX_WS_PIN_EN 0 -#elif (RTE_I2S1_TX_WS_PIN_SEL == 1) - #define RTE_I2S1_TX_WS_PORT 0 - #define RTE_I2S1_TX_WS_BIT 0 - #define RTE_I2S1_TX_WS_FUNC 7 -#elif (RTE_I2S1_TX_WS_PIN_SEL == 2) - #define RTE_I2S1_TX_WS_PORT 0x0F - #define RTE_I2S1_TX_WS_BIT 7 - #define RTE_I2S1_TX_WS_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_WS_PIN_EN -#define RTE_I2S1_TX_WS_PIN_EN 1 -#endif -// I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6 -// Transmit data for I2S -#define RTE_I2S1_TX_SDA_PIN_SEL 0 -#if (RTE_I2S1_TX_SDA_PIN_SEL == 0) -#define RTE_I2S1_TX_SDA_PIN_EN 0 -#elif (RTE_I2S1_TX_SDA_PIN_SEL == 1) - #define RTE_I2S1_TX_SDA_PORT 0 - #define RTE_I2S1_TX_SDA_BIT 1 - #define RTE_I2S1_TX_SDA_FUNC 7 -#elif (RTE_I2S1_TX_SDA_PIN_SEL == 2) - #define RTE_I2S1_TX_SDA_PORT 0x0F - #define RTE_I2S1_TX_SDA_BIT 6 - #define RTE_I2S1_TX_SDA_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_SDA_PIN_EN -#define RTE_I2S1_TX_SDA_PIN_EN 1 -#endif -// I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1 -// Transmit master clock for I2S1 -#define RTE_I2S1_TX_MCLK_PIN_SEL 0 -#if (RTE_I2S1_TX_MCLK_PIN_SEL == 0) -#define RTE_I2S1_TX_MCLK_PIN_EN 0 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 1) - #define RTE_I2S1_TX_MCLK_PORT 8 - #define RTE_I2S1_TX_MCLK_BIT 8 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 2) - #define RTE_I2S1_TX_MCLK_PORT 0x0F - #define RTE_I2S1_TX_MCLK_BIT 0 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 3) - #define RTE_I2S1_TX_MCLK_PORT 0x10 - #define RTE_I2S1_TX_MCLK_BIT 1 - #define RTE_I2S1_TX_MCLK_FUNC 7 -#else - #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!" -#endif -#ifndef RTE_I2S1_TX_MCLK_PIN_EN -#define RTE_I2S1_TX_MCLK_PIN_EN 1 -#endif -// Pin Configuration - -// DMA -// Tx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>3 (DMAMUXPER3) -// -#define RTE_I2S1_DMA_TX_EN 0 -#define RTE_I2S1_DMA_TX_CH 0 -#define RTE_I2S1_DMA_TX_PERI_ID 0 -#if (RTE_I2S1_DMA_TX_PERI_ID == 0) - #define RTE_I2S1_DMA_TX_PERI 3 - #define RTE_I2S1_DMA_TX_PERI_SEL 2 -#endif -// Rx -// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 -// Peripheral <0=>4 (DMAMUXPER4) -// -#define RTE_I2S1_DMA_RX_EN 0 -#define RTE_I2S1_DMA_RX_CH 1 -#define RTE_I2S1_DMA_RX_PERI_ID 0 -#if (RTE_I2S1_DMA_RX_PERI_ID == 0) - #define RTE_I2S1_DMA_RX_PERI 4 - #define RTE_I2S1_DMA_RX_PERI_SEL 2 -#endif -// DMA -// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] - -// CAN0 Controller [Driver_CAN0] -// Configuration settings for Driver_CAN0 in component ::Drivers:CAN -#define RTE_CAN_CAN0 0 - -// Pin Configuration -// CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2 -// CAN0 receiver input. -#define RTE_CAN0_RD_ID 0 -#if (RTE_CAN0_RD_ID == 0) - #define RTE_CAN0_RD_PIN_EN 0 -#elif (RTE_CAN0_RD_ID == 1) - #define RTE_CAN0_RD_PORT 3 - #define RTE_CAN0_RD_BIT 1 - #define RTE_CAN0_RD_FUNC 2 -#elif (RTE_CAN0_RD_ID == 2) - #define RTE_CAN0_RD_PORT 0xE - #define RTE_CAN0_RD_BIT 2 - #define RTE_CAN0_RD_FUNC 1 -#else - #error "Invalid RTE_CAN0_RD Pin Configuration!" -#endif -#ifndef RTE_CAN0_RD_PIN_EN - #define RTE_CAN0_RD_PIN_EN 1 -#endif -// CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3 -// CAN0 transmitter output. -#define RTE_CAN0_TD_ID 0 -#if (RTE_CAN0_TD_ID == 0) - #define RTE_CAN0_TD_PIN_EN 0 -#elif (RTE_CAN0_TD_ID == 1) - #define RTE_CAN0_TD_PORT 3 - #define RTE_CAN0_TD_BIT 2 - #define RTE_CAN0_TD_FUNC 2 -#elif (RTE_CAN0_TD_ID == 2) - #define RTE_CAN0_TD_PORT 0xE - #define RTE_CAN0_TD_BIT 3 - #define RTE_CAN0_TD_FUNC 1 -#else - #error "Invalid RTE_CAN0_TD Pin Configuration!" -#endif -#ifndef RTE_CAN0_TD_PIN_EN - #define RTE_CAN0_TD_PIN_EN 1 -#endif -// Pin Configuration -// CAN0 Controller [Driver_CAN0] - -// CAN1 Controller [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::Drivers:CAN -#define RTE_CAN_CAN1 0 - -// Pin Configuration -// CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1 -// CAN1 receiver input. -#define RTE_CAN1_RD_ID 0 -#if (RTE_CAN1_RD_ID == 0) - #define RTE_CAN1_RD_PIN_EN 0 -#elif (RTE_CAN1_RD_ID == 1) - #define RTE_CAN1_RD_PORT 1 - #define RTE_CAN1_RD_BIT 18 - #define RTE_CAN1_RD_FUNC 5 -#elif (RTE_CAN1_RD_ID == 2) - #define RTE_CAN1_RD_PORT 4 - #define RTE_CAN1_RD_BIT 9 - #define RTE_CAN1_RD_FUNC 6 -#elif (RTE_CAN1_RD_ID == 3) - #define RTE_CAN1_RD_PORT 0xE - #define RTE_CAN1_RD_BIT 1 - #define RTE_CAN1_RD_FUNC 5 -#else - #error "Invalid RTE_CAN1_RD Pin Configuration!" -#endif -#ifndef RTE_CAN1_RD_PIN_EN - #define RTE_CAN1_RD_PIN_EN 1 -#endif -// CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0 -// CAN1 transmitter output. -#define RTE_CAN1_TD_ID 0 -#if (RTE_CAN1_TD_ID == 0) - #define RTE_CAN1_TD_PIN_EN 0 -#elif (RTE_CAN1_TD_ID == 1) - #define RTE_CAN1_TD_PORT 1 - #define RTE_CAN1_TD_BIT 17 - #define RTE_CAN1_TD_FUNC 5 -#elif (RTE_CAN1_TD_ID == 2) - #define RTE_CAN1_TD_PORT 4 - #define RTE_CAN1_TD_BIT 8 - #define RTE_CAN1_TD_FUNC 6 -#elif (RTE_CAN1_TD_ID == 3) - #define RTE_CAN1_TD_PORT 0xE - #define RTE_CAN1_TD_BIT 0 - #define RTE_CAN1_TD_FUNC 5 -#else - #error "Invalid RTE_CAN1_TD Pin Configuration!" -#endif -#ifndef RTE_CAN1_TD_PIN_EN - #define RTE_CAN1_TD_PIN_EN 1 -#endif -// Pin Configuration -// CAN1 Controller [Driver_CAN1] - - -#endif /* __RTE_DEVICE_H */ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/startup_LPC43xx.s b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/startup_LPC43xx.s deleted file mode 100644 index 48a7c6e..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/startup_LPC43xx.s +++ /dev/null @@ -1,333 +0,0 @@ -;/**************************************************************************//** -; * @file LPC43xx.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * NXP LPC43xxDevice Series -; * @version V1.00 -; * @date 03. September 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; * <<< Use Configuration Wizard in Context Menu >>> -; ******************************************************************************/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001800 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -Sign_Value EQU 0x5A5A5A5A - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD Reset_Handler ; 1 Reset Handler - DCD NMI_Handler ; 2 NMI Handler - DCD HardFault_Handler ; 3 Hard Fault Handler - DCD MemManage_Handler ; 4 MPU Fault Handler - DCD BusFault_Handler ; 5 Bus Fault Handler - DCD UsageFault_Handler ; 6 Usage Fault Handler - DCD Sign_Value ; 7 Reserved - DCD 0 ; 8 Reserved - DCD 0 ; 9 Reserved - DCD 0 ; 10 Reserved - DCD SVC_Handler ; 11 SVCall Handler - DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD 0 ; 13 Reserved - DCD PendSV_Handler ; 14 PendSV Handler - DCD SysTick_Handler ; 15 SysTick Handler - - ; External LPC43xx/M4 Interrupts - DCD DAC_IRQHandler ; 0 DAC interrupt - DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication - DCD DMA_IRQHandler ; 2 DMA interrupt - DCD 0 ; 3 Reserved - DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt - DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt - DCD SDIO_IRQHandler ; 6 SD/MMC interrupt - DCD LCD_IRQHandler ; 7 LCD interrupt - DCD USB0_IRQHandler ; 8 OTG interrupt - DCD USB1_IRQHandler ; 9 USB1 interrupt - DCD SCT_IRQHandler ; 10 SCT combined interrupt - DCD RITIMER_IRQHandler ; 11 RI Timer interrupt - DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt - DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt - DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt - DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt - DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt - DCD ADC0_IRQHandler ; 17 ADC0 interrupt - DCD I2C0_IRQHandler ; 18 I2C0 interrupt - DCD I2C1_IRQHandler ; 19 I2C1 interrupt - DCD SPI_IRQHandler ; 20 SPI interrupt - DCD ADC1_IRQHandler ; 21 ADC1 interrupt - DCD SSP0_IRQHandler ; 22 SSP0 interrupt - DCD SSP1_IRQHandler ; 23 SSP1 interrupt - DCD USART0_IRQHandler ; 24 USART0 interrupt - DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt - DCD USART2_IRQHandler ; 26 USART2 interrupt - DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt - DCD I2S0_IRQHandler ; 28 I2S0 interrupt - DCD I2S1_IRQHandler ; 29 I2S1 interrupt - DCD SPIFI_IRQHandler ; 30 SPISI interrupt - DCD SGPIO_IRQHandler ; 31 SGPIO interrupt - DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0 - DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1 - DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2 - DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3 - DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4 - DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5 - DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6 - DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7 - DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0 - DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1 - DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt - DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt - DCD 0 ; 44 Reserved - DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt - DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt - DCD RTC_IRQHandler ; 47 RTC interrupt - DCD 0 ; 48 Reserved - DCD WWDT_IRQHandler ; 49 WWDT interrupt - DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt - DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt - DCD QEI_IRQHandler ; 52 QEI interrupt - - -;CRP address at offset 0x2FC relative to the BOOT Bank address - IF :LNOT::DEF:NO_CRP - SPACE (0x2FC - (. - __Vectors)) -; EXPORT CRP_Key -CRP_Key DCD 0xFFFFFFFF -; 0xFFFFFFFF => CRP Disabled -; 0x12345678 => CRP Level 1 -; 0x87654321 => CRP Level 2 -; 0x43218765 => CRP Level 3 (ARE YOU SURE?) -; 0x4E697370 => NO ISP (ARE YOU SURE?) - ENDIF - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT DAC_IRQHandler [WEAK] - EXPORT M0APP_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT FLASHEEPROM_IRQHandler [WEAK] - EXPORT ETHERNET_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT RITIMER_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT I2S1_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SGPIO_IRQHandler [WEAK] - EXPORT PIN_INT0_IRQHandler [WEAK] - EXPORT PIN_INT1_IRQHandler [WEAK] - EXPORT PIN_INT2_IRQHandler [WEAK] - EXPORT PIN_INT3_IRQHandler [WEAK] - EXPORT PIN_INT4_IRQHandler [WEAK] - EXPORT PIN_INT5_IRQHandler [WEAK] - EXPORT PIN_INT6_IRQHandler [WEAK] - EXPORT PIN_INT7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT EVENTROUTER_IRQHandler [WEAK] - EXPORT C_CAN1_IRQHandler [WEAK] - EXPORT ADCHS_IRQHandler [WEAK] - EXPORT ATIMER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT WWDT_IRQHandler [WEAK] - EXPORT M0SUB_IRQHandler [WEAK] - EXPORT C_CAN0_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - -DAC_IRQHandler -M0APP_IRQHandler -DMA_IRQHandler -FLASHEEPROM_IRQHandler -ETHERNET_IRQHandler -SDIO_IRQHandler -LCD_IRQHandler -USB0_IRQHandler -USB1_IRQHandler -SCT_IRQHandler -RITIMER_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -MCPWM_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI_IRQHandler -ADC1_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -USART0_IRQHandler -UART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -I2S0_IRQHandler -I2S1_IRQHandler -SPIFI_IRQHandler -SGPIO_IRQHandler -PIN_INT0_IRQHandler -PIN_INT1_IRQHandler -PIN_INT2_IRQHandler -PIN_INT3_IRQHandler -PIN_INT4_IRQHandler -PIN_INT5_IRQHandler -PIN_INT6_IRQHandler -PIN_INT7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -EVENTROUTER_IRQHandler -C_CAN1_IRQHandler -ADCHS_IRQHandler -ATIMER_IRQHandler -RTC_IRQHandler -WWDT_IRQHandler -M0SUB_IRQHandler -C_CAN0_IRQHandler -QEI_IRQHandler - - B . - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/system_LPC43xx.c b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/system_LPC43xx.c deleted file mode 100644 index 92d56ec..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Device/LPC4357_Cortex-M4/system_LPC43xx.c +++ /dev/null @@ -1,938 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013 - 2017 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 10. September 2018 - * $Revision: V1.0.3 - * - * Project: NXP LPC43xx System initialization - * -------------------------------------------------------------------------- */ - -#include "LPC43xx.h" - -/*---------------------------------------------------------------------------- - This file configures the clocks as follows: - ----------------------------------------------------------------------------- - Clock Unit | Output clock | Source clock | Note - ----------------------------------------------------------------------------- - PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz - ----------------------------------------------------------------------------- - PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz - ----------------------------------------------------------------------------- - CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK - ----------------------------------------------------------------------------- - IDIV A | 60 MHz | PLL1 | To the USB1 peripheral - ----------------------------------------------------------------------------- - IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz - ----------------------------------------------------------------------------- - IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz - ----------------------------------------------------------------------------- - IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz - ----------------------------------------------------------------------------- - IDIV E | 5.3 MHz | PLL1 | To the LCD controller - -----------------------------------------------------------------------------*/ - - -/*---------------------------------------------------------------------------- - Clock source selection definitions (do not change) - *----------------------------------------------------------------------------*/ -#define CLK_SRC_32KHZ 0x00 -#define CLK_SRC_IRC 0x01 -#define CLK_SRC_ENET_RX 0x02 -#define CLK_SRC_ENET_TX 0x03 -#define CLK_SRC_GP_CLKIN 0x04 -#define CLK_SRC_XTAL 0x06 -#define CLK_SRC_PLL0U 0x07 -#define CLK_SRC_PLL0A 0x08 -#define CLK_SRC_PLL1 0x09 -#define CLK_SRC_IDIVA 0x0C -#define CLK_SRC_IDIVB 0x0D -#define CLK_SRC_IDIVC 0x0E -#define CLK_SRC_IDIVD 0x0F -#define CLK_SRC_IDIVE 0x10 - - -/*---------------------------------------------------------------------------- - Define external input frequency values - *----------------------------------------------------------------------------*/ -#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */ -#define CLK_IRC 12000000UL /* Internal oscillator frequency */ -#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */ -#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */ -#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */ -#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */ - - -/*---------------------------------------------------------------------------- - Define clock sources - *----------------------------------------------------------------------------*/ -#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */ -#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */ -#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */ -#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */ -#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */ -#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */ -#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */ - - -/*---------------------------------------------------------------------------- - Configure integer divider values - *----------------------------------------------------------------------------*/ -#define IDIVA_IDIV 2 /* Divide input clock by 3 */ -#define IDIVB_IDIV 1 /* Divide input clock by 2 */ -#define IDIVC_IDIV 0 /* Divide input clock by 1 */ -#define IDIVD_IDIV 0 /* Divide input clock by 1 */ -#define IDIVE_IDIV 33 /* Divide input clock by 34 */ - - -/*---------------------------------------------------------------------------- - Define CPU clock input - *----------------------------------------------------------------------------*/ -#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */ - - -/*---------------------------------------------------------------------------- - Configure external memory controller options - *----------------------------------------------------------------------------*/ -#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */ -#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */ - - -/*---------------------------------------------------------------------------- - * Configure PLL1 - *---------------------------------------------------------------------------- - * Integer mode: - * - PLL1_DIRECT = 0 (Post divider enabled) - * - PLL1_FBSEL = 1 (Feedback divider runs from PLL output) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M - * FCCO = FCLKOUT * 2 * P - * - * Non-integer: - * - PLL1_DIRECT = 0 (Post divider enabled) - * - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M / (2 * P) - * FCCO = FCLKOUT * 2 * P - * - * Direct mode: - * - PLL1_DIRECT = 1 (Post divider disabled) - * - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock) - * - Output frequency: - * FCLKOUT = (FCLKIN / N) * M - * FCCO = FCLKOUT - * - *---------------------------------------------------------------------------- - * PLL1 requirements: - * | Frequency | Minimum | Maximum | Note | - * | FCLKIN | 1MHz | 25MHz | Clock source is external crystal | - * | FCLKIN | 1MHz | 50MHz | | - * | FCCO | 156MHz | 320MHz | | - * | FCLKOUT | 9.75MHz | 320MHz | | - *---------------------------------------------------------------------------- - * Configuration examples: - * | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS | - * | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 | - * | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 | - * | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 | - * | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 | - * | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 | - * | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 | - * | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 | - *---------------------------------------------------------------------------- - * Relations beetwen PLL dividers and definitions: - * N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL - *----------------------------------------------------------------------------*/ - -/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */ -#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */ -#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */ -#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */ - -#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ -#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */ -#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */ - /* 1: FCLKOUT is used as PLL feedback */ - -/*---------------------------------------------------------------------------- - * Configure Flash Accelerator - *---------------------------------------------------------------------------- - * Flash acces time: - * | CPU clock | FLASHTIM | - * | up to 21MHz | 0 | - * | up to 43MHz | 1 | - * | up to 64MHz | 2 | - * | up to 86MHz | 3 | - * | up to 107MHz | 4 | - * | up to 129MHz | 5 | - * | up to 150MHz | 6 | - * | up to 172MHz | 7 | - * | up to 193MHz | 8 | - * | up to 204MHz | 9 | - *----------------------------------------------------------------------------*/ -#define FLASHCFG_FLASHTIM 8 - - -/*---------------------------------------------------------------------------- - * Configure PLL0USB - *---------------------------------------------------------------------------- - * - * Normal operating mode without post-divider and without pre-divider - * - PLL0USB_DIRECTI = 1 - * - PLL0USB_DIRECTO = 1 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * 2 * M - * FCCO = FOUT - * - * Normal operating mode with post-divider and without pre-divider - * - PLL0USB_DIRECTI = 1 - * - PLL0USB_DIRECTO = 0 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * (M / P) - * FCCO = FOUT * 2 * P - * - * Normal operating mode without post-divider and with pre-divider - * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 1 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * 2 * M / N - * FCCO = FOUT - * - * Normal operating mode with post-divider and with pre-divider - * - PLL0USB_DIRECTI = 0 - * - PLL0USB_DIRECTO = 0 - * - PLL0USB_BYPASS = 0 - * - Output frequency: - * FOUT = FIN * M / (P * N) - * FCCO = FOUT * 2 * P - *---------------------------------------------------------------------------- - * PLL0 requirements: - * | Frequency | Minimum | Maximum | Note | - * | FCLKIN | 14kHz | 25MHz | Clock source is external crystal | - * | FCLKIN | 14kHz | 150MHz | | - * | FCCO | 275MHz | 550MHz | | - * | FCLKOUT | 4.3MHz | 550MHz | | - *---------------------------------------------------------------------------- - * Configuration examples: - * | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS | - * | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 | - * | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 | - *----------------------------------------------------------------------------*/ - -/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */ -#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */ -#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */ -#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */ - -#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */ -#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */ -#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ - - -/*---------------------------------------------------------------------------- - End of configuration - *----------------------------------------------------------------------------*/ - -/* PLL0 Setting Check */ -#if (PLL0USB_BYPASS == 0) - #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL) - #define PLL0USB_CLKIN CLK_XTAL - #else - #define PLL0USB_CLKIN CLK_IRC - #endif - - #if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M) - #define PLL0USB_FCCO (PLL0USB_FOUT) - #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P) - #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) - #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N) - #define PLL0USB_FCCO (PLL0USB_FOUT) - #else /* Mode 1d */ - #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N)) - #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) - #endif - - #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL) - #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)" - #endif - #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL) - #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)" - #endif -#endif - -/* PLL1 Setting Check */ -#if (PLL1_BYPASS == 0) - #if (PLL1_CLK_SEL == CLK_SRC_XTAL) - #define PLL1_CLKIN CLK_XTAL - #else - #define PLL1_CLKIN CLK_IRC - #endif - - #if (PLL1_DIRECT == 1) /* Direct Mode */ - #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #elif (PLL1_FBSEL == 1) /* Integer Mode */ - #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #else /* Noninteger Mode */ - #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) - #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL))) - #endif - #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL) - #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)" - #endif - #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL) - #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)" - #endif -#endif - - -/*---------------------------------------------------------------------------- - System Core Clock variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */ - - -/****************************************************************************** - * SetClock - ******************************************************************************/ -void SetClock (void) { - uint32_t x, i; - uint32_t selp, seli; - - - /* Set flash accelerator configuration for bank A and B to reset value */ - LPC_CREG->FLASHCFGA |= (0xF << 12); - LPC_CREG->FLASHCFGB |= (0xF << 12); - - /* Set flash wait states to maximum */ - LPC_EMC->STATICWAITRD0 = 0x1F; - - /* Switch BASE_M4_CLOCK to IRC */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (CLK_SRC_IRC << 24) ; /* Set clock source */ - - /* Configure input to crystal oscilator */ - LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */ - (0 << 1) | /* Operation with crystal connected */ - (0 << 2) ; /* Low-frequency mode */ - - /* Wait ~250us @ 12MHz */ - for (i = 1500; i; i--); - -#if (USE_SPIFI) -/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */ - LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ - (0 << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (CLK_SRC_IRC << 24) ; /* Clock source */ - - LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */ - (0 << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (CLK_SRC_IDIVA << 24) ; /* Clock source */ -#endif - -/*---------------------------------------------------------------------------- - PLL1 Setup - *----------------------------------------------------------------------------*/ - /* Power down PLL */ - LPC_CGU->PLL1_CTRL |= 1; - -#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1)) - /* To run at full speed, CPU must first run at an intermediate speed */ - LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ - (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ - (PLL1_FBSEL << 6) | /* PLL output used as feedback */ - (0 << 7) | /* Direct on/off */ - (PLL1_PSEL << 8) | /* PSEL */ - (0 << 11)| /* Autoblock Disabled */ - (PLL1_NSEL << 12)| /* NSEL */ - (PLL1_MSEL << 16)| /* MSEL */ - (PLL1_CLK_SEL << 24); /* Clock source */ - /* Wait for lock */ - while (!(LPC_CGU->PLL1_STAT & 1)); - - /* CPU base clock is in the mid frequency range before final clock set */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (0x09 << 24) ; /* Clock source: PLL1 */ - - /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */ - for (i = 1050; i; i--); /* Wait minimum 2100 cycles */ -#endif - /* Configure PLL1 */ - LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ - (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ - (PLL1_FBSEL << 6) | /* PLL output used as feedback */ - (PLL1_DIRECT << 7) | /* Direct on/off */ - (PLL1_PSEL << 8) | /* PSEL */ - (1 << 11)| /* Autoblock En */ - (PLL1_NSEL << 12)| /* NSEL */ - (PLL1_MSEL << 16)| /* MSEL */ - (PLL1_CLK_SEL << 24); /* Clock source */ - - /* Wait for lock */ - while (!(LPC_CGU->PLL1_STAT & 1)); - - /* Set CPU base clock source */ - LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ - (CPU_CLK_SEL << 24) ; /* Set clock source */ - - /* Set flash accelerator configuration for internal flash bank A and B */ - LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12); - LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12); - -/*---------------------------------------------------------------------------- - PLL0USB Setup - *----------------------------------------------------------------------------*/ - - /* Power down PLL0USB */ - LPC_CGU->PLL0USB_CTRL |= 1; - - /* M divider */ - x = 0x00004000; - switch (PLL0USB_M) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00018003; - break; - case 2: x = 0x00010003; - break; - default: - for (i = PLL0USB_M; i <= 0x8000; i++) { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - } - } - - if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1; - else selp = 31; - - if (PLL0USB_M > 16384) seli = 1; - else if (PLL0USB_M > 8192) seli = 2; - else if (PLL0USB_M > 2048) seli = 4; - else if (PLL0USB_M >= 501) seli = 8; - else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9)); - else seli = (PLL0USB_M & 0x3C) + 4; - LPC_CGU->PLL0USB_MDIV = (selp << 17) | - (seli << 22) | - (x << 0); - - /* N divider */ - x = 0x80; - switch (PLL0USB_N) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00000302; - break; - case 2: x = 0x00000202; - break; - default: - for (i = PLL0USB_N; i <= 0x0100; i++) { - x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - } - } - LPC_CGU->PLL0USB_NP_DIV = (x << 12); - - /* P divider */ - x = 0x10; - switch (PLL0USB_P) { - case 0: x = 0xFFFFFFFF; - break; - case 1: x = 0x00000062; - break; - case 2: x = 0x00000042; - break; - default: - for (i = PLL0USB_P; i <= 0x200; i++) { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F); - } - } - LPC_CGU->PLL0USB_NP_DIV |= x; - - LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */ - (1 << 11) | /* Autoblock En */ - (1 << 4 ) | /* PLL0USB clock en */ - (PLL0USB_DIRECTO << 3 ) | /* Direct output */ - (PLL0USB_DIRECTI << 2 ) | /* Direct input */ - (PLL0USB_BYPASS << 1 ) | /* PLL bypass */ - (0 << 0 ) ; /* PLL0USB Enabled */ - while (!(LPC_CGU->PLL0USB_STAT & 1)); - - -/*---------------------------------------------------------------------------- - Integer divider Setup - *----------------------------------------------------------------------------*/ - - /* Configure integer dividers */ - LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVA_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVA_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVB_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVB_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVC_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVC_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVD_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVD_CLK_SEL << 24) ; /* Clock source */ - - LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */ - (IDIVE_IDIV << 2) | /* IDIV */ - (1 << 11) | /* Autoblock En */ - (IDIVE_CLK_SEL << 24) ; /* Clock source */ -} - - -/*---------------------------------------------------------------------------- - Approximate delay function (must be used after SystemCoreClockUpdate() call) - *----------------------------------------------------------------------------*/ -#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000) - -static void WaitUs (uint32_t us) { - uint32_t cyc = us * CPU_NANOSEC(1000)/4; - while(cyc--); -} - - -/*---------------------------------------------------------------------------- - External Memory Controller Definitions - *----------------------------------------------------------------------------*/ -#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */ -/* Write Mode register macro */ -#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x)))) - -/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */ -#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4)) -#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000) - -#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */ -#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */ - -typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg); - -const uint16_t emcdivby2_opc[] = { - 0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */ - 0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */ - 0x6003, /* STR R3,[R0,#0] ; Store CREG6 */ - 0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */ - 0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */ - 0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */ - 0xD0FC, /* BEQ loop ; Jump if 0 */ - 0x4770, /* BX LR ; Exit */ - 0, -}; - -#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4) -#define emcdivby2_ram 0x10000000 - -/*---------------------------------------------------------------------------- - Initialize external memory controller - *----------------------------------------------------------------------------*/ - -void SystemInit_ExtMemCtl (void) { - uint32_t emcdivby2_buf[emcdivby2_szw]; - uint32_t div, n; - - /* Select and enable EMC branch clock */ - LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1; - while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1)); - - /* Set EMC clock output delay */ - if (SystemCoreClock < 80000000UL) { - LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */ - } - else { - LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */ - } - - /* Configure EMC port pins */ - LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */ - LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */ - LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */ - LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */ - LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */ - LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */ - LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */ - LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */ - LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */ - LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */ - LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */ - LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */ - LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */ - LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */ - LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */ - - LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */ - LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */ - LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */ - LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */ - LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */ - LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */ - LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */ - LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */ - LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */ - LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */ - LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */ - - LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */ - LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */ - LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */ - LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */ - LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */ - LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */ - LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */ - LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */ - - LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */ - LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */ - LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */ - LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */ - LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */ - LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */ - LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */ - LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */ - LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */ - LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */ - LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */ - LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */ - - LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */ - - LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */ - LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */ - LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */ - LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */ - LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */ - LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */ - LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */ - LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */ - LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */ - LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */ - LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */ - LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */ - LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */ - LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */ - LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */ - LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */ - LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */ - - LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */ - LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */ - LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */ - LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */ - LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */ - LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */ - LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */ - LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */ - LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */ - LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */ - LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */ - LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */ - LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */ - LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */ - LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */ - LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */ - - LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */ - LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */ - - div = 0; - if (SystemCoreClock > 120000000UL) { - /* Use EMC clock divider and EMC clock output delay */ - div = 1; - /* Following code must be executed in RAM to ensure stable operation */ - /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */ - /* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */ - /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */ - - /* This code configures EMC clock divider and is executed in RAM */ - for (n = 0; n < emcdivby2_szw; n++) { - emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n); - *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n); - } - __ISB(); - ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1); - for (n = 0; n < emcdivby2_szw; n++) { - *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n]; - } - } - - /* Configure EMC clock-out pins */ - LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */ - LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */ - LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */ - LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */ - - /* Static memory configuration (chip select 0) */ -#if (USE_EXT_STAT_MEM_CS0) - LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */ - (2 << 0) | /* Memory width 32-bit */ - (1 << 3); /* Async page mode enable */ - - LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */ - - LPC_EMC->STATICWAITPAGE0 = 2; - - /* Set Static Memory Read Delay for 90ns External NOR Flash */ - LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div); - LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */ -#endif - - /* Dynamic memory configuration (chip select 0) */ -#if (USE_EXT_DYN_MEM_CS0) - - /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */ - LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */ - (0 << 12) | /* AM[12] = 0 */ - (2 << 9) | /* AM[11:9] = 2 */ - (2 << 7) ; /* AM[8:7] = 2 */ - - LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/ - LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */ - - LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div); - LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div); - LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div); - LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div); - LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div); - LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div); - LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div); - LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div); - - WaitUs (100); - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */ - WaitUs (1); - LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ - WaitUs (1); - LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1; - WaitUs (10); - LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1; - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */ - - /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */ - WR_MODE(((3 << 4) | 2) << 12); - - WaitUs (10); - LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */ - LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */ -#endif -} - - -/*---------------------------------------------------------------------------- - Measure frequency using frequency monitor - *----------------------------------------------------------------------------*/ -uint32_t MeasureFreq (uint32_t clk_sel) { - uint32_t fcnt, rcnt, fout; - - /* Set register values */ - LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */ - LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */ - LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */ - while (LPC_CGU->FREQ_MON & (1 << 23)) { - fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; - rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF; - if (fcnt == 0 && rcnt == 0) { - return (0); /* No input clock present */ - } - } - fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; - fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */ - - return (fout); -} - - -/*---------------------------------------------------------------------------- - Get PLL1 (divider and multiplier) parameters - *----------------------------------------------------------------------------*/ -static __inline uint32_t GetPLL1Param (void) { - uint32_t ctrl; - uint32_t p; - uint32_t div, mul; - - ctrl = LPC_CGU->PLL1_CTRL; - div = ((ctrl >> 12) & 0x03) + 1; - mul = ((ctrl >> 16) & 0xFF) + 1; - p = 1 << ((ctrl >> 8) & 0x03); - - if (ctrl & (1 << 1)) { - /* Bypass = 1, PLL1 input clock sent to post-dividers */ - if (ctrl & (1 << 7)) { - div *= (2*p); - } - } - else { - /* Direct and integer mode */ - if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) { - /* Non-integer mode */ - div *= (2*p); - } - } - return ((div << 8) | (mul)); -} - - -/*---------------------------------------------------------------------------- - Get input clock source for specified clock generation block - *----------------------------------------------------------------------------*/ -int32_t GetClkSel (uint32_t clk_src) { - uint32_t reg; - int32_t clk_sel = -1; - - switch (clk_src) { - case CLK_SRC_IRC: - case CLK_SRC_ENET_RX: - case CLK_SRC_ENET_TX: - case CLK_SRC_GP_CLKIN: - return (clk_src); - - case CLK_SRC_32KHZ: - return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ); - case CLK_SRC_XTAL: - return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL); - - case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break; - case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break; - case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break; - - case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break; - case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break; - case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break; - case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break; - case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break; - - default: - return (clk_sel); - } - if (!(reg & 1)) { - clk_sel = (reg >> 24) & 0x1F; - } - return (clk_sel); -} - - -/*---------------------------------------------------------------------------- - Get clock frequency for specified clock source - *----------------------------------------------------------------------------*/ -uint32_t GetClockFreq (uint32_t clk_src) { - uint32_t tmp; - uint32_t mul = 1; - uint32_t div = 1; - uint32_t main_freq = 0; - int32_t clk_sel = clk_src; - - do { - switch (clk_sel) { - case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break; - case CLK_SRC_IRC: main_freq = CLK_IRC; break; - case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break; - case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break; - case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break; - case CLK_SRC_XTAL: main_freq = CLK_XTAL; break; - - case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break; - case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break; - case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break; - - case CLK_SRC_PLL0U: /* Not implemented */ break; - case CLK_SRC_PLL0A: /* Not implemented */ break; - - case CLK_SRC_PLL1: - tmp = GetPLL1Param (); - mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ - div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */ - break; - - default: - return (0); /* Clock not running or not supported */ - } - if (main_freq == 0) { - clk_sel = GetClkSel (clk_sel); - } - } - while (main_freq == 0); - - return ((main_freq * mul) / div); -} - - -/*---------------------------------------------------------------------------- - System Core Clock update - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) { - /* Check BASE_M4_CLK connection */ - uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F; - - /* Update core clock frequency */ - SystemCoreClock = GetClockFreq (base_src); -} - - -extern uint32_t __Vectors; /* see startup_LPC43xx.s */ - -/*---------------------------------------------------------------------------- - Initialize the system - *----------------------------------------------------------------------------*/ -void SystemInit (void) { - - #if (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ - #endif - - /* Stop CM0 core */ - LPC_RGU->RESET_CTRL1 = (1 << 24); - - /* Disable SysTick timer */ - SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); - - /* Set vector table pointer */ - SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL; - - /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */ - SetClock(); - - /* Update SystemCoreClock variable */ - SystemCoreClockUpdate(); - - /* Configure External Memory Controller */ - SystemInit_ExtMemCtl (); -} diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config.c b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config.c deleted file mode 100644 index 6946e8f..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config.c +++ /dev/null @@ -1,173 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V7.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Network System Settings -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "SockServer" - -// Memory Pool Size <1536-262144:4> -// This is the size of a memory pool in bytes. Buffers for -// network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_POOL_SIZE 16384 - -// Start System Services -// If enabled, the system will automatically start server services -// (HTTP, FTP, TFTP server, ...) when initializing the network system. -// Default: Enabled -#define NET_START_SERVICE 1 - -// OS Resource Settings -// These settings are used to optimize usage of OS resources. -// Core Thread Stack Size <512-65535:4> -// Default: 1024 bytes -#define NET_THREAD_STACK_SIZE 1024 - -// Core Thread Priority -#define NET_THREAD_PRIORITY osPriorityNormal - -// -// - -//------------- <<< end of configuration section >>> --------------------------- - -#include "RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_WiFi_0 -#include "Net_Config_WiFi_0.h" -#endif - -#ifdef RTE_Network_Interface_WiFi_1 -#include "Net_Config_WiFi_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP -#include "Net_Config_PPP.h" -#endif - -#ifdef RTE_Network_Interface_SLIP -#include "Net_Config_SLIP.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (NET_ERROR error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (NET_ERROR error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case NET_ERROR_MEM_ALLOC: - /* Out of memory */ - break; - - case NET_ERROR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case NET_ERROR_MEM_CORRUPT: - /* Memory Link pointer corrupted */ - /* More data written than the size of allocated memory block */ - break; - - case NET_ERROR_CONFIG: - /* Network configuration error detected */ - break; - - case NET_ERROR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case NET_ERROR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case NET_ERROR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_BSD.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index 8b7ba1b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,38 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration for BSD Sockets - * Rev.: V5.0.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 9 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 5 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_ETH_0.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index e554082..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,247 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration for ETH Interface - * Rev.: V7.2.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 0 - -// MAC Address -// Ethernet MAC Address in text representation -// Value FF-FF-FF-FF-FF-FF is not allowed, -// LSB of first byte must be 0 (an ethernet Multicast bit). -// Default: "1E-30-6C-A2-45-5E" -#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5A" - -// VLAN -// Enable or disable Virtual LAN -#define ETH0_VLAN_ENABLE 0 - -// VLAN Identifier <1-4093> -// A unique 12-bit numeric value -// Default: 1 -#define ETH0_VLAN_ID 1 -// - -// IPv4 -// Enable IPv4 Protocol for Network Interface -#define ETH0_IP4_ENABLE 1 - -// IP Address -// Static IPv4 Address in text representation -// Default: "192.168.0.100" -#define ETH0_IP4_ADDR "192.168.0.100" - -// Subnet mask -// Local Subnet mask in text representation -// Default: "255.255.255.0" -#define ETH0_IP4_MASK "255.255.255.0" - -// Default Gateway -// IP Address of Default Gateway in text representation -// Default: "192.168.0.254" -#define ETH0_IP4_GATEWAY "192.168.0.254" - -// Primary DNS Server -// IP Address of Primary DNS Server in text representation -// Default: "8.8.8.8" -#define ETH0_IP4_PRIMARY_DNS "8.8.8.8" - -// Secondary DNS Server -// IP Address of Secondary DNS Server in text representation -// Default: "8.8.4.4" -#define ETH0_IP4_SECONDARY_DNS "8.8.4.4" - -// IP Fragmentation -// This option enables fragmentation of outgoing IP datagrams, -// and reassembling the fragments of incoming IP datagrams. -// Default: enabled -#define ETH0_IP4_FRAG_ENABLE 1 - -// MTU size <576-1500> -// Maximum Transmission Unit in bytes -// Default: 1500 -#define ETH0_IP4_MTU 1500 -// - -// ARP Address Resolution -// ARP cache and node address resolver settings -// Cache Table size <5-100> -// Number of cached MAC/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by its name on local LAN using NBNS protocol. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -#define ETH0_DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// -// - -// IPv6 -// Enable IPv6 Protocol for Network Interface -#define ETH0_IP6_ENABLE 1 - -// IPv6 Address -// Static IPv6 Address in text representation -// Use unspecified address "::" when static -// IPv6 address is not used. -// Default: "fec0::2" -#define ETH0_IP6_ADDR "fec0::2" - -// Subnet prefix-length <1-128> -// Number of bits that define network address -// Default: 64 -#define ETH0_IP6_PREFIX_LEN 64 - -// Default Gateway -// Default Gateway IPv6 Address in text representation -// Default: "fec0::1" -#define ETH0_IP6_GATEWAY "fec0::1" - -// Primary DNS Server -// Primary DNS Server IPv6 Address in text representation -// Default: "2001:4860:4860::8888" -#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888" - -// Secondary DNS Server -// Secondary DNS Server IPv6 Address in text representation -// Default: "2001:4860:4860::8844" -#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844" - -// Neighbor Discovery -// Neighbor cache and node address resolver settings -// Cache Table size <5-100> -// Number of cached node addresses -// Default: 5 -#define ETH0_NDP_TAB_SIZE 5 - -// Cache Timeout in seconds <5-255> -// Timeout for cached node addresses -// Default: 150 -#define ETH0_NDP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of retries to resolve an IP address -// before NDP module gives up -// Default: 4 -#define ETH0_NDP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend Neighbor Solicitation -// Default: 2 -#define ETH0_NDP_RESEND_TOUT 2 -// - -// Dynamic Host Configuration -// When this option is enabled, local IPv6 address is -// automatically configured. -#define ETH0_DHCP6_ENABLE 1 - -// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode -// Stateless DHCPv6 Client uses router advertisements -// for IPv6 address autoconfiguration (SLAAC). -// Statefull DHCPv6 Client connects to DHCPv6 server for a -// leased IPv6 address and DNS server IPv6 addresses. -#define ETH0_DHCP6_MODE 1 - -// Vendor Class Option -// If enabled, Vendor Class option is added to DHCPv6 -// request message, identifying vendor type. -// Default: disabled -#define ETH0_DHCP6_VCLASS_ENABLE 0 - -// Enterprise ID -// Enterprise-number as registered with IANA. -// Default: 0 (Reserved) -#define ETH0_DHCP6_VCLASS_EID 0 - -// Vendor Class Data -// This string identifies vendor type. -// Default: "" -#define ETH0_DHCP6_VCLASS_DATA "" -// -// -// - -// OS Resource Settings -// These settings are used to optimize usage of OS resources. -// Interface Thread Stack Size <512-65535:4> -// Default: 512 bytes -#define ETH0_THREAD_STACK_SIZE 512 - -// Interface Thread Priority -#define ETH0_THREAD_PRIORITY osPriorityAboveNormal - -// -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_TCP.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index 5a5de02..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,69 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration for TCP Sockets - * Rev.: V7.1.1 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 6 -#define TCP_NUM_SOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-65535> -// If no TCP data frame has been exchanged during this time, -// the TCP connection is either closed or a keep-alive frame -// is sent to verify that the connection still exists. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1440> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1440 -#define TCP_MAX_SEG_SIZE 1440 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4320 -#define TCP_RECEIVE_WIN_SIZE 4320 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - -// Dynamic port start (default 49152) -#define TCP_DYN_PORT_START 49152 - -// Dynamic port end (default 65535) -#define TCP_DYN_PORT_END 65535 - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_Telnet_Server.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_Telnet_Server.h deleted file mode 100644 index 929d14b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_Telnet_Server.h +++ /dev/null @@ -1,58 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_Telnet_Server.h - * Purpose: Network Configuration for Telnet Server - * Rev.: V7.0.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Telnet Server -#define TELNET_SERVER_ENABLE 1 - -// Number of Connections <1-10> -// Number of simultaneously active Telnet Connections. -// Default: 1 -#define TELNET_SERVER_NUM_SESSISONS 1 - -// Port Number <1-65535> -// Listening port number. -// Default: 23 -#define TELNET_SERVER_PORT_NUM 23 - -// Idle Connection Timeout in seconds <0-3600> -// When timeout expires, the connection is closed. -// A value of 0 disables disconnection on timeout. -// Default: 120 -#define TELNET_SERVER_TOUT 120 - -// Disable Echo -// When disabled, the server will not echo characters it receives. -// Default: Not disabled -#define TELNET_SERVER_NO_ECHO 0 - -// Enable User Authentication -// When enabled, requires authentication of the user through -// the credentials to access the server. -#define TELNET_SERVER_AUTH_ENABLE 0 - -// Built-in Administrator Account -// Enable the built-in Administrator account on the server -// Default: Enabled -#define TELNET_SERVER_AUTH_ADMIN 1 - -// Administrator Username -// Default: "admin" -#define TELNET_SERVER_AUTH_USER "admin" - -// Administrator Password -// Default: "" -#define TELNET_SERVER_AUTH_PASS "" -// -// - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_UDP.h b/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index b6b2172..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,28 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration for UDP Sockets - * Rev.: V5.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 11 - -// - -// Dynamic port start (default 49152) -#define UDP_DYN_PORT_START 49152 - -// Dynamic port end (default 65535) -#define UDP_DYN_PORT_END 65535 - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/SockServer.uvguix b/Tools/SockServer/Embedded/MDK/Board/MCB4300/SockServer.uvguix deleted file mode 100644 index bba5016..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/SockServer.uvguix +++ /dev/null @@ -1,1878 +0,0 @@ - - - - -6.1 - -
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
- - - - LPC4357 Flash - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - LPC4357:Cortex-M4 - NXP - Keil.LPC4300_DFP.2.9.0 - http://www.keil.com/pack/ - IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC4357$Flash\LPC18xx43xx_512_BA.FLM) -FP1($$Device:LPC4357$Flash\LPC18xx43xx_512_BB.FLM)) - 0 - $$Device:LPC4357$Device\Include\LPC43xx.h - - - - - - - - - - $$Device:LPC4357$SVD\LPC43xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - SockServer - 1 - 0 - 0 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - $K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000) - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - -1 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 1 - 1 - 8 - 1 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x10000000 - 0x8000 - - - 1 - 0x1a000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x1a000000 - 0x80000 - - - 1 - 0x1b000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x10000000 - 0x8000 - - - 0 - 0x20000000 - 0x10000 - - - - - - 1 - 4 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - ..\..\Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x1A000000 - 0x10000000 - - - - - - - - - - - - - Source - - - main.c - 1 - .\main.c - - - - - SockServer Source - - - SockServer.c - 1 - ..\..\Source\SockServer.c - - - Telnet_Server_UIF.c - 1 - ..\..\Source\Telnet_Server_UIF.c - - - - - Documentation - - - Abstract.txt - 5 - .\Abstract.txt - - - - - ::Board Support - - - ::CMSIS - - - ::CMSIS Driver - - - ::Device - - - ::Network - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RTE\CMSIS\RTX_Config.c - - - - - - - - RTE\CMSIS\RTX_Config.h - - - - - - - - RTE\Device\LPC4357_Cortex-M4\RTE_Device.h - - - - - - - - RTE\Device\LPC4357_Cortex-M4\startup_LPC43xx.s - - - - - - - - RTE\Device\LPC4357_Cortex-M4\system_LPC43xx.c - - - - - - - - RTE\Network\Net_Config.c - - - - - - - - RTE\Network\Net_Config_BSD.h - - - - - - - - RTE\Network\Net_Config_ETH_0.h - - - - - - - - RTE\Network\Net_Config_TCP.h - - - - - - - - RTE\Network\Net_Config_Telnet_Server.h - - - - - - - - RTE\Network\Net_Config_UDP.h - - - - - - - - - - diff --git a/Tools/SockServer/Embedded/MDK/Board/MCB4300/main.c b/Tools/SockServer/Embedded/MDK/Board/MCB4300/main.c deleted file mode 100644 index 904846e..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCB4300/main.c +++ /dev/null @@ -1,92 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2019 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: main.c - * Purpose: Socket tester using BSD sockets - *----------------------------------------------------------------------------*/ - -#include -#include -#include "RTE_Components.h" -#include CMSIS_device_header -#include "cmsis_os2.h" -#include "rl_net.h" -#include "SockServer.h" - -#include "Board_LED.h" -#include "Board_GLCD.h" -#include "GLCD_Config.h" - -extern GLCD_FONT GLCD_Font_6x8; -extern GLCD_FONT GLCD_Font_16x24; - -static osThreadId_t display_id; - -// Functions -static void app_main (void *argument); -static void DisplayServer (void *argument); - -// IP address change notification -void netDHCP_Notify (uint32_t if_num, uint8_t opt, const uint8_t *val, uint32_t len) { - if (opt == NET_DHCP_OPTION_IP_ADDRESS) { - osThreadFlagsSet (display_id, 0x01); - } -} - - -// LCD display handler thread -static void DisplayServer (void *argument) { - uint8_t ip_addr[NET_ADDR_IP4_LEN]; - static char ip_ascii[16]; - static char buf[24]; - - GLCD_Initialize (); - GLCD_SetBackgroundColor (GLCD_COLOR_BLUE); - GLCD_SetForegroundColor (GLCD_COLOR_WHITE); - GLCD_ClearScreen (); - GLCD_SetFont (&GLCD_Font_16x24); - GLCD_DrawString (0, 1*24, " MW-Network "); - GLCD_DrawString (0, 2*24, " Socket test server "); - GLCD_DrawString (0, 4*24, " ECHO: port 7 "); - GLCD_DrawString (0, 5*24, " CHARGEN: port 19 "); - GLCD_DrawString (0, 6*24, " DISCARD: port 9 "); - - osDelay (100); - - while(1) { - osThreadFlagsWait (0x01, osFlagsWaitAll, osWaitForever); - netIF_GetOption (NET_IF_CLASS_ETH | 0, - netIF_OptionIP4_Address, ip_addr, sizeof(ip_addr)); - netIP_ntoa (NET_ADDR_IP4, ip_addr, ip_ascii, sizeof(ip_ascii)); - sprintf (buf, " IP=%-15s",ip_ascii); - GLCD_DrawString (0, 8*24, buf); - } -} - -// Application main thread -static void app_main (void *argument) { - - osDelay (500); - - LED_Initialize (); - netInitialize (); - LED_On (0); - - osThreadNew(DgramServer, NULL, NULL); - osThreadNew(StreamServer, NULL, NULL); - osThreadNew(TestAssistant, NULL, NULL); - display_id = osThreadNew (DisplayServer, NULL, NULL); - osThreadFlagsSet (display_id, 0x01); -} - -int main (void) { - - // System Initialization - SystemCoreClockUpdate(); - - osKernelInitialize(); - osThreadNew(app_main, NULL, NULL); - osKernelStart(); - for (;;) {} -} diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/Abstract.txt b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/Abstract.txt deleted file mode 100644 index 765450d..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/Abstract.txt +++ /dev/null @@ -1,67 +0,0 @@ -This is socket test server for the Keil MCBSTM32F400 evaluation board. -The example runs both CHARGEN and ECHO servers for TCP and UDP. -It is based on MW-Network and uses BSD sockets for the implementation. - -The SockServer is able to accept 7 connections simultaneously: -- 2 concurrent TCP echo sessions, -- 2 concurrent TCP chargen sessions, -- 1 concurrent TCP discard session, -- 1 socket UDP echo session, -- 1 socket UDP chargen session, -- 1 socket TCP test assistant session. - -Note: -- Use Network system viewer to see the assigned IP address of the server. -- Character ESC (0x1b) terminates TCP session. - - -ECHO -==== -Open a telnet session to your test platform at port 7. -For example: - -telnet 192.168.1.100 7 - -Then, enter in the telnet a few characters and you will see that the characters -are echoed back to you. In telnet you will see all duplicate characters: - -aabbccddee -kkwwaa -tteesstt - - -CHARGEN -======= - -Open a telnet session to your test platform at port 19. -For example: - -telnet 192.168.1.100 19 - -You will see a pattern similar to the following on streaming by on your -screen: - -ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01 -BCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012 -CDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123 -DEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01234 -EFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012345 -FGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456 -GHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./01234567 -HIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./012345678 -IJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789 -JKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789: -KLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:; -LMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:;< -MNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~!"#$%&'()*+,-./0123456789:;<= - - -DISCARD -======= - -Open a telnet session to your test platform at port 9. -For example: - -telnet 192.168.1.100 9 - -The service discards all received characters. diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.c b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.c deleted file mode 100644 index e487101..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.1.0 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration - * - * ----------------------------------------------------------------------------- - */ - -#include "cmsis_compiler.h" -#include "rtx_os.h" - -// OS Idle Thread -__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { - (void)argument; - - for (;;) {} -} - -// OS Error Callback function -__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { - (void)object_id; - - switch (code) { - case osRtxErrorStackUnderflow: - // Stack overflow detected for thread (thread_id=object_id) - break; - case osRtxErrorISRQueueOverflow: - // ISR Queue overflow detected when inserting object (object_id) - break; - case osRtxErrorTimerQueueOverflow: - // User Timer Callback Queue overflow detected for timer (timer_id=object_id) - break; - case osRtxErrorClibSpace: - // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM - break; - case osRtxErrorClibMutex: - // Standard C/C++ library mutex initialization failed - break; - default: - // Reserved - break; - } - for (;;) {} -//return 0U; -} diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.h deleted file mode 100644 index 89e82f9..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.h +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Copyright (c) 2013-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * $Revision: V5.5.0 - * - * Project: CMSIS-RTOS RTX - * Title: RTX Configuration definitions - * - * ----------------------------------------------------------------------------- - */ - -#ifndef RTX_CONFIG_H_ -#define RTX_CONFIG_H_ - -#ifdef _RTE_ -#include "RTE_Components.h" -#ifdef RTE_RTX_CONFIG_H -#include RTE_RTX_CONFIG_H -#endif -#endif - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Configuration -// ======================= - -// Global Dynamic Memory size [bytes] <0-1073741824:8> -// Defines the combined global dynamic memory size. -// Default: 4096 -#ifndef OS_DYNAMIC_MEM_SIZE -#define OS_DYNAMIC_MEM_SIZE 4096 -#endif - -// Kernel Tick Frequency [Hz] <1-1000000> -// Defines base time unit for delays and timeouts. -// Default: 1000 (1ms tick) -#ifndef OS_TICK_FREQ -#define OS_TICK_FREQ 1000 -#endif - -// Round-Robin Thread switching -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN_ENABLE -#define OS_ROBIN_ENABLE 1 -#endif - -// Round-Robin Timeout <1-1000> -// Defines how many ticks a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBIN_TIMEOUT -#define OS_ROBIN_TIMEOUT 5 -#endif - -// - -// ISR FIFO Queue -// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries -// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries -// RTOS Functions called from ISR store requests to this buffer. -// Default: 16 entries -#ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 16 -#endif - -// Object Memory usage counters -// Enables object memory usage counters (requires RTX source variant). -#ifndef OS_OBJ_MEM_USAGE -#define OS_OBJ_MEM_USAGE 0 -#endif - -// - -// Thread Configuration -// ======================= - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_THREAD_OBJ_MEM -#define OS_THREAD_OBJ_MEM 0 -#endif - -// Number of user Threads <1-1000> -// Defines maximum number of user threads that can be active at the same time. -// Applies to user threads with system provided memory for control blocks. -#ifndef OS_THREAD_NUM -#define OS_THREAD_NUM 1 -#endif - -// Number of user Threads with default Stack size <0-1000> -// Defines maximum number of user threads with default stack size. -// Applies to user threads with zero stack size specified. -#ifndef OS_THREAD_DEF_STACK_NUM -#define OS_THREAD_DEF_STACK_NUM 0 -#endif - -// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> -// Defines the combined stack size for user threads with user-provided stack size. -// Applies to user threads with user-provided stack size and system provided memory for stack. -// Default: 0 -#ifndef OS_THREAD_USER_STACK_SIZE -#define OS_THREAD_USER_STACK_SIZE 0 -#endif - -// - -// Default Thread Stack size [bytes] <96-1073741824:8> -// Defines stack size for threads with zero stack size specified. -// Default: 256 -#ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 400 -#endif - -// Idle Thread Stack size [bytes] <72-1073741824:8> -// Defines stack size for Idle thread. -// Default: 256 -#ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 256 -#endif - -// Idle Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_IDLE_THREAD_TZ_MOD_ID -#define OS_IDLE_THREAD_TZ_MOD_ID 0 -#endif - -// Stack overrun checking -// Enables stack overrun check at thread switch. -// Enabling this option increases slightly the execution time of a thread switch. -#ifndef OS_STACK_CHECK -#define OS_STACK_CHECK 1 -#endif - -// Stack usage watermark -// Initializes thread stack with watermark pattern for analyzing stack usage. -// Enabling this option increases significantly the execution time of thread creation. -#ifndef OS_STACK_WATERMARK -#define OS_STACK_WATERMARK 0 -#endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_PRIVILEGE_MODE -#define OS_PRIVILEGE_MODE 1 -#endif - -// - -// Timer Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_TIMER_OBJ_MEM -#define OS_TIMER_OBJ_MEM 0 -#endif - -// Number of Timer objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_TIMER_NUM -#define OS_TIMER_NUM 1 -#endif - -// - -// Timer Thread Priority -// <8=> Low -// <16=> Below Normal <24=> Normal <32=> Above Normal -// <40=> High -// <48=> Realtime -// Defines priority for timer thread -// Default: High -#ifndef OS_TIMER_THREAD_PRIO -#define OS_TIMER_THREAD_PRIO 40 -#endif - -// Timer Thread Stack size [bytes] <0-1073741824:8> -// Defines stack size for Timer thread. -// May be set to 0 when timers are not used. -// Default: 256 -#ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 256 -#endif - -// Timer Thread TrustZone Module Identifier -// Defines TrustZone Thread Context Management Identifier. -// Applies only to cores with TrustZone technology. -// Default: 0 (not used) -#ifndef OS_TIMER_THREAD_TZ_MOD_ID -#define OS_TIMER_THREAD_TZ_MOD_ID 0 -#endif - -// Timer Callback Queue entries <0-256> -// Number of concurrent active timer callback functions. -// May be set to 0 when timers are not used. -// Default: 4 -#ifndef OS_TIMER_CB_QUEUE -#define OS_TIMER_CB_QUEUE 4 -#endif - -// - -// Event Flags Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_EVFLAGS_OBJ_MEM -#define OS_EVFLAGS_OBJ_MEM 0 -#endif - -// Number of Event Flags objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_EVFLAGS_NUM -#define OS_EVFLAGS_NUM 1 -#endif - -// - -// - -// Mutex Configuration -// ====================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MUTEX_OBJ_MEM -#define OS_MUTEX_OBJ_MEM 0 -#endif - -// Number of Mutex objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MUTEX_NUM -#define OS_MUTEX_NUM 1 -#endif - -// - -// - -// Semaphore Configuration -// ========================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_SEMAPHORE_OBJ_MEM -#define OS_SEMAPHORE_OBJ_MEM 0 -#endif - -// Number of Semaphore objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_SEMAPHORE_NUM -#define OS_SEMAPHORE_NUM 1 -#endif - -// - -// - -// Memory Pool Configuration -// ============================ - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MEMPOOL_OBJ_MEM -#define OS_MEMPOOL_OBJ_MEM 0 -#endif - -// Number of Memory Pool objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MEMPOOL_NUM -#define OS_MEMPOOL_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MEMPOOL_DATA_SIZE -#define OS_MEMPOOL_DATA_SIZE 0 -#endif - -// - -// - -// Message Queue Configuration -// ============================== - -// Object specific Memory allocation -// Enables object specific memory allocation. -#ifndef OS_MSGQUEUE_OBJ_MEM -#define OS_MSGQUEUE_OBJ_MEM 0 -#endif - -// Number of Message Queue objects <1-1000> -// Defines maximum number of objects that can be active at the same time. -// Applies to objects with system provided memory for control blocks. -#ifndef OS_MSGQUEUE_NUM -#define OS_MSGQUEUE_NUM 1 -#endif - -// Data Storage Memory size [bytes] <0-1073741824:8> -// Defines the combined data storage memory size. -// Applies to objects with system provided memory for data storage. -// Default: 0 -#ifndef OS_MSGQUEUE_DATA_SIZE -#define OS_MSGQUEUE_DATA_SIZE 0 -#endif - -// - -// - -// Event Recorder Configuration -// =============================== - -// Global Initialization -// Initialize Event Recorder during 'osKernelInitialize'. -#ifndef OS_EVR_INIT -#define OS_EVR_INIT 0 -#endif - -// Start recording -// Start event recording after initialization. -#ifndef OS_EVR_START -#define OS_EVR_START 1 -#endif - -// Global Event Filter Setup -// Initial recording level applied to all components. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_LEVEL -#define OS_EVR_LEVEL 0x00U -#endif - -// RTOS Event Filter Setup -// Recording levels for RTX components. -// Only applicable if events for the respective component are generated. - -// Memory Management -// Recording level for Memory Management events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMORY_LEVEL -#define OS_EVR_MEMORY_LEVEL 0x01U -#endif - -// Kernel -// Recording level for Kernel events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_KERNEL_LEVEL -#define OS_EVR_KERNEL_LEVEL 0x01U -#endif - -// Thread -// Recording level for Thread events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THREAD_LEVEL -#define OS_EVR_THREAD_LEVEL 0x05U -#endif - -// Generic Wait -// Recording level for Generic Wait events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_WAIT_LEVEL -#define OS_EVR_WAIT_LEVEL 0x01U -#endif - -// Thread Flags -// Recording level for Thread Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_THFLAGS_LEVEL -#define OS_EVR_THFLAGS_LEVEL 0x01U -#endif - -// Event Flags -// Recording level for Event Flags events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_EVFLAGS_LEVEL -#define OS_EVR_EVFLAGS_LEVEL 0x01U -#endif - -// Timer -// Recording level for Timer events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_TIMER_LEVEL -#define OS_EVR_TIMER_LEVEL 0x01U -#endif - -// Mutex -// Recording level for Mutex events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MUTEX_LEVEL -#define OS_EVR_MUTEX_LEVEL 0x01U -#endif - -// Semaphore -// Recording level for Semaphore events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_SEMAPHORE_LEVEL -#define OS_EVR_SEMAPHORE_LEVEL 0x01U -#endif - -// Memory Pool -// Recording level for Memory Pool events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MEMPOOL_LEVEL -#define OS_EVR_MEMPOOL_LEVEL 0x01U -#endif - -// Message Queue -// Recording level for Message Queue events. -// Error events -// API function call events -// Operation events -// Detailed operation events -// -#ifndef OS_EVR_MSGQUEUE_LEVEL -#define OS_EVR_MSGQUEUE_LEVEL 0x01U -#endif - -// - -// - -// RTOS Event Generation -// Enables event generation for RTX components (requires RTX source variant). - -// Memory Management -// Enables Memory Management event generation. -#ifndef OS_EVR_MEMORY -#define OS_EVR_MEMORY 1 -#endif - -// Kernel -// Enables Kernel event generation. -#ifndef OS_EVR_KERNEL -#define OS_EVR_KERNEL 1 -#endif - -// Thread -// Enables Thread event generation. -#ifndef OS_EVR_THREAD -#define OS_EVR_THREAD 1 -#endif - -// Generic Wait -// Enables Generic Wait event generation. -#ifndef OS_EVR_WAIT -#define OS_EVR_WAIT 1 -#endif - -// Thread Flags -// Enables Thread Flags event generation. -#ifndef OS_EVR_THFLAGS -#define OS_EVR_THFLAGS 1 -#endif - -// Event Flags -// Enables Event Flags event generation. -#ifndef OS_EVR_EVFLAGS -#define OS_EVR_EVFLAGS 1 -#endif - -// Timer -// Enables Timer event generation. -#ifndef OS_EVR_TIMER -#define OS_EVR_TIMER 1 -#endif - -// Mutex -// Enables Mutex event generation. -#ifndef OS_EVR_MUTEX -#define OS_EVR_MUTEX 1 -#endif - -// Semaphore -// Enables Semaphore event generation. -#ifndef OS_EVR_SEMAPHORE -#define OS_EVR_SEMAPHORE 1 -#endif - -// Memory Pool -// Enables Memory Pool event generation. -#ifndef OS_EVR_MEMPOOL -#define OS_EVR_MEMPOOL 1 -#endif - -// Message Queue -// Enables Message Queue event generation. -#ifndef OS_EVR_MSGQUEUE -#define OS_EVR_MSGQUEUE 1 -#endif - -// - -// - -// Number of Threads which use standard C/C++ library libspace -// (when thread specific memory allocation is not used). -#if (OS_THREAD_OBJ_MEM == 0) -#define OS_THREAD_LIBSPACE_NUM 4 -#else -#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM -#endif - -//------------- <<< end of configuration section >>> --------------------------- - -#endif // RTX_CONFIG_H_ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/RTE_Device.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/RTE_Device.h deleted file mode 100644 index deabff0..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/RTE_Device.h +++ /dev/null @@ -1,2693 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2018 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 9. April 2018 - * $Revision: V2.4.5 - * - * Project: RTE Device Configuration for ST STM32F4xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT0 GPIOA -#define GPIO_PORT1 GPIOB -#define GPIO_PORT2 GPIOC -#define GPIO_PORT3 GPIOD -#define GPIO_PORT4 GPIOE -#define GPIO_PORT5 GPIOF -#define GPIO_PORT6 GPIOG -#define GPIO_PORT7 GPIOH -#define GPIO_PORT8 GPIOI -#define GPIO_PORT9 GPIOJ -#define GPIO_PORT10 GPIOK - -#define GPIO_PORT(num) GPIO_PORT##num - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>Not Used <1=>PA9 <2=>PA15 <3=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX 0 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 2) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 15 -#elif (RTE_USART1_TX_ID == 3) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PA10 <2=>PB3 <3=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX 0 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 2) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 3 -#elif (RTE_USART1_RX_ID == 3) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// USART1_CK Pin <0=>Not Used <1=>PA8 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK 0 -#elif (RTE_USART1_CK_ID == 1) -#define RTE_USART1_CK 1 -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// USART1_CTS Pin <0=>Not Used <1=>PA11 -#define RTE_USART1_CTS_ID 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS 0 -#elif (RTE_USART1_CTS_ID == 1) -#define RTE_USART1_CTS 1 -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif - -// USART1_RTS Pin <0=>Not Used <1=>PA12 -#define RTE_USART1_RTS_ID 0 -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS 0 -#elif (RTE_USART1_RTS_ID == 1) -#define RTE_USART1_RTS 1 -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 0 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 0 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>Not Used <1=>PA2 <2=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX 0 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX 1 -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 2) -#define RTE_USART2_TX 1 -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PA3 <2=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX 0 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX 1 -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 2) -#define RTE_USART2_RX 1 -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PA4 <2=>PD7 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK 0 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK 1 -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 2) -#define RTE_USART2_CK 1 -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PA0 <2=>PD3 -#define RTE_USART2_CTS_ID 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS 1 -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 2) -#define RTE_USART2_CTS 1 -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PA1 <2=>PD4 -#define RTE_USART2_RTS_ID 0 -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS 0 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS 1 -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 2) -#define RTE_USART2_RTS 1 -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <4=>4 <6=>6 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 0 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 0 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>Not Used <1=>PB10 <2=>PC10 <3=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX 0 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 3) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PB11 <2=>PC11 <3=>PD9 <4=>PC5 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX 0 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 3) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#elif (RTE_USART3_RX_ID == 4) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 5 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PB12 <2=>PC12 <3=>PD10 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK 0 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 3) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PB13 <2=>PD11 -#define RTE_USART3_CTS_ID 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS 0 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS 1 -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 2) -#define RTE_USART3_CTS 1 -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PB14 <2=>PD12 -#define RTE_USART3_RTS_ID 0 -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS 0 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS 1 -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 2) -#define RTE_USART3_RTS 1 -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <4=>4 -// Selects DMA Stream (only Stream 1 or 4 can be used) -// Channel <4=>4 <7=>7 -// Selects DMA Channel (only Channel 4 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 0 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 <4=>4 -// Selects DMA Stream (only Stream 3 or 4 can be used) -// Channel <4=>4 <7=>7 -// Selects DMA Channel (only Channel 4 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 0 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] -// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>Not Used <1=>PA0 <2=>PC10 <3=>PD10 <4=>PA12 <5=>PD1 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 2) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#elif (RTE_UART4_TX_ID == 3) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOD -#define RTE_UART4_TX_BIT 10 -#elif (RTE_UART4_TX_ID == 4) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 12 -#elif (RTE_UART4_TX_ID == 5) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOD -#define RTE_UART4_TX_BIT 1 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>Not Used <1=>PA1 <2=>PC11 <3=>PA11 <4=>PD0 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX 0 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 2) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#elif (RTE_UART4_RX_ID == 3) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 11 -#elif (RTE_UART4_RX_ID == 4) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOD -#define RTE_UART4_RX_BIT 0 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 0 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 0 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] -// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>Not Used <1=>PC12 <2=>PB6 <3=>PB9 <4=>PB13 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX 0 -#elif (RTE_UART5_TX_ID == 1) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#elif (RTE_UART5_TX_ID == 2) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 6 -#elif (RTE_UART5_TX_ID == 3) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 9 -#elif (RTE_UART5_TX_ID == 4) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 13 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>Not Used <1=>PD2 <2=>PB5 <3=>PB8 <4=>PB12 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX 0 -#elif (RTE_UART5_RX_ID == 1) -#define RTE_UART5_RX 1 -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#elif (RTE_UART5_TX_ID == 2) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 5 -#elif (RTE_UART5_TX_ID == 3) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 8 -#elif (RTE_UART5_TX_ID == 4) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 0 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 <8=>8 -// Selects DMA Channel (only Channel 4 or 8 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 0 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_USART6] -// Configuration settings for Driver_USART6 in component ::CMSIS Driver:USART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>Not Used <1=>PA11 <2=>PC6 <3=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX 0 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOA -#define RTE_USART6_TX_BIT 11 -#elif (RTE_USART6_TX_ID == 2) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 3) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>Not Used <1=>PA12 <2=>PC7 <3=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX 0 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOA -#define RTE_USART6_RX_BIT 12 -#elif (RTE_USART6_RX_ID == 2) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 3) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// USART6_CK Pin <0=>Not Used <1=>PC8 <2=>PG7 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK 0 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK 1 -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 2) -#define RTE_USART6_CK 1 -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// USART6_CTS Pin <0=>Not Used <1=>PG13 <2=>PG15 -#define RTE_USART6_CTS_ID 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS 0 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS 1 -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 2) -#define RTE_USART6_CTS 1 -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif - -// USART6_RTS Pin <0=>Not Used <1=>PG8 <2=>PG12 -#define RTE_USART6_RTS_ID 0 -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS 0 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS 1 -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 2) -#define RTE_USART6_RTS 1 -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 0 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 0 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - -// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] -// Configuration settings for Driver_USART7 in component ::CMSIS Driver:USART -#define RTE_UART7 0 - -// UART7_TX Pin <0=>Not Used <1=>PF7 <2=>PE8 <3=>PA15 <4=>PB4 -#define RTE_UART7_TX_ID 0 -#if (RTE_UART7_TX_ID == 0) -#define RTE_UART7_TX 0 -#elif (RTE_UART7_TX_ID == 1) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOF -#define RTE_UART7_TX_BIT 7 -#elif (RTE_UART7_TX_ID == 2) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOE -#define RTE_UART7_TX_BIT 8 -#elif (RTE_UART7_TX_ID == 3) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOA -#define RTE_UART7_TX_BIT 15 -#elif (RTE_UART7_TX_ID == 4) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOB -#define RTE_UART7_TX_BIT 4 -#else -#error "Invalid UART7_TX Pin Configuration!" -#endif - -// UART7_RX Pin <0=>Not Used <1=>PF6 <2=>PE7 <3=>PA8 <4=>PB3 -#define RTE_UART7_RX_ID 0 -#if (RTE_UART7_RX_ID == 0) -#define RTE_UART7_RX 0 -#elif (RTE_UART7_RX_ID == 1) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOF -#define RTE_UART7_RX_BIT 6 -#elif (RTE_UART7_RX_ID == 2) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOE -#define RTE_UART7_RX_BIT 7 -#elif (RTE_UART7_RX_ID == 3) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOA -#define RTE_UART7_RX_BIT 8 -#elif (RTE_UART7_RX_ID == 4) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOB -#define RTE_UART7_RX_BIT 3 -#else -#error "Invalid UART7_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART7_RX_DMA 0 -#define RTE_UART7_RX_DMA_NUMBER 1 -#define RTE_UART7_RX_DMA_STREAM 3 -#define RTE_UART7_RX_DMA_CHANNEL 5 -#define RTE_UART7_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART7_TX_DMA 0 -#define RTE_UART7_TX_DMA_NUMBER 1 -#define RTE_UART7_TX_DMA_STREAM 1 -#define RTE_UART7_TX_DMA_CHANNEL 5 -#define RTE_UART7_TX_DMA_PRIORITY 0 - -// - -// UART8 (Universal asynchronous receiver transmitter) [Driver_USART8] -// Configuration settings for Driver_USART8 in component ::CMSIS Driver:USART -#define RTE_UART8 0 - -// UART8_TX Pin <0=>Not Used <1=>PE1 <2=>PF9 -#define RTE_UART8_TX_ID 0 -#if (RTE_UART8_TX_ID == 0) -#define RTE_UART8_TX 0 -#elif (RTE_UART8_TX_ID == 1) -#define RTE_UART8_TX 1 -#define RTE_UART8_TX_PORT GPIOE -#define RTE_UART8_TX_BIT 1 -#elif (RTE_UART8_TX_ID == 2) -#define RTE_UART8_TX 1 -#define RTE_UART8_TX_PORT GPIOF -#define RTE_UART8_TX_BIT 9 -#else -#error "Invalid UART8_TX Pin Configuration!" -#endif - -// UART8_RX Pin <0=>Not Used <1=>PE0 <2=>PF8 -#define RTE_UART8_RX_ID 0 -#if (RTE_UART8_RX_ID == 0) -#define RTE_UART8_RX 0 -#elif (RTE_UART8_RX_ID == 1) -#define RTE_UART8_RX 1 -#define RTE_UART8_RX_PORT GPIOE -#define RTE_UART8_RX_BIT 0 -#elif (RTE_UART8_RX_ID == 2) -#define RTE_UART8_RX 1 -#define RTE_UART8_RX_PORT GPIOF -#define RTE_UART8_RX_BIT 8 -#else -#error "Invalid UART8_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART8_RX_DMA 0 -#define RTE_UART8_RX_DMA_NUMBER 1 -#define RTE_UART8_RX_DMA_STREAM 6 -#define RTE_UART8_RX_DMA_CHANNEL 5 -#define RTE_UART8_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART8_TX_DMA 0 -#define RTE_UART8_TX_DMA_NUMBER 1 -#define RTE_UART8_TX_DMA_STREAM 0 -#define RTE_UART8_TX_DMA_CHANNEL 5 -#define RTE_UART8_TX_DMA_PRIORITY 0 - -// - -// UART9 (Universal asynchronous receiver transmitter) [Driver_USART9] -// Configuration settings for Driver_USART9 in component ::CMSIS Driver:USART -#define RTE_UART9 0 - -// UART9_TX Pin <0=>Not Used <1=>PD15 <2=>PG1 -#define RTE_UART9_TX_ID 0 -#if (RTE_UART9_TX_ID == 0) -#define RTE_UART9_TX 0 -#elif (RTE_UART9_TX_ID == 1) -#define RTE_UART9_TX 1 -#define RTE_UART9_TX_PORT GPIOD -#define RTE_UART9_TX_BIT 15 -#elif (RTE_UART9_TX_ID == 2) -#define RTE_UART9_TX 1 -#define RTE_UART9_TX_PORT GPIOG -#define RTE_UART9_TX_BIT 1 -#else -#error "Invalid UART9_TX Pin Configuration!" -#endif - -// UART9_RX Pin <0=>Not Used <1=>PD14 <2=>PG0 -#define RTE_UART9_RX_ID 0 -#if (RTE_UART9_RX_ID == 0) -#define RTE_UART9_RX 0 -#elif (RTE_UART9_RX_ID == 1) -#define RTE_UART9_RX 1 -#define RTE_UART9_RX_PORT GPIOD -#define RTE_UART9_RX_BIT 14 -#elif (RTE_UART9_RX_ID == 2) -#define RTE_UART9_RX 1 -#define RTE_UART9_RX_PORT GPIOG -#define RTE_UART9_RX_BIT 0 -#else -#error "Invalid UART9_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART9_RX_DMA 0 -#define RTE_UART9_RX_DMA_NUMBER 1 -#define RTE_UART9_RX_DMA_STREAM 6 -#define RTE_UART9_RX_DMA_CHANNEL 5 -#define RTE_UART9_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART9_TX_DMA 0 -#define RTE_UART9_TX_DMA_NUMBER 1 -#define RTE_UART9_TX_DMA_STREAM 0 -#define RTE_UART9_TX_DMA_CHANNEL 5 -#define RTE_UART9_TX_DMA_PRIORITY 0 - -// - -// UART10 (Universal asynchronous receiver transmitter) [Driver_USART10] -// Configuration settings for Driver_USART10 in component ::CMSIS Driver:USART -#define RTE_UART10 0 - -// UART10_TX Pin <0=>Not Used <1=>PE3 <2=>PG12 -#define RTE_UART10_TX_ID 0 -#if (RTE_UART10_TX_ID == 0) -#define RTE_UART10_TX 0 -#elif (RTE_UART10_TX_ID == 1) -#define RTE_UART10_TX 1 -#define RTE_UART10_TX_PORT GPIOE -#define RTE_UART10_TX_BIT 3 -#elif (RTE_UART10_TX_ID == 2) -#define RTE_UART10_TX 1 -#define RTE_UART10_TX_PORT GPIOG -#define RTE_UART10_TX_BIT 12 -#else -#error "Invalid UART10_TX Pin Configuration!" -#endif - -// UART10_RX Pin <0=>Not Used <1=>PE2 <2=>PG11 -#define RTE_UART10_RX_ID 0 -#if (RTE_UART10_RX_ID == 0) -#define RTE_UART10_RX 0 -#elif (RTE_UART10_RX_ID == 1) -#define RTE_UART10_RX 1 -#define RTE_UART10_RX_PORT GPIOE -#define RTE_UART10_RX_BIT 2 -#elif (RTE_UART10_RX_ID == 2) -#define RTE_UART10_RX 1 -#define RTE_UART10_RX_PORT GPIOG -#define RTE_UART10_RX_BIT 11 -#else -#error "Invalid UART10_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <3=>3 -// Selects DMA Stream (only Stream 0 or 3 can be used) -// Channel <5=>5 <9=>9 -// Selects DMA Channel (only Channel 5 or 9 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART10_RX_DMA 0 -#define RTE_UART10_RX_DMA_NUMBER 1 -#define RTE_UART10_RX_DMA_STREAM 6 -#define RTE_UART10_RX_DMA_CHANNEL 5 -#define RTE_UART10_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 <3=>5 -// Selects DMA Stream (only Stream 7 or 5 can be used) -// Channel <6=>6 <9=>9 -// Selects DMA Channel (only Channel 6 or 9 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART10_TX_DMA 0 -#define RTE_UART10_TX_DMA_NUMBER 1 -#define RTE_UART10_TX_DMA_STREAM 0 -#define RTE_UART10_TX_DMA_CHANNEL 5 -#define RTE_UART10_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 0 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <6=>6 <7=>7 -// Selects DMA Stream (only Stream 1 or 6 or 7 can be used) -// Channel <0=>0 <1=>1 -// Selects DMA Channel (only Channel 0 or 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 0 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 <3=>PB3 <4=>PB9 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#elif (RTE_I2C2_SDA_PORT_ID == 3) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 3 -#elif (RTE_I2C2_SDA_PORT_ID == 4) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 9 -#else -#error "Invalid I2C2_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 0 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 0 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::CMSIS Driver:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 <2=>PB4 <3=>PB8 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#elif (RTE_I2C3_SDA_PORT_ID == 2) -#define RTE_I2C3_SDA_PORT GPIOB -#define RTE_I2C3_SDA_BIT 4 -#elif (RTE_I2C3_SDA_PORT_ID == 3) -#define RTE_I2C3_SDA_PORT GPIOB -#define RTE_I2C3_SDA_BIT 8 -#else -#error "Invalid I2C3_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <1=>1 <3=>3 -// Selects DMA Channel (only Channel 1 or 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 0 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 <5=>5 -// Selects DMA Stream (only Stream 4 or 5 can be used) -// Channel <3=>3 <6=>6 -// Selects DMA Channel (only Channel 3 or 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 0 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI -#define RTE_SPI1 0 - -// SPI1_MISO Pin <0=>Not Used <1=>PA6 <2=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO 0 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO 1 -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 2) -#define RTE_SPI1_MISO 1 -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>Not Used <1=>PA7 <2=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI 0 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI 1 -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 2) -#define RTE_SPI1_MOSI 1 -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MOSI Pin Configuration!" -#endif - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 -#define RTE_SPI1_NSS_PORT_ID 0 -#if (RTE_SPI1_NSS_PORT_ID == 0) -#define RTE_SPI1_NSS_PIN 0 -#elif (RTE_SPI1_NSS_PORT_ID == 1) -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIOA -#define RTE_SPI1_NSS_BIT 4 -#elif (RTE_SPI1_NSS_PORT_ID == 2) -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIOA -#define RTE_SPI1_NSS_BIT 15 -#else -#error "Invalid SPI1_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 0 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <3=>3 <5=>5 -// Selects DMA Stream (only Stream 2 or 3 or 5 can be used) -// Channel <2=>2 <3=>3 -// Selects DMA Channel (only Channel 2 or 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 0 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI -#define RTE_SPI2 0 - -// SPI2_MISO Pin <0=>Not Used <1=>PB14 <2=>PC2 <3=>PI2 <4=>PA12 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO 0 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 3) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 4) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOA -#define RTE_SPI2_MISO_BIT 12 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>Not Used <1=>PB15 <2=>PC3 <3=>PI3 <4=>PA10 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI 0 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 3) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 4) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOA -#define RTE_SPI2_MOSI_BIT 10 -#else -#error "Invalid SPI2_MOSI Pin Configuration!" -#endif - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PC7 <3=>PD3 <4=>PI1 <5=>PA9 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOC -#define RTE_SPI2_SCL_BIT 7 -#elif (RTE_SPI2_SCL_PORT_ID == 3) -#define RTE_SPI2_SCL_PORT GPIOD -#define RTE_SPI2_SCL_BIT 3 -#elif (RTE_SPI2_SCL_PORT_ID == 4) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#elif (RTE_SPI2_SCL_PORT_ID == 5) -#define RTE_SPI2_SCL_PORT GPIOA -#define RTE_SPI2_SCL_BIT 9 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_NSS Pin <0=>Not Used <1=>PB9 <2=>PB12 <3=>PI0 <4=>PA11 -#define RTE_SPI2_NSS_PORT_ID 0 -#if (RTE_SPI2_NSS_PORT_ID == 0) -#define RTE_SPI2_NSS_PIN 0 -#elif (RTE_SPI2_NSS_PORT_ID == 1) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOB -#define RTE_SPI2_NSS_BIT 9 -#elif (RTE_SPI2_NSS_PORT_ID == 2) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOB -#define RTE_SPI2_NSS_BIT 12 -#elif (RTE_SPI2_NSS_PORT_ID == 3) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOI -#define RTE_SPI2_NSS_BIT 0 -#elif (RTE_SPI2_NSS_PORT_ID == 4) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOA -#define RTE_SPI2_NSS_BIT 11 -#else -#error "Invalid SPI2_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 0 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 3 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 0 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 4 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI -#define RTE_SPI3 0 - -// SPI3_MISO Pin <0=>Not Used <1=>PB4 <2=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO 0 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO 1 -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 2) -#define RTE_SPI3_MISO 1 -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>Not Used <1=>PB5 <2=>PC12 <3=>PD6 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI 0 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 2) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#elif (RTE_SPI3_MOSI_PORT_ID == 3) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOD -#define RTE_SPI3_MOSI_BIT 6 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// SPI3_SCK Pin <0=>PB3 <1=>PB12 <2=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 12 -#elif (RTE_SPI3_SCL_PORT_ID == 2) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 -#define RTE_SPI3_NSS_PORT_ID 0 -#if (RTE_SPI3_NSS_PORT_ID == 0) -#define RTE_SPI3_NSS_PIN 0 -#elif (RTE_SPI3_NSS_PORT_ID == 1) -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIOA -#define RTE_SPI3_NSS_BIT 4 -#elif (RTE_SPI3_NSS_PORT_ID == 2) -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIOA -#define RTE_SPI3_NSS_BIT 15 -#else -#error "Invalid SPI3_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 0 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 0 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] -// Configuration settings for Driver_SPI4 in component ::CMSIS Driver:SPI -#define RTE_SPI4 0 - -// SPI4_MISO Pin <0=>Not Used <1=>PA11 <2=>PE5 <3=>PE13 -#define RTE_SPI4_MISO_PORT_ID 0 -#if (RTE_SPI4_MISO_PORT_ID == 0) -#define RTE_SPI4_MISO 0 -#elif (RTE_SPI4_MISO_PORT_ID == 1) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOA -#define RTE_SPI4_MISO_BIT 11 -#elif (RTE_SPI4_MISO_PORT_ID == 2) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOE -#define RTE_SPI4_MISO_BIT 5 -#elif (RTE_SPI4_MISO_PORT_ID == 3) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOE -#define RTE_SPI4_MISO_BIT 13 -#else -#error "Invalid SPI4_MISO Pin Configuration!" -#endif - -// SPI4_MOSI Pin <0=>Not Used <1=>PA1 <2=>PE6 <3=>PE14 -#define RTE_SPI4_MOSI_PORT_ID 0 -#if (RTE_SPI4_MOSI_PORT_ID == 0) -#define RTE_SPI4_MOSI 0 -#elif (RTE_SPI4_MOSI_PORT_ID == 1) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOA -#define RTE_SPI4_MOSI_BIT 1 -#elif (RTE_SPI4_MOSI_PORT_ID == 2) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOE -#define RTE_SPI4_MOSI_BIT 6 -#elif (RTE_SPI4_MOSI_PORT_ID == 3) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOE -#define RTE_SPI4_MOSI_BIT 14 -#else -#error "Invalid SPI4_MOSI Pin Configuration!" -#endif - -// SPI4_SCK Pin <0=>PB13 <1=>PE2 <2=>PE12 -#define RTE_SPI4_SCL_PORT_ID 0 -#if (RTE_SPI4_SCL_PORT_ID == 0) -#define RTE_SPI4_SCL_PORT GPIOB -#define RTE_SPI4_SCL_BIT 13 -#elif (RTE_SPI4_SCL_PORT_ID == 1) -#define RTE_SPI4_SCL_PORT GPIOE -#define RTE_SPI4_SCL_BIT 2 -#elif (RTE_SPI4_SCL_PORT_ID == 2) -#define RTE_SPI4_SCL_PORT GPIOE -#define RTE_SPI4_SCL_BIT 12 -#else -#error "Invalid SPI4_SCK Pin Configuration!" -#endif - -// SPI4_NSS Pin <0=>Not Used <1=>PB12 <2=>PE4 <3=>PE11 -#define RTE_SPI4_NSS_PORT_ID 0 -#if (RTE_SPI4_NSS_PORT_ID == 0) -#define RTE_SPI4_NSS_PIN 0 -#elif (RTE_SPI4_NSS_PORT_ID == 1) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOB -#define RTE_SPI4_NSS_BIT 12 -#elif (RTE_SPI4_NSS_PORT_ID == 2) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOE -#define RTE_SPI4_NSS_BIT 4 -#elif (RTE_SPI4_NSS_PORT_ID == 3) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOE -#define RTE_SPI4_NSS_BIT 11 -#else -#error "Invalid SPI4_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <3=>3 <4=>4 -// Selects DMA Stream (only Stream 0 or 3 can be used) -// Channel <4=>4 <5=>5 -// Selects DMA Channel (only Channel 4 or 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI4_RX_DMA 0 -#define RTE_SPI4_RX_DMA_NUMBER 1 -#define RTE_SPI4_RX_DMA_STREAM 0 -#define RTE_SPI4_RX_DMA_CHANNEL 0 -#define RTE_SPI4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <4=>4 -// Selects DMA Stream (only Stream 1 or 4 can be used) -// Channel <4=>4 <5=>5 -// Selects DMA Channel (only Channel 4 or 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI4_TX_DMA 0 -#define RTE_SPI4_TX_DMA_NUMBER 1 -#define RTE_SPI4_TX_DMA_STREAM 5 -#define RTE_SPI4_TX_DMA_CHANNEL 0 -#define RTE_SPI4_TX_DMA_PRIORITY 0 - -// - - -// SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] -// Configuration settings for Driver_SPI5 in component ::CMSIS Driver:SPI -#define RTE_SPI5 0 - -// SPI5_MISO Pin <0=>Not Used <1=>PA12 <2=>PE5 <3=>PE13 <4=>PF8 <5=>PH7 -#define RTE_SPI5_MISO_PORT_ID 0 -#if (RTE_SPI5_MISO_PORT_ID == 0) -#define RTE_SPI5_MISO 0 -#elif (RTE_SPI5_MISO_PORT_ID == 1) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOA -#define RTE_SPI5_MISO_BIT 12 -#elif (RTE_SPI5_MISO_PORT_ID == 2) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOE -#define RTE_SPI5_MISO_BIT 5 -#elif (RTE_SPI5_MISO_PORT_ID == 3) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOE -#define RTE_SPI5_MISO_BIT 13 -#elif (RTE_SPI5_MISO_PORT_ID == 4) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOF -#define RTE_SPI5_MISO_BIT 8 -#elif (RTE_SPI5_MISO_PORT_ID == 5) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOH -#define RTE_SPI5_MISO_BIT 7 -#else -#error "Invalid SPI5_MISO Pin Configuration!" -#endif - -// SPI5_MOSI Pin <0=>Not Used <1=>PA10 <2=>PB8 <3=>PE6 <4=>PE14 <5=>PF9 <6=>PF11 -#define RTE_SPI5_MOSI_PORT_ID 0 -#if (RTE_SPI5_MOSI_PORT_ID == 0) -#define RTE_SPI5_MOSI 0 -#elif (RTE_SPI5_MOSI_PORT_ID == 1) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOA -#define RTE_SPI5_MOSI_BIT 10 -#elif (RTE_SPI5_MOSI_PORT_ID == 2) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOB -#define RTE_SPI5_MOSI_BIT 8 -#elif (RTE_SPI5_MOSI_PORT_ID == 3) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOE -#define RTE_SPI5_MOSI_BIT 6 -#elif (RTE_SPI5_MOSI_PORT_ID == 4) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOE -#define RTE_SPI5_MOSI_BIT 14 -#elif (RTE_SPI5_MOSI_PORT_ID == 5) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOF -#define RTE_SPI5_MOSI_BIT 9 -#elif (RTE_SPI5_MOSI_PORT_ID == 6) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOF -#define RTE_SPI5_MOSI_BIT 11 -#else -#error "Invalid SPI5_MOSI Pin Configuration!" -#endif - -// SPI5_SCK Pin <0=>PB0 <1=>PE2 <2=>PE12 <3=>PF7 <4=>PH6 -#define RTE_SPI5_SCL_PORT_ID 0 -#if (RTE_SPI5_SCL_PORT_ID == 0) -#define RTE_SPI5_SCL_PORT GPIOB -#define RTE_SPI5_SCL_BIT 0 -#elif (RTE_SPI5_SCL_PORT_ID == 1) -#define RTE_SPI5_SCL_PORT GPIOE -#define RTE_SPI5_SCL_BIT 2 -#elif (RTE_SPI5_SCL_PORT_ID == 2) -#define RTE_SPI5_SCL_PORT GPIOE -#define RTE_SPI5_SCL_BIT 12 -#elif (RTE_SPI5_SCL_PORT_ID == 3) -#define RTE_SPI5_SCL_PORT GPIOF -#define RTE_SPI5_SCL_BIT 7 -#elif (RTE_SPI5_SCL_PORT_ID == 4) -#define RTE_SPI5_SCL_PORT GPIOH -#define RTE_SPI5_SCL_BIT 6 -#else -#error "Invalid SPI5_SCK Pin Configuration!" -#endif - -// SPI5_NSS Pin <0=>Not Used <1=>PB1 <2=>PE4 <3=>PE11 <4=>PF6 <5=>PH5 -#define RTE_SPI5_NSS_PORT_ID 0 -#if (RTE_SPI5_NSS_PORT_ID == 0) -#define RTE_SPI5_NSS_PIN 0 -#elif (RTE_SPI5_NSS_PORT_ID == 1) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOB -#define RTE_SPI5_NSS_BIT 1 -#elif (RTE_SPI5_NSS_PORT_ID == 2) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOE -#define RTE_SPI5_NSS_BIT 4 -#elif (RTE_SPI5_NSS_PORT_ID == 3) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOE -#define RTE_SPI5_NSS_BIT 11 -#elif (RTE_SPI5_NSS_PORT_ID == 4) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOF -#define RTE_SPI5_NSS_BIT 6 -#elif (RTE_SPI5_NSS_PORT_ID == 5) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOH -#define RTE_SPI5_NSS_BIT 5 -#else -#error "Invalid SPI5_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <2=>2 <7=>7 -// Selects DMA Channel (only Channel 2 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI5_RX_DMA 0 -#define RTE_SPI5_RX_DMA_NUMBER 2 -#define RTE_SPI5_RX_DMA_STREAM 3 -#define RTE_SPI5_RX_DMA_CHANNEL 2 -#define RTE_SPI5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <4=>4 <5=>5 <6=>6 -// Selects DMA Stream (only Stream 4 or 6 can be used) -// Channel <2=>2 <5=>5 <7=>7 -// Selects DMA Channel (only Channel 2 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI5_TX_DMA 0 -#define RTE_SPI5_TX_DMA_NUMBER 2 -#define RTE_SPI5_TX_DMA_STREAM 4 -#define RTE_SPI5_TX_DMA_CHANNEL 2 -#define RTE_SPI5_TX_DMA_PRIORITY 0 - -// - - -// SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] -// Configuration settings for Driver_SPI6 in component ::CMSIS Driver:SPI -#define RTE_SPI6 0 - -// SPI6_MISO Pin <0=>Not Used <1=>PG12 -#define RTE_SPI6_MISO_PORT_ID 0 -#if (RTE_SPI6_MISO_PORT_ID == 0) -#define RTE_SPI6_MISO 0 -#elif (RTE_SPI6_MISO_PORT_ID == 1) -#define RTE_SPI6_MISO 1 -#define RTE_SPI6_MISO_PORT GPIOG -#define RTE_SPI6_MISO_BIT 12 -#else -#error "Invalid SPI6_MISO Pin Configuration!" -#endif - -// SPI6_MOSI Pin <0=>Not Used <1=>PG14 -#define RTE_SPI6_MOSI_PORT_ID 0 -#if (RTE_SPI6_MOSI_PORT_ID == 0) -#define RTE_SPI6_MOSI 0 -#elif (RTE_SPI6_MOSI_PORT_ID == 1) -#define RTE_SPI6_MOSI 1 -#define RTE_SPI6_MOSI_PORT GPIOG -#define RTE_SPI6_MOSI_BIT 14 -#else -#error "Invalid SPI6_MOSI Pin Configuration!" -#endif - -// SPI6_SCK Pin <0=>PG13 -#define RTE_SPI6_SCL_PORT_ID 0 -#if (RTE_SPI6_SCL_PORT_ID == 0) -#define RTE_SPI6_SCL_PORT GPIOG -#define RTE_SPI6_SCL_BIT 13 -#else -#error "Invalid SPI6_SCK Pin Configuration!" -#endif - -// SPI6_NSS Pin <0=>Not Used <1=>PG8 -#define RTE_SPI6_NSS_PORT_ID 0 -#if (RTE_SPI6_NSS_PORT_ID == 0) -#define RTE_SPI6_NSS_PIN 0 -#elif (RTE_SPI6_NSS_PORT_ID == 1) -#define RTE_SPI6_NSS_PIN 1 -#define RTE_SPI6_NSS_PORT GPIOG -#define RTE_SPI6_NSS_BIT 8 -#else -#error "Invalid SPI6_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI6_RX_DMA 0 -#define RTE_SPI6_RX_DMA_NUMBER 2 -#define RTE_SPI6_RX_DMA_STREAM 6 -#define RTE_SPI6_RX_DMA_CHANNEL 1 -#define RTE_SPI6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI6_TX_DMA 0 -#define RTE_SPI6_TX_DMA_NUMBER 2 -#define RTE_SPI6_TX_DMA_STREAM 5 -#define RTE_SPI6_TX_DMA_CHANNEL 1 -#define RTE_SPI6_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI -#define RTE_SDIO 0 - -// SDIO Peripheral Bus -// SDIO_CK Pin <0=>PC12 <1=>PB15 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) - #define RTE_SDIO_CK_PORT GPIOC - #define RTE_SDIO_CK_PIN GPIO_PIN_12 -#elif (RTE_SDIO_CK_PORT_ID == 1) - #define RTE_SDIO_CK_PORT GPIOB - #define RTE_SDIO_CK_PIN GPIO_PIN_15 -#else - #error "Invalid SD_CLK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 <1=>PA6 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) - #define RTE_SDIO_CMD_PORT GPIOD - #define RTE_SDIO_CMD_PIN GPIO_PIN_2 -#elif (RTE_SDIO_CMD_PORT_ID == 1) - #define RTE_SDIO_CMD_PORT GPIOA - #define RTE_SDIO_CMD_PIN GPIO_PIN_6 -#else - #error "Invalid SD_CMD Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 <1=>PB4 <2=>PB6 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) - #define RTE_SDIO_D0_PORT GPIOC - #define RTE_SDIO_D0_PIN GPIO_PIN_8 -#elif (RTE_SDIO_D0_PORT_ID == 1) - #define RTE_SDIO_D0_PORT GPIOB - #define RTE_SDIO_D0_PIN GPIO_PIN_4 -#elif (RTE_SDIO_D0_PORT_ID == 2) - #define RTE_SDIO_D0_PORT GPIOB - #define RTE_SDIO_D0_PIN GPIO_PIN_6 -#else - #error "Invalid SD_DAT0 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -#define RTE_SDIO_BUS_WIDTH_4 1 -// SDIO_D1 Pin <0=>PC9 <1=>PA8 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) - #define RTE_SDIO_D1_PORT GPIOC - #define RTE_SDIO_D1_PIN GPIO_PIN_9 -#elif (RTE_SDIO_D1_PORT_ID == 1) - #define RTE_SDIO_D1_PORT GPIOA - #define RTE_SDIO_D1_PIN GPIO_PIN_8 -#else - #error "Invalid SD_DAT1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 <1=>PA9 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) - #define RTE_SDIO_D2_PORT GPIOC - #define RTE_SDIO_D2_PIN GPIO_PIN_10 -#elif (RTE_SDIO_D2_PORT_ID == 1) - #define RTE_SDIO_D2_PORT GPIOA - #define RTE_SDIO_D2_PIN GPIO_PIN_9 -#else - #error "Invalid SD_DAT2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 <1=>PB5 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) - #define RTE_SDIO_D3_PORT GPIOC - #define RTE_SDIO_D3_PIN GPIO_PIN_11 -#elif (RTE_SDIO_D3_PORT_ID == 1) - #define RTE_SDIO_D3_PORT GPIOB - #define RTE_SDIO_D3_PIN GPIO_PIN_5 -#else - #error "Invalid SD_DAT3 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -// SDIO_D[4 .. 7] -#define RTE_SDIO_BUS_WIDTH_8 0 -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) - #define RTE_SDIO_D4_PORT GPIOB - #define RTE_SDIO_D4_PIN GPIO_PIN_8 -#else - #error "Invalid SD_DAT4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) - #define RTE_SDIO_D5_PORT GPIOB - #define RTE_SDIO_D5_PIN GPIO_PIN_9 -#else - #error "Invalid SD_DAT5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 <1=>PB14 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) - #define RTE_SDIO_D6_PORT GPIOC - #define RTE_SDIO_D6_PIN GPIO_PIN_6 -#elif (RTE_SDIO_D6_PORT_ID == 1) - #define RTE_SDIO_D6_PORT GPIOB - #define RTE_SDIO_D6_PIN GPIO_PIN_14 -#else - #error "Invalid SD_DAT6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 <1=>PB10 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) - #define RTE_SDIO_D7_PORT GPIOC - #define RTE_SDIO_D7_PIN GPIO_PIN_7 -#elif (RTE_SDIO_D7_PORT_ID == 1) - #define RTE_SDIO_D7_PORT GPIOB - #define RTE_SDIO_D7_PIN GPIO_PIN_10 -#else - #error "Invalid SD_DAT7 Pin Configuration!" -#endif -// SDIO_D[4 .. 7] -// SDIO Peripheral Bus - -// Card Detect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN_EN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_PIN 15 - -// Write Protect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_EN 0 -#define RTE_SDIO_WP_ACTIVE 1 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_PIN 10 - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_RX_DMA 1 -#define RTE_SDIO_RX_DMA_NUMBER 2 -#define RTE_SDIO_RX_DMA_STREAM 3 -#define RTE_SDIO_RX_DMA_CHANNEL 4 -#define RTE_SDIO_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_TX_DMA 1 -#define RTE_SDIO_TX_DMA_NUMBER 2 -#define RTE_SDIO_TX_DMA_STREAM 6 -#define RTE_SDIO_TX_DMA_CHANNEL 4 -#define RTE_SDIO_TX_DMA_PRIORITY 0 - -// - - -// CAN1 (Controller Area Network 1) [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN -#define RTE_CAN1 0 - -// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 <3=>PI9 <4=>PG0 -#define RTE_CAN1_RX_PORT_ID 0 -#if (RTE_CAN1_RX_PORT_ID == 0) -#define RTE_CAN1_RX_PORT GPIOA -#define RTE_CAN1_RX_BIT GPIO_PIN_11 -#elif (RTE_CAN1_RX_PORT_ID == 1) -#define RTE_CAN1_RX_PORT GPIOB -#define RTE_CAN1_RX_BIT GPIO_PIN_8 -#elif (RTE_CAN1_RX_PORT_ID == 2) -#define RTE_CAN1_RX_PORT GPIOD -#define RTE_CAN1_RX_BIT GPIO_PIN_0 -#elif (RTE_CAN1_RX_PORT_ID == 3) -#define RTE_CAN1_RX_PORT GPIOI -#define RTE_CAN1_RX_BIT GPIO_PIN_9 -#elif (RTE_CAN1_RX_PORT_ID == 4) -#define RTE_CAN1_RX_PORT GPIOG -#define RTE_CAN1_RX_BIT GPIO_PIN_0 -#else -#error "Invalid CAN1_RX Pin Configuration!" -#endif - -// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 <3=>PH13 <4=>PG1 -#define RTE_CAN1_TX_PORT_ID 0 -#if (RTE_CAN1_TX_PORT_ID == 0) -#define RTE_CAN1_TX_PORT GPIOA -#define RTE_CAN1_TX_BIT GPIO_PIN_12 -#elif (RTE_CAN1_TX_PORT_ID == 1) -#define RTE_CAN1_TX_PORT GPIOB -#define RTE_CAN1_TX_BIT GPIO_PIN_9 -#elif (RTE_CAN1_TX_PORT_ID == 2) -#define RTE_CAN1_TX_PORT GPIOD -#define RTE_CAN1_TX_BIT GPIO_PIN_1 -#elif (RTE_CAN1_TX_PORT_ID == 3) -#define RTE_CAN1_TX_PORT GPIOH -#define RTE_CAN1_TX_BIT GPIO_PIN_13 -#elif (RTE_CAN1_TX_PORT_ID == 4) -#define RTE_CAN1_TX_PORT GPIOG -#define RTE_CAN1_TX_BIT GPIO_PIN_1 -#else -#error "Invalid CAN1_TX Pin Configuration!" -#endif - -// - - -// CAN2 (Controller Area Network 2) [Driver_CAN2] -// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN -#define RTE_CAN2 0 - -// CAN2_RX Pin <0=>PB5 <1=>PB12 <2=>PG11 -#define RTE_CAN2_RX_PORT_ID 0 -#if (RTE_CAN2_RX_PORT_ID == 0) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT GPIO_PIN_5 -#elif (RTE_CAN2_RX_PORT_ID == 1) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT GPIO_PIN_12 -#elif (RTE_CAN2_RX_PORT_ID == 2) -#define RTE_CAN2_RX_PORT GPIOG -#define RTE_CAN2_RX_BIT GPIO_PIN_11 -#else -#error "Invalid CAN2_RX Pin Configuration!" -#endif - -// CAN2_TX Pin <0=>PB6 <1=>PB13 <2=>PG12 -#define RTE_CAN2_TX_PORT_ID 0 -#if (RTE_CAN2_TX_PORT_ID == 0) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT GPIO_PIN_6 -#elif (RTE_CAN2_TX_PORT_ID == 1) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT GPIO_PIN_13 -#elif (RTE_CAN2_TX_PORT_ID == 2) -#define RTE_CAN2_TX_PORT GPIOG -#define RTE_CAN2_TX_BIT GPIO_PIN_12 -#else -#error "Invalid CAN2_TX Pin Configuration!" -#endif - -// - - -// CAN3 (Controller Area Network 3) [Driver_CAN3] -// Configuration settings for Driver_CAN3 in component ::CMSIS Driver:CAN -// Available only on STM32F413xx and STM32F423xx device series -#define RTE_CAN3 0 - -// CAN3_RX Pin <0=>PA8 <1=>PB3 -#define RTE_CAN3_RX_PORT_ID 0 -#if (RTE_CAN3_RX_PORT_ID == 0) -#define RTE_CAN3_RX_PORT GPIOA -#define RTE_CAN3_RX_BIT GPIO_PIN_8 -#elif (RTE_CAN3_RX_PORT_ID == 1) -#define RTE_CAN3_RX_PORT GPIOB -#define RTE_CAN3_RX_BIT GPIO_PIN_3 -#else -#error "Invalid CAN3_RX Pin Configuration!" -#endif - -// CAN3_TX Pin <0=>PA15 <1=>PB4 -#define RTE_CAN3_TX_PORT_ID 0 -#if (RTE_CAN3_TX_PORT_ID == 0) -#define RTE_CAN3_TX_PORT GPIOA -#define RTE_CAN3_TX_BIT GPIO_PIN_15 -#elif (RTE_CAN3_TX_PORT_ID == 1) -#define RTE_CAN3_TX_PORT GPIOB -#define RTE_CAN3_TX_BIT GPIO_PIN_4 -#else -#error "Invalid CAN3_TX Pin Configuration!" -#endif - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC -#define RTE_ETH 1 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RX_ER_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::CMSIS Driver:USB Device - -#define RTE_USB_OTG_FS_DEVICE 1 - -// VBUS Sensing Pin -// Enable or disable VBUS sensing -#define RTE_OTG_FS_VBUS_SENSING_PIN 1 -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::CMSIS Driver:USB Host - -#define RTE_USB_OTG_FS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC3 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 3 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::CMSIS Driver:USB Device - -#define RTE_USB_OTG_HS_DEVICE 0 - -// VBUS Sensing Pin -// Enable or disable VBUS sensing -// Relevant only if PHY Interface On-chip full-speed PHY is selected -#define RTE_OTG_HS_VBUS_SENSING_PIN 0 -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::CMSIS Driver:USB Host -#define RTE_USB_OTG_HS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 0 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(2) -#define RTE_OTG_HS_OC_BIT 5 -// - -// DMA -// Use dedicated DMA for transfers -// If DMA is used all USB transfer data buffers have to be 4-byte aligned. -#define RTE_OTG_HS_DMA 0 - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/startup_stm32f407xx.s b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/startup_stm32f407xx.s deleted file mode 100644 index 4044480..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/startup_stm32f407xx.s +++ /dev/null @@ -1,438 +0,0 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32f407xx.s -;* Author : MCD Application Team -;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001800 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/stm32f4xx_hal_conf.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/stm32f4xx_hal_conf.h deleted file mode 100644 index be5dc65..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,615 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file - * - * @note modified by ARM - * The modifications allow to use this file as User Code Template - * within the Device Family Pack. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017-2018 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef _RTE_ -#include "RTE_Components.h" /* Component selection */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#ifdef RTE_DEVICE_HAL_COMMON -#define HAL_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_ADC -#define HAL_ADC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CAN -#define HAL_CAN_MODULE_ENABLED -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -#endif -#ifdef RTE_DEVICE_HAL_CRC -#define HAL_CRC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CEC -#define HAL_CEC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CRYP -#define HAL_CRYP_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DAC -#define HAL_DAC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DCMI -#define HAL_DCMI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DMA -#define HAL_DMA_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DMA2D -#define HAL_DMA2D_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_ETH -#define HAL_ETH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_EXTI -#define HAL_EXTI_MODULE_ENABLED -#endif -#if defined (RTE_DEVICE_HAL_FLASH) || defined (RTE_DEVICE_HAL_COMMON) -#define HAL_FLASH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_NAND -#define HAL_NAND_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_NOR -#define HAL_NOR_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PCCARD -#define HAL_PCCARD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SRAM -#define HAL_SRAM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SDRAM -#define HAL_SDRAM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_HASH -#define HAL_HASH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_GPIO -#define HAL_GPIO_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_I2C -#define HAL_I2C_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_I2S -#define HAL_I2S_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_IWDG -#define HAL_IWDG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_LTDC -#define HAL_LTDC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DSI -#define HAL_DSI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PWR -#define HAL_PWR_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_QSPI -#define HAL_QSPI_MODULE_ENABLED -#endif -#if defined (RTE_DEVICE_HAL_RCC) || defined (RTE_DEVICE_HAL_COMMON) -#define HAL_RCC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_RNG -#define HAL_RNG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_RTC -#define HAL_RTC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SAI -#define HAL_SAI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SD -#define HAL_SD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SPI -#define HAL_SPI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_TIM -#define HAL_TIM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_UART -#define HAL_UART_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_USART -#define HAL_USART_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_IRDA -#define HAL_IRDA_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SMARTCARD -#define HAL_SMARTCARD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_WWDG -#define HAL_WWDG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CORTEX -#define HAL_CORTEX_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PCD -#define HAL_PCD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_HCD -#define HAL_HCD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_FMPI2C -#define HAL_FMPI2C_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SPDIFRX -#define HAL_SPDIFRX_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DFSDM -#define HAL_DFSDM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_LPTIM -#define HAL_LPTIM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_MMC -#define HAL_MMC_MODULE_ENABLED -#endif - - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the external oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 0 /* The prefetch will be enabled in SystemClock_Config(), depending on the used - STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */ -#define INSTRUCTION_CACHE_ENABLE 1 -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2 -#define MAC_ADDR1 0 -#define MAC_ADDR2 0 -#define MAC_ADDR3 0 -#define MAC_ADDR4 0 -#define MAC_ADDR5 0 - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB (4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB (4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY (0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY (0x00000FFFU) - -#define PHY_READ_TO (0x0000FFFFU) -#define PHY_WRITE_TO (0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/system_stm32f4xx.c b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/system_stm32f4xx.c deleted file mode 100644 index 04569a1..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/system_stm32f4xx.c +++ /dev/null @@ -1,764 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - * @note modified by ARM - * adapted for board MCBSTM32F400. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017-2018 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - - -#include "stm32f4xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ - || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) -/* #define DATA_IN_ExtSRAM */ -#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ - STM32F412Zx || STM32F412Vx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/* #define DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -uint32_t SystemCoreClock = 16000000; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value - * depends on the application requirements), user has to ensure that HSE_VALUE - * is same as the real frequency of the crystal used. Otherwise, this function - * may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external memories (SRAM/SDRAM) - * This SRAM/SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmp = 0x00; - - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ - RCC->AHB1ENR |= 0x000001F8; - - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; - -/*-- FMC Configuration -------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - - FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ - FMC_Bank5_6->SDCMR = 0x00000073; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ - FMC_Bank5_6->SDCMR = 0x00046014; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001091; - FMC_Bank1->BTCR[3] = 0x00110212; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F469xx || STM32F479xx */ - - (void)(tmp); -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external memories (SRAM/SDRAM) - * This SRAM/SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmp = 0x00; -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#if defined (DATA_IN_ExtSDRAM) - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - -#if defined(STM32F446xx) - /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface - clock */ - RCC->AHB1ENR |= 0x0000007D; -#else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface - clock */ - RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - -#if defined(STM32F446xx) - /* Connect PAx pins to FMC Alternate function */ - GPIOA->AFR[0] |= 0xC0000000; - GPIOA->AFR[1] |= 0x00000000; - /* Configure PDx pins in Alternate function mode */ - GPIOA->MODER |= 0x00008000; - /* Configure PDx pins speed to 50 MHz */ - GPIOA->OSPEEDR |= 0x00008000; - /* Configure PDx pins Output type to push-pull */ - GPIOA->OTYPER |= 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOA->PUPDR |= 0x00000000; - - /* Connect PCx pins to FMC Alternate function */ - GPIOC->AFR[0] |= 0x00CC0000; - GPIOC->AFR[1] |= 0x00000000; - /* Configure PDx pins in Alternate function mode */ - GPIOC->MODER |= 0x00000A00; - /* Configure PDx pins speed to 50 MHz */ - GPIOC->OSPEEDR |= 0x00000A00; - /* Configure PDx pins Output type to push-pull */ - GPIOC->OTYPER |= 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOC->PUPDR |= 0x00000000; -#endif /* STM32F446xx */ - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x000000CC; - GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ - GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ - GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - -/*-- FMC Configuration -------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - - /* Configure and enable SDRAM bank1 */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCR[0] = 0x00001954; -#else - FMC_Bank5_6->SDCR[0] = 0x000019E4; -#endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCMR = 0x000000F3; -#else - FMC_Bank5_6->SDCMR = 0x00000073; -#endif /* STM32F446xx */ - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ -#if defined(STM32F446xx) - FMC_Bank5_6->SDCMR = 0x00044014; -#else - FMC_Bank5_6->SDCMR = 0x00046014; -#endif /* STM32F446xx */ - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; -#if defined(STM32F446xx) - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); -#endif /* STM32F446xx */ - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); -#endif /* DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ - || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) - -#if defined(DATA_IN_ExtSRAM) -/*-- GPIOs Configuration -----------------------------------------------------*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0xC0CC00CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA8A0A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFFCF0F; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC0CCC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA8A8A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFCFCF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x00000C00; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00200AAA; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x00300FFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FMC/FSMC Configuration --------------------------------------------------*/ - /* Enable the FMC/FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#if defined(STM32F469xx) || defined(STM32F479xx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001091; - FMC_Bank1->BTCR[3] = 0x00110212; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F469xx || STM32F479xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ - || defined(STM32F412Zx) || defined(STM32F412Vx) - /* Delay after an RCC peripheral clock enabling */ - tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); - /* Configure and enable Bank1_SRAM3 */ - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00100911; - FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ - -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); -} -#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config.c b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config.c deleted file mode 100644 index 6946e8f..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config.c +++ /dev/null @@ -1,173 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V7.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Network System Settings -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "SockServer" - -// Memory Pool Size <1536-262144:4> -// This is the size of a memory pool in bytes. Buffers for -// network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_POOL_SIZE 16384 - -// Start System Services -// If enabled, the system will automatically start server services -// (HTTP, FTP, TFTP server, ...) when initializing the network system. -// Default: Enabled -#define NET_START_SERVICE 1 - -// OS Resource Settings -// These settings are used to optimize usage of OS resources. -// Core Thread Stack Size <512-65535:4> -// Default: 1024 bytes -#define NET_THREAD_STACK_SIZE 1024 - -// Core Thread Priority -#define NET_THREAD_PRIORITY osPriorityNormal - -// -// - -//------------- <<< end of configuration section >>> --------------------------- - -#include "RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_WiFi_0 -#include "Net_Config_WiFi_0.h" -#endif - -#ifdef RTE_Network_Interface_WiFi_1 -#include "Net_Config_WiFi_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP -#include "Net_Config_PPP.h" -#endif - -#ifdef RTE_Network_Interface_SLIP -#include "Net_Config_SLIP.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (NET_ERROR error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (NET_ERROR error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case NET_ERROR_MEM_ALLOC: - /* Out of memory */ - break; - - case NET_ERROR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case NET_ERROR_MEM_CORRUPT: - /* Memory Link pointer corrupted */ - /* More data written than the size of allocated memory block */ - break; - - case NET_ERROR_CONFIG: - /* Network configuration error detected */ - break; - - case NET_ERROR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case NET_ERROR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case NET_ERROR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_BSD.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index 8b7ba1b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,38 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration for BSD Sockets - * Rev.: V5.0.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 9 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 5 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_ETH_0.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index e554082..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,247 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration for ETH Interface - * Rev.: V7.2.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 0 - -// MAC Address -// Ethernet MAC Address in text representation -// Value FF-FF-FF-FF-FF-FF is not allowed, -// LSB of first byte must be 0 (an ethernet Multicast bit). -// Default: "1E-30-6C-A2-45-5E" -#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5A" - -// VLAN -// Enable or disable Virtual LAN -#define ETH0_VLAN_ENABLE 0 - -// VLAN Identifier <1-4093> -// A unique 12-bit numeric value -// Default: 1 -#define ETH0_VLAN_ID 1 -// - -// IPv4 -// Enable IPv4 Protocol for Network Interface -#define ETH0_IP4_ENABLE 1 - -// IP Address -// Static IPv4 Address in text representation -// Default: "192.168.0.100" -#define ETH0_IP4_ADDR "192.168.0.100" - -// Subnet mask -// Local Subnet mask in text representation -// Default: "255.255.255.0" -#define ETH0_IP4_MASK "255.255.255.0" - -// Default Gateway -// IP Address of Default Gateway in text representation -// Default: "192.168.0.254" -#define ETH0_IP4_GATEWAY "192.168.0.254" - -// Primary DNS Server -// IP Address of Primary DNS Server in text representation -// Default: "8.8.8.8" -#define ETH0_IP4_PRIMARY_DNS "8.8.8.8" - -// Secondary DNS Server -// IP Address of Secondary DNS Server in text representation -// Default: "8.8.4.4" -#define ETH0_IP4_SECONDARY_DNS "8.8.4.4" - -// IP Fragmentation -// This option enables fragmentation of outgoing IP datagrams, -// and reassembling the fragments of incoming IP datagrams. -// Default: enabled -#define ETH0_IP4_FRAG_ENABLE 1 - -// MTU size <576-1500> -// Maximum Transmission Unit in bytes -// Default: 1500 -#define ETH0_IP4_MTU 1500 -// - -// ARP Address Resolution -// ARP cache and node address resolver settings -// Cache Table size <5-100> -// Number of cached MAC/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by its name on local LAN using NBNS protocol. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -#define ETH0_DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// -// - -// IPv6 -// Enable IPv6 Protocol for Network Interface -#define ETH0_IP6_ENABLE 1 - -// IPv6 Address -// Static IPv6 Address in text representation -// Use unspecified address "::" when static -// IPv6 address is not used. -// Default: "fec0::2" -#define ETH0_IP6_ADDR "fec0::2" - -// Subnet prefix-length <1-128> -// Number of bits that define network address -// Default: 64 -#define ETH0_IP6_PREFIX_LEN 64 - -// Default Gateway -// Default Gateway IPv6 Address in text representation -// Default: "fec0::1" -#define ETH0_IP6_GATEWAY "fec0::1" - -// Primary DNS Server -// Primary DNS Server IPv6 Address in text representation -// Default: "2001:4860:4860::8888" -#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888" - -// Secondary DNS Server -// Secondary DNS Server IPv6 Address in text representation -// Default: "2001:4860:4860::8844" -#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844" - -// Neighbor Discovery -// Neighbor cache and node address resolver settings -// Cache Table size <5-100> -// Number of cached node addresses -// Default: 5 -#define ETH0_NDP_TAB_SIZE 5 - -// Cache Timeout in seconds <5-255> -// Timeout for cached node addresses -// Default: 150 -#define ETH0_NDP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of retries to resolve an IP address -// before NDP module gives up -// Default: 4 -#define ETH0_NDP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend Neighbor Solicitation -// Default: 2 -#define ETH0_NDP_RESEND_TOUT 2 -// - -// Dynamic Host Configuration -// When this option is enabled, local IPv6 address is -// automatically configured. -#define ETH0_DHCP6_ENABLE 1 - -// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode -// Stateless DHCPv6 Client uses router advertisements -// for IPv6 address autoconfiguration (SLAAC). -// Statefull DHCPv6 Client connects to DHCPv6 server for a -// leased IPv6 address and DNS server IPv6 addresses. -#define ETH0_DHCP6_MODE 1 - -// Vendor Class Option -// If enabled, Vendor Class option is added to DHCPv6 -// request message, identifying vendor type. -// Default: disabled -#define ETH0_DHCP6_VCLASS_ENABLE 0 - -// Enterprise ID -// Enterprise-number as registered with IANA. -// Default: 0 (Reserved) -#define ETH0_DHCP6_VCLASS_EID 0 - -// Vendor Class Data -// This string identifies vendor type. -// Default: "" -#define ETH0_DHCP6_VCLASS_DATA "" -// -// -// - -// OS Resource Settings -// These settings are used to optimize usage of OS resources. -// Interface Thread Stack Size <512-65535:4> -// Default: 512 bytes -#define ETH0_THREAD_STACK_SIZE 512 - -// Interface Thread Priority -#define ETH0_THREAD_PRIORITY osPriorityAboveNormal - -// -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_TCP.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index 5a5de02..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,69 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration for TCP Sockets - * Rev.: V7.1.1 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 6 -#define TCP_NUM_SOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-65535> -// If no TCP data frame has been exchanged during this time, -// the TCP connection is either closed or a keep-alive frame -// is sent to verify that the connection still exists. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1440> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1440 -#define TCP_MAX_SEG_SIZE 1440 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4320 -#define TCP_RECEIVE_WIN_SIZE 4320 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - -// Dynamic port start (default 49152) -#define TCP_DYN_PORT_START 49152 - -// Dynamic port end (default 65535) -#define TCP_DYN_PORT_END 65535 - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_Telnet_Server.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_Telnet_Server.h deleted file mode 100644 index 929d14b..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_Telnet_Server.h +++ /dev/null @@ -1,58 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_Telnet_Server.h - * Purpose: Network Configuration for Telnet Server - * Rev.: V7.0.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Telnet Server -#define TELNET_SERVER_ENABLE 1 - -// Number of Connections <1-10> -// Number of simultaneously active Telnet Connections. -// Default: 1 -#define TELNET_SERVER_NUM_SESSISONS 1 - -// Port Number <1-65535> -// Listening port number. -// Default: 23 -#define TELNET_SERVER_PORT_NUM 23 - -// Idle Connection Timeout in seconds <0-3600> -// When timeout expires, the connection is closed. -// A value of 0 disables disconnection on timeout. -// Default: 120 -#define TELNET_SERVER_TOUT 120 - -// Disable Echo -// When disabled, the server will not echo characters it receives. -// Default: Not disabled -#define TELNET_SERVER_NO_ECHO 0 - -// Enable User Authentication -// When enabled, requires authentication of the user through -// the credentials to access the server. -#define TELNET_SERVER_AUTH_ENABLE 0 - -// Built-in Administrator Account -// Enable the built-in Administrator account on the server -// Default: Enabled -#define TELNET_SERVER_AUTH_ADMIN 1 - -// Administrator Username -// Default: "admin" -#define TELNET_SERVER_AUTH_USER "admin" - -// Administrator Password -// Default: "" -#define TELNET_SERVER_AUTH_PASS "" -// -// - -// - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_UDP.h b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index b6b2172..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,28 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration for UDP Sockets - * Rev.: V5.1.0 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 11 - -// - -// Dynamic port start (default 49152) -#define UDP_DYN_PORT_START 49152 - -// Dynamic port end (default 65535) -#define UDP_DYN_PORT_END 65535 - -//------------- <<< end of configuration section >>> --------------------------- diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/SockServer.uvguix b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/SockServer.uvguix deleted file mode 100644 index 3e2b7c2..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/SockServer.uvguix +++ /dev/null @@ -1,1878 +0,0 @@ - - - - -6.1 - -
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
- - - - STM32F407 Flash - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - STM32F407IGHx - STMicroelectronics - Keil.STM32F4xx_DFP.2.13.0 - http://www.keil.com/pack - IROM(0x08000000,0x100000) IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM)) - 0 - $$Device:STM32F407IGHx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h - - - - - - - - - - $$Device:STM32F407IGHx$CMSIS\SVD\STM32F40x.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - SockServer - 1 - 0 - 0 - 1 - 0 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 1 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 1 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x10000000 - 0x10000 - - - - - - 1 - 4 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - HSE_VALUE=25000000 - - ..\..\Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Source - - - main.c - 1 - .\main.c - - - - - Documentation - - - Abstract.txt - 5 - .\Abstract.txt - - - - - SockServer Source - - - SockServer.c - 1 - ..\..\Source\SockServer.c - - - Telnet_Server_UIF.c - 1 - ..\..\Source\Telnet_Server_UIF.c - - - - - ::Board Support - - - ::CMSIS - - - ::CMSIS Driver - - - ::Device - - - ::Network - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RTE\CMSIS\RTX_Config.c - - - - - - - - RTE\CMSIS\RTX_Config.h - - - - - - - - RTE\Device\STM32F407IGHx\RTE_Device.h - - - - - - - - RTE\Device\STM32F407IGHx\startup_stm32f407xx.s - - - - - - - - RTE\Device\STM32F407IGHx\stm32f4xx_hal_conf.h - - - - - - - - RTE\Device\STM32F407IGHx\system_stm32f4xx.c - - - - - - - - RTE\Network\Net_Config.c - - - - - - - - RTE\Network\Net_Config_BSD.h - - - - - - - - RTE\Network\Net_Config_ETH_0.h - - - - - - - - RTE\Network\Net_Config_TCP.h - - - - - - - - RTE\Network\Net_Config_Telnet_Server.h - - - - - - - - RTE\Network\Net_Config_UDP.h - - - - - - - - - - diff --git a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/main.c b/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/main.c deleted file mode 100644 index 5458912..0000000 --- a/Tools/SockServer/Embedded/MDK/Board/MCBSTM32F400/main.c +++ /dev/null @@ -1,231 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2019 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: main.c - * Purpose: Socket tester using BSD sockets - *----------------------------------------------------------------------------*/ - -#include -#include -#include "RTE_Components.h" -#include CMSIS_device_header -#include "stm32f4xx_hal.h" -#include "cmsis_os2.h" -#include "rl_net.h" -#include "SockServer.h" - -#include "Board_LED.h" -#include "Board_GLCD.h" -#include "GLCD_Config.h" - -extern GLCD_FONT GLCD_Font_6x8; -extern GLCD_FONT GLCD_Font_16x24; - -static osThreadId_t display_id; - -// Functions -static void app_main (void *argument); -static void DisplayServer (void *argument); - -// IP address change notification -void netDHCP_Notify (uint32_t if_num, uint8_t opt, const uint8_t *val, uint32_t len) { - if (opt == NET_DHCP_OPTION_IP_ADDRESS) { - osThreadFlagsSet (display_id, 0x01); - } -} - - -// LCD display handler thread -static void DisplayServer (void *argument) { - uint8_t ip_addr[NET_ADDR_IP4_LEN]; - static char ip_ascii[16]; - static char buf[24]; - - GLCD_Initialize (); - GLCD_SetBackgroundColor (GLCD_COLOR_BLUE); - GLCD_SetForegroundColor (GLCD_COLOR_WHITE); - GLCD_ClearScreen (); - GLCD_SetFont (&GLCD_Font_16x24); - GLCD_DrawString (0, 1*24, " MW-Network "); - GLCD_DrawString (0, 2*24, " Socket test server "); - GLCD_DrawString (0, 4*24, " ECHO: port 7 "); - GLCD_DrawString (0, 5*24, " CHARGEN: port 19 "); - GLCD_DrawString (0, 6*24, " DISCARD: port 9 "); - - osDelay (100); - - while(1) { - osThreadFlagsWait (0x01, osFlagsWaitAll, osWaitForever); - netIF_GetOption (NET_IF_CLASS_ETH | 0, - netIF_OptionIP4_Address, ip_addr, sizeof(ip_addr)); - netIP_ntoa (NET_ADDR_IP4, ip_addr, ip_ascii, sizeof(ip_ascii)); - sprintf (buf, " IP=%-15s",ip_ascii); - GLCD_DrawString (0, 8*24, buf); - } -} - -#ifdef RTE_CMSIS_RTOS2_RTX5 -/** - * Override default HAL_GetTick function - */ -uint32_t HAL_GetTick (void) { - static uint32_t ticks = 0U; - uint32_t i; - - if (osKernelGetState () == osKernelRunning) { - return ((uint32_t)osKernelGetTickCount ()); - } - - /* If Kernel is not running wait approximately 1 ms then increment - and return auxiliary tick counter value */ - for (i = (SystemCoreClock >> 14U); i > 0U; i--) { - __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); - } - return ++ticks; -} -#endif - -static void SystemClock_Config(void); -static void Error_Handler(void); - -// Application main thread -static void app_main (void *argument) { - - LED_Initialize (); - netInitialize (); - LED_On (0); - osDelay (500); - - osThreadNew(DgramServer, NULL, NULL); - osThreadNew(StreamServer, NULL, NULL); - osThreadNew(TestAssistant, NULL, NULL); - display_id = osThreadNew (DisplayServer, NULL, NULL); - osThreadFlagsSet (display_id, 0x01); -} - -int main(void) { - HAL_Init(); - - /* Configure the system clock to 168 MHz */ - SystemClock_Config(); - SystemCoreClockUpdate(); - - osKernelInitialize (); - osThreadNew(app_main, NULL, NULL); - osKernelStart(); - for (;;) {} -} - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (HSE) - * SYSCLK(Hz) = 168000000 - * HCLK(Hz) = 168000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 4 - * APB2 Prescaler = 2 - * HSE Frequency(Hz) = 8000000 - * PLL_M = 25 - * PLL_N = 336 - * PLL_P = 2 - * PLL_Q = 7 - * VDD(V) = 3.3 - * Main regulator output voltage = Scale1 mode - * Flash Latency(WS) = 5 - * @param None - * @retval None - */ -static void SystemClock_Config(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */ - if (HAL_GetREVID() == 0x1001) - { - /* Enable the Flash prefetch */ - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - } -} -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -static void Error_Handler(void) -{ - /* User may add here some code to deal with this error */ - while(1) - { - } -} - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Tools/SockServer/Embedded/MDK/Include/SockServer.h b/Tools/SockServer/Embedded/MDK/Include/SockServer.h deleted file mode 100644 index 0a1c184..0000000 --- a/Tools/SockServer/Embedded/MDK/Include/SockServer.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: SockServer - * Title: SockServer definitions - * - * ----------------------------------------------------------------------------- - */ - -// Definitions -#define ESC 0x1b // Ascii code for ESC -#define BUFF_SIZE 2000 // Size of buffers (heap: 6000 bytes) - -// Service ports -#define ECHO_PORT 7 // Echo port number -#define DISCARD_PORT 9 // Discard port number -#define CHARGEN_PORT 19 // Chargen port number -#define ASSISTANT_PORT 5000 // Test Assistant port number -#define TCP_REJECTED_PORT 5001 // Rejected connection server TCP port -#define TCP_TIMEOUT_PORT 5002 // Non-responding server TCP port - -#define GET_SYSTICK() osKernelGetSysTimerCount() -#define SYSTICK_MSEC(ms) ((uint64_t)ms * osKernelGetSysTimerFreq() / 1000) - -// Socket Server threads -extern void DgramServer (void *argument); -extern void StreamServer (void *argument); -extern void TestAssistant (void *argument); diff --git a/Tools/SockServer/Embedded/MDK/Source/SockServer.c b/Tools/SockServer/Embedded/MDK/Source/SockServer.c deleted file mode 100644 index bf3311e..0000000 --- a/Tools/SockServer/Embedded/MDK/Source/SockServer.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: SockServer - * Title: SockServer embedded system application - * Purpose: Implements ECHO, DISCARD and CHARGEN services - * - Echo Protocol service [RFC 862] - * - Discard Protocol service [RFC 863] - * - Character Generator Protocol service [RFC 864] - * - * ----------------------------------------------------------------------------- - */ - -#include -#include -#include -#include "rl_net.h" -#include "cmsis_os2.h" -#include "SockServer.h" - -// Global status variables -SOCKADDR_IN remote_addr; // Remote IP address and port -uint32_t rx_cnt; // Receive count -uint32_t tx_cnt; // Transmit count - -// Local functions -static void EchoThread (void *argument); -static void ChargenThread (void *argument); -static void DiscardThread (void *argument); -static char gen_char (char *buf, char setchar, uint32_t len); - -// Generate character array for transmit -static char gen_char (char *buf, char setchar, uint32_t len) { - uint32_t i; - char ch; - - if ((++setchar < 0x21) || (setchar == 0x7f)) { - setchar = 0x21; - } - for (i = 0, ch = setchar; i < (len-2); i++) { - buf[i] = ch; - if (++ch == 0x7f) ch = 0x21; - } - buf[i] = '\n'; - buf[i+1] = '\r'; - return (setchar); -} - -// Datagram server thread -// (runs ECHO and CHARGEN services) -void DgramServer (void *argument) { - SOCKADDR_IN sa; - int32_t sock_echo,sock_chargen; - int32_t nfds,rc,sa_len; - char *buff,setchar; - struct timeval tv; - fd_set fds; - - // Allocate sockets - sock_echo = socket (PF_INET, SOCK_DGRAM, 0); - sock_chargen = socket (PF_INET, SOCK_DGRAM, 0); - - // Bind sockets - sa.sin_family = AF_INET; - sa.sin_addr.s_addr = INADDR_ANY; - - sa.sin_port = htons (ECHO_PORT); - bind (sock_echo, (SOCKADDR *)&sa, sizeof(sa)); - - sa.sin_port = htons (CHARGEN_PORT); - bind (sock_chargen, (SOCKADDR *)&sa, sizeof(sa)); - - setchar = '@'; - buff = malloc (BUFF_SIZE); - - // Receive data - for (;;) { - FD_ZERO(&fds); - FD_SET(sock_echo, &fds); - FD_SET(sock_chargen, &fds); - nfds = (sock_echo > sock_chargen) ? sock_echo : sock_chargen; - tv.tv_sec = 120; - tv.tv_usec = 0; - - // Wait for the packet - select (nfds+1, &fds, 0, 0, &tv); - - if (FD_ISSET(sock_echo, &fds)) { - // Data ready, recvfrom will not block - sa_len = sizeof (sa); - rc = recvfrom (sock_echo, buff, BUFF_SIZE, 0, (SOCKADDR *)&sa, &sa_len); - if (rc > 0) { - rx_cnt += rc; - memcpy (&remote_addr, &sa, sizeof(sa)); - rc = sendto (sock_echo, buff, rc, 0, (SOCKADDR *)&sa, sa_len); - if (rc > 0) tx_cnt += rc; - } - if (rc < 0) { - break; - } - } - if (FD_ISSET(sock_chargen, &fds)) { - // Data ready, recvfrom will not block - sa_len = sizeof (sa); - rc = recvfrom (sock_chargen, buff, BUFF_SIZE, 0, (SOCKADDR *)&sa, &sa_len); - if (rc > 0) { - rx_cnt += rc; - memcpy (&remote_addr, &sa, sizeof(sa)); - int32_t len = rand() >> 22; - if (len < 2) len = 2; - if (len > BUFF_SIZE) len = BUFF_SIZE; - setchar = gen_char (buff, setchar, len); - rc = sendto (sock_chargen, buff, len, 0, (SOCKADDR *)&sa, sa_len); - if (rc > 0) tx_cnt += rc; - } - if (rc < 0) { - break; - } - } - } - free (buff); -} - -// ECHO stream socket handler (2 instances) -static void EchoThread (void *argument) { - int32_t sock = (int32_t)argument; - int32_t rc; - - char *buff = malloc (BUFF_SIZE); - for (; buff;) { - rc = recv (sock, buff, BUFF_SIZE, 0); - if (rc > 0) { - rx_cnt += rc; - rc = send (sock, buff, rc, 0); - if (rc > 0) tx_cnt += rc; - // ESC terminates the thread - if (buff[0] == ESC) break; - } - if (rc < 0) break; - } - closesocket (sock); - free (buff); -} - -// CHARGEN stream socket handler (2 instances) -static void ChargenThread (void *argument) { - int32_t rc,sock = (int32_t)argument; - char buff[82],setchar = '@'; - - for (;;) { - rc = recv (sock, buff, sizeof(buff), MSG_DONTWAIT); - if (rc > 0) rx_cnt += rc; - // ESC terminates the thread - if ((rc > 0) && (buff[0] == ESC)) break; - setchar = gen_char (buff, setchar, 81); - rc = send (sock, buff, 81, 0); - if (rc < 0) break; - else tx_cnt += rc; - osDelay (100); - } - closesocket (sock); -} - -// DISCARD stream socket handler (1 instance) -static void DiscardThread (void *argument) { - int32_t rc,sock = (int32_t)argument; - char buff[40]; - - for (;;) { - rc = recv (sock, buff, sizeof(buff), 0); - if (rc > 0) rx_cnt += rc; - // ESC terminates the thread - if ((rc > 0) && (buff[0] == ESC)) break; - if (rc < 0) break; - } - closesocket (sock); -} - -// Stream server thread -// (runs ECHO, CHARGEN and DISCARD services) -void StreamServer (void *argument) { - SOCKADDR_IN sa; - int32_t sock_echo,sock_chargen,sock_discard,sock_timeout; - int32_t sock,nfds,sa_len; - struct timeval tv; - fd_set fds; - - // Allocate sockets - sock_echo = socket (PF_INET, SOCK_STREAM, 0); - sock_chargen = socket (PF_INET, SOCK_STREAM, 0); - sock_discard = socket (PF_INET, SOCK_STREAM, 0); - sock_timeout = socket (PF_INET, SOCK_STREAM, 0); - - // Bind sockets - sa.sin_family = AF_INET; - sa.sin_addr.s_addr = INADDR_ANY; - - sa.sin_port = htons (ECHO_PORT); - bind (sock_echo, (SOCKADDR *)&sa, sizeof(sa)); - - sa.sin_port = htons (CHARGEN_PORT); - bind (sock_chargen, (SOCKADDR *)&sa, sizeof(sa)); - - sa.sin_port = htons (DISCARD_PORT); - bind (sock_discard, (SOCKADDR *)&sa, sizeof(sa)); - - sa.sin_port = htons (TCP_TIMEOUT_PORT); - bind (sock_timeout, (SOCKADDR *)&sa, sizeof(sa)); - - // Start listening - listen (sock_echo, 2); - listen (sock_chargen, 2); - listen (sock_discard, 1); - listen (sock_timeout, 1); - - for (;;) { - FD_ZERO(&fds); - FD_SET(sock_echo, &fds); - FD_SET(sock_chargen, &fds); - FD_SET(sock_discard, &fds); - - nfds = sock_echo; - if (sock_chargen > nfds) nfds = sock_chargen; - if (sock_discard > nfds) nfds = sock_discard; - - tv.tv_sec = 120; - tv.tv_usec = 0; - - // Wait for the client to connect - select (nfds+1, &fds, 0, 0, &tv); - if (FD_ISSET(sock_echo, &fds)) { - // Connect is pending, accept will not block - sa_len = sizeof(sa); - sock = accept (sock_echo, (SOCKADDR *)&sa, &sa_len); - if (sock >= 0) { - memcpy (&remote_addr, &sa, sa_len); - // Create spawn thread (max.2) - osThreadNew(EchoThread, (void *)sock, NULL); - } - } - if (FD_ISSET(sock_chargen, &fds)) { - // Connect is pending, accept will not block - sa_len = sizeof(sa); - sock = accept (sock_chargen, (SOCKADDR *)&sa, &sa_len); - if (sock >= 0) { - memcpy (&remote_addr, &sa, sa_len); - // Create spawn thread (max.2) - osThreadNew(ChargenThread, (void *)sock, NULL); - } - } - if (FD_ISSET(sock_discard, &fds)) { - // Connect is pending, accept will not block - sa_len = sizeof(sa); - sock = accept (sock_discard, (SOCKADDR *)&sa, &sa_len); - if (sock >= 0) { - memcpy (&remote_addr, &sa, sa_len); - // Create spawn thread (max.1) - osThreadNew(DiscardThread, (void *)sock, NULL); - } - } - osDelay (10); - } -} - -// Test assistant thread -void TestAssistant (void *argument) { - SOCKADDR_IN sa; - int32_t sock,sd,rc,sa_len; - static char buff[1500]; - - while (1) { - // Create socket - sock = socket (PF_INET, SOCK_STREAM, 0); - - // Server mode first - sa.sin_family = AF_INET; - sa.sin_addr.s_addr = INADDR_ANY; - sa.sin_port = htons (ASSISTANT_PORT); - bind (sock, (SOCKADDR *)&sa, sizeof(sa)); - listen (sock, 1); - - while (1) { - // Wait for the client to connect - sa_len = sizeof (sa); - sd = accept (sock, (SOCKADDR *)&sa, &sa_len); - if (sd >= 0) { - // Set blocking receive timeout - uint32_t tout = 2000; - setsockopt (sd, SOL_SOCKET, SO_RCVTIMEO, (char *)&tout, sizeof(tout)); - // Receive the command (tout = 2s) - rc = recv (sd, buff, sizeof(buff), 0); - if (rc > 0) { - buff[rc] = 0; - if ((strncmp (buff, "CONNECT TCP", 11) == 0) || - (strncmp (buff, "CONNECT UDP", 11) == 0) || - (strncmp (buff, "SEND TCP", 8) == 0) || - (strncmp (buff, "RECV TCP", 8) == 0)) { - break; - } - } - closesocket (sd); - osDelay (10); - } - } - closesocket (sock); - - /* Syntax: CONNECT ,,, - Param: = protocol (TCP, UDP) - = IP address (0.0.0.0 = sender address) - = port number - = startup delay - - Example: CONNECT TCP,192.168.1.200,80,600 - (wait 600ms then connect to 192.168.1.200, port 80) - */ - if (buff[0] == 'C') { // CONNECT - uint16_t delay,port; - IN_ADDR da; - - closesocket (sd); - - da.s_addr = INADDR_ANY; - sscanf (buff+11,",%hhu.%hhu.%hhu.%hhu,%hu,%hu", - &da.s_b1, &da.s_b2, &da.s_b3, &da.s_b4, &port, &delay); - if (da.s_addr != INADDR_ANY) { - // Supplied address not 0.0.0.0 use it - sa.sin_addr.s_addr = da.s_addr; - } - sa.sin_port = htons (port); - - // Limit the timeout - if (delay < 10) delay = 10; - if (delay > 5000) delay = 6000; - osDelay (delay); - - // Create stream or datagram socket - sock = socket (PF_INET, (buff[8] == 'T') ? SOCK_STREAM : SOCK_DGRAM, 0); - - // Connect to requested address - rc = connect (sock, (SOCKADDR *)&sa, sa_len); - if (rc == 0) { - // Send some text, wait and close - send (sock, "SockServer", 10, 0); - osDelay (500); - } - closesocket (sock); - osDelay (10); - continue; - } - - /* Syntax: SEND ,, - Param: = protocol (TCP, UDP) - = size of data block in bytes - = test duration in ms - */ - if (buff[0] == 'S') { // SEND - uint32_t bsize,time,ticks; - int32_t i,n,cnt,ch = 'a'; - - // Parse command parameters - sscanf (buff+8,",%u,%u",&bsize,&time); - - // Check limits - if (bsize < 32) bsize = 32; - if (bsize > 1460) bsize = 1460; - if (time < 500) time = 500; - if (time > 60000) time = 60000; - - osDelay (10); - - time = SYSTICK_MSEC(time); - ticks = GET_SYSTICK(); - i = cnt = 0; - do { - n = sprintf (buff,"Block[%d] ",++i); - memset (buff+n, ch, bsize-n); - buff[bsize] = 0; - if (++ch > '~') ch = ' '; - n = send (sd, buff, bsize, 0); - if (n > 0) cnt += n; - } while (GET_SYSTICK() - ticks < time); - - // Inform the client of the number of bytes received - n = sprintf (buff,"STAT %d bytes.",cnt); - send (sd, buff, n, 0); - - // Let the client close the connection - while (recv (sd, buff, sizeof(buff), 0) > 0); - - closesocket (sd); - continue; - } - - /* Syntax: RECV , - Param: = protocol (TCP, UDP) - = size of data block in bytes - */ - if (buff[0] == 'R') { // RECV - uint32_t bsize; - int32_t n,cnt; - - // Parse command parameters - sscanf (buff+8,",%u",&bsize); - - // Check limits - if (bsize < 32) bsize = 32; - if (bsize > 1460) bsize = 1460; - - osDelay (10); - - for (cnt = 0; ; cnt += n) { - n = recv (sd, buff, bsize, 0); - if (strncmp(buff, "STOP", 4) == 0) { - // Client terminated upload - break; - } - if (n <= 0) break; - } - - // Inform the client of the number of bytes received - n = sprintf (buff, "STAT %d bytes.",cnt); - send (sd, buff, n, 0); - - // Let the client close the connection - while (recv (sd, buff, sizeof(buff), 0) > 0); - - closesocket (sd); - continue; - } - } -} diff --git a/Tools/SockServer/Embedded/MDK/Source/Telnet_Server_UIF.c b/Tools/SockServer/Embedded/MDK/Source/Telnet_Server_UIF.c deleted file mode 100644 index b97a90f..0000000 --- a/Tools/SockServer/Embedded/MDK/Source/Telnet_Server_UIF.c +++ /dev/null @@ -1,131 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. - *------------------------------------------------------------------------------ - * Name: Telnet_Server_UIF.c - * Purpose: Telnet Server User Interface - * Rev.: V7.0.0 - *----------------------------------------------------------------------------*/ -//! [code_Telnet_Server_UIF] -#include -#include -#include "rl_net.h" - -// ANSI ESC Sequences for terminal control -#define CLS "\033[2J" - -// Global variables -extern SOCKADDR_IN remote_addr; -extern uint32_t rx_cnt; -extern uint32_t tx_cnt; - -static const char help[] = { - "\r\n" - "Commands:\r\n" - " stat - print Server status\r\n" - " clear - clear RX/TX counters\r\n" - " cls - clear screen\r\n" - " help, ? - display this help\r\n" - " - delete Character left\r\n" - " , - recall Command History\r\n" - " bye,,^C- disconnect" -}; - -// \brief Request a message for a Telnet server session. -// \param[in] msg code of requested message. -// \param[out] buf output buffer to write the message to. -// \param[in] buf_len length of the output buffer in bytes. -// \return number of bytes written to output buffer. -uint32_t netTELNETs_ProcessMessage (netTELNETs_Message msg, char *buf, uint32_t buf_len) { - uint32_t len = 0; - - switch (msg) { - case netTELNETs_MessageWelcome: - // Initial welcome message - len = sprintf (buf, "\r\n" - "*** SockServer ***\r\n" - "%s",help); - break; - - case netTELNETs_MessagePrompt: - // Prompt message - len = sprintf (buf, "\r\n" - "Cmd> "); - break; - - default: - break; - } - return (len); -} - -// \brief Process and execute a command requested by the Telnet client. -// \param[in] cmd pointer to command string from Telnet client. -// \param[out] buf output buffer to write the return message to. -// \param[in] buf_len length of the output buffer in bytes. -// \param[in,out] pvar pointer to a session's local buffer of 4 bytes. -// - 1st call = cleared to 0, -// - 2nd call = not altered by the system, -// - 3rd call = not altered by the system, etc. -// \return number of bytes written to output buffer. -// - return len | (1u<<31) = repeat flag, the system calls this function -// again for the same command. -// - return len | (1u<<30) = disconnect flag, the system disconnects -// the Telnet client. -uint32_t netTELNETs_ProcessCommand (const char *cmd, char *buf, uint32_t buf_len, uint32_t *pvar) { - uint32_t len = 0; - - // Command line parser - if (netTELNETs_CheckCommand (cmd, "STAT") == true) { - // Display SockServer status - if (*pvar == 0) { - // Confirm the command - *pvar = 1; - len = (uint32_t)sprintf (buf, " Ok\r\n\n"); - } - else { - // Update status - len = sprintf (buf, "\r"); - len += sprintf (buf+len, "IP=%s, ", inet_ntoa(remote_addr.sin_addr)); - len += sprintf (buf+len, "port=%u, ", ntohs(remote_addr.sin_port)); - len += sprintf (buf+len, "rx=%u, ", rx_cnt); - len += sprintf (buf+len, "tx=%u", tx_cnt); - } - // Update interval 10 ticks (1 second) - netTELNETs_RepeatCommand (10); - return (len | (1u << 31)); - } - - if (netTELNETs_CheckCommand (cmd, "CLEAR") == true) { - // Clear system counters and IP address - rx_cnt = 0; - tx_cnt = 0; - memset (&remote_addr, 0, sizeof(remote_addr)); - len = (uint32_t)sprintf (buf, " Ok"); - return (len); - } - - if (netTELNETs_CheckCommand (cmd, "CLS") == true) { - // Clear the client screen - len = (uint32_t)sprintf (buf, CLS); - return (len); - } - - if (netTELNETs_CheckCommand (cmd, "BYE") == true) { - // Disconnect the client - len = (uint32_t)sprintf (buf, "\r\nDisconnecting\r\n"); - // Bit-30 of return value is a disconnect flag - return (len | (1u << 30)); - } - - if (netTELNETs_CheckCommand (cmd, "HELP") == true || - netTELNETs_CheckCommand (cmd, "?") == true) { - // Display help text - len = (uint32_t)sprintf (buf, help); - return (len); - } - // Unknown command - len = (uint32_t)sprintf (buf, " <- Unknown Command"); - return (len); -} -//! [code_Telnet_Server_UIF]