diff --git a/ARM.CMSIS-Driver_Validation.pdsc b/ARM.CMSIS-Driver_Validation.pdsc index cb1ead8..51fddeb 100644 --- a/ARM.CMSIS-Driver_Validation.pdsc +++ b/ARM.CMSIS-Driver_Validation.pdsc @@ -10,6 +10,9 @@ Active Development ... + - Add SPI Server application template + - Update SPI Server application to CMSIS solution format + - Remove old SPI Server files - Add GPIO Driver validation - Remove XML report format - Improve Ethernet driver validation @@ -272,6 +275,21 @@ + + CMSIS-Driver Validation SPI Server application for STM32F429I-DISC1 board + + + + + + + + CMSIS-Driver Validation SPI Server application + + + + + CMSIS-Driver Validation Example diff --git a/Documentation/Doxygen/src/DV_SPI.txt b/Documentation/Doxygen/src/DV_SPI.txt index 273a746..de91930 100644 --- a/Documentation/Doxygen/src/DV_SPI.txt +++ b/Documentation/Doxygen/src/DV_SPI.txt @@ -1,227 +1,174 @@ -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/*====================================================================================================*/ /** \defgroup spi_config Configuration \ingroup dv_spi -The SPI driver validation settings are available in the DV_SPI_Config.h configuration file. +The SPI driver validation settings are defined in the **DV_SPI_Config.h** configuration file. \image html dv_spi_config_h.png "DV_SPI_Config.h configuration file in Configuration Wizard view mode" -Some settings depend on the test environment and need to be changed for proper operation of the SPI driver validation.
+Some settings depend on the test environment and may require adjustment to ensure proper operation of the SPI +Driver Validation suite. \section spi_config_detail Configuration settings -Driver_SPI# selects the driver instance that will be tested.
-For example if we want to test Driver_SPI2 then this setting would be set to 2. - -Configuration section contains configuration of: Test Mode, SPI Server and Tests settings: -- Test Mode can be set to Loopback or SPI Server.
- Loopback mode should be used for initial validation.
- Loopback mode requires that MOSI and MISO pins are connected together thus driver validation can test basic - functionality in the Master mode.
- For full compliance of the SPI driver with the CMSIS-Driver SPI specification the SPI Server Test Mode has to be used. -- SPI Server settings are relevant if Test Mode: SPI Server is selected.
- These settings specify communication settings at which Driver Validation communicates with the SPI Server
- and must be same as configured on the SPI Server. - - Some settings are fixed and cannot be changed, these are the following ones: - - Clock / Frame Format: Clock Polarity 0/ Clock Phase 0 - - Data Bits: 8 - - Bit Order: MSB to LSB - - Settings configurable for the SPI Server are: - - Slave Select setting specifies the way that Slave Select line will be handled by the driver under test.
- SPI Server requires that commands are exchanged with Slave Select line used, so driver being tested must support - Slave Select line handling.
- Software Controlled selection means that driver will use software controlled driving of the Slave Select line by - calling driver Control function with ARM_SPI_CONTROL_SS control code to activate Slave Select Line - before the transfer and deactivate it after the transfer.
- Hardware Controlled selection means that driver will use hardware controlled driving of the Slave Select line. - - Bus Speed setting specifies the nominal bus speed used to exchange commands with the SPI Server.
- This setting should be set to a speed guaranteeing reliable command exchange with the SPI Server. -- Tests settings specify tests configuration: - - Default settings specifies the default settings used in the data exchange tests.
- Usually, one feature is tested by executing the data exchange while all other parameters are used as default.
- For details on which parameters are used as default in each test function please refer to \ref spi_tests_data_xchg - functions documentation. - - Bus Speed settings specifies minimum and maximum bus speeds at which data transfer will be executed.
- These settings are used by the \ref SPI_Bus_Speed_Min and \ref SPI_Bus_Speed_Max test functions. - - Number of Items settings specifies a few different number of items to be tested.
- These settings are used by the \ref SPI_Number_Of_Items test function which tests that odd and unusual number of items - are transferred correctly according to the CMSIS-Driver specification. - -Tests section contains selection of tests to be executed: -- Driver Management allows enabling or disabling of the whole driver management group of test functions.
- Each test function in this group can be enabled or disabled individually, for details on tests performed - by each test function please refer to \ref spi_tests_drv_mgmt documentation. -- Data Exchange allows enabling or disabling of the whole data exchange group of test functions.
- Each test function in this group can be enabled or disabled individually, for details on tests performed - by each test function please refer to \ref spi_tests_data_xchg documentation. -- Event allows enabling or disabling of the whole event group of test functions.
- Each test function in this group can be enabled or disabled individually, for details on tests performed - by each test function please refer to \ref spi_tests_evt documentation. -*/ +**Driver_SPI#** selects the driver instance to be tested. +Example: to test `Driver_SPI2`, set this value to `2`. + +**Configuration** contains settings for **Test Mode**, **SPI Server**, and **Tests**: + +- **Test Mode**: **Loopback** or **SPI Server**. + - *Loopback* is recommended for initial validation of **Master** functionality. It requires MOSI and MISO to be + connected together to verify basic operation. + - For *full* CMSIS-Driver SPI compliance, use **SPI Server** mode. + +- **SPI Server** (applies only when *Test Mode: SPI Server* is selected): + Defines communication settings between Driver Validation and the SPI Server and **must match** the Server. + - Fixed parameters: + - **Clock/Frame:** CPOL=0, CPHA=0 + - **Data Bits:** 8 + - **Bit Order:** MSB → LSB + - Configurable parameters: + - **Slave Select** — **Software Controlled** (driver toggles SS using `ARM_SPI_CONTROL_SS`) or **Hardware Controlled**. + - **Bus Speed** — nominal bus speed for reliable command exchange with the Server. + +- **Tests**: configuration for test execution. + - **Default settings** — defaults for data exchange tests (see \ref spi_tests_data_xchg). + - **Bus Speed** — minimum/maximum speeds used by \ref SPI_Bus_Speed_Min and \ref SPI_Bus_Speed_Max. + - **Number of Items** — item counts (including odd/unusual) used by \ref SPI_Number_Of_Items to verify conformance. + +**Tests** section — enable/disable test groups (and individual tests): +- **Driver Management** — see \ref spi_tests_drv_mgmt. +- **Data Exchange** — see \ref spi_tests_data_xchg. +- **Event** — see \ref spi_tests_evt. +*/ -/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ +/*====================================================================================================*/ /** \defgroup spi_server SPI Server \ingroup dv_spi -The SPI Server is an application providing a set of features used by the CMSIS-Driver Validation suite to test the -physical operation of the SPI driver.
-It is located in the \\\Tools\\SPI_Server directory. +The **SPI Server** application provides features used by the CMSIS-Driver Validation suite to test physical operation of +the SPI driver. -The SPI Server offers the following features: -- read of the version information -- read of the capabilities information -- set and read of the data buffers content -- read of the last transfer count -- transfer in Slave or Master mode +It is available for the STMicroelectronics **STM32F429I-DISC1** board and as a template for **any board** +with available **Board Layer** and configured **CMSIS compliant SPI driver**. -\section spi_server_oper Operation +\note STM32F429I-DISC1 was selected because its SPI driver is stable and supports all required features. +\note For running on STM32F429I-DISC1 board, see \ref spi_server_disc1. +\note For running on other hardware, see \ref spi_server_template. -The SPI Server is continuously waiting on a command from the SPI Client (Driver Validation), -after the command is received it is executed, and the process repeats.
-Most commands do not have any additional related data phase, but some do have additional input or output -data exchange phase following the command. +\section spi_server_features Features +- Read **version** information +- Read **capabilities** information (auto-detected) +- Set and read **buffer** contents +- Read last **transfer count** +- Execute **transfer** in **Slave** or **Master** mode -The SPI Server behaves as an SPI Slave except when command for Master transfer was requested, in which case it -executes the requested Master transfer and reverts to Slave mode. +\section spi_server_oper Operation +The Server waits for a command from the SPI Client (Driver Validation), executes it, and then waits for the next one. +Most commands have no additional data phase, though some do. The Server operates as an SPI **Slave** except when a **Master** +transfer is explicitly requested; after completing it, the Server returns to **Slave** mode. \section spi_server_config Configuration - -Communication interface settings used during command exchange are set in the SPI_Server_Config.h configuration file. +Communication settings are defined in **SPI_Server_Config.h** file. \image html spi_server_config_h.png "SPI_Server_Config.h configuration file in Configuration Wizard view mode" \subsection spi_server_config_detail Configuration settings -Driver_SPI# selects the driver instance used by the SPI Server.
-Communication settings used for command exchange with the SPI Client are fixed to: - - Mode: Slave with Slave Select Hardware monitored - - Clock / Frame Format: Clock Polarity 0/ Clock Phase 0 - - Data Bits: 8 - - Bit Order: MSB to LSB +- **Driver_SPI#** — selects the driver instance used by the Server. +- **Communication settings** (fixed for command exchange): + - **Mode:** Slave with **hardware-monitored Slave Select** + - **Clock/Frame:** Clock Polarity 0/ Clock Phase 0 + - **Data Bits:** 8 + - **Bit Order:** MSB to LSB -\note The SPI Server is receiving commands operating in SPI Slave mode with usage of the Slave Select line -\note The SPI driver used by the SPI Server must support Hardware monitored Slave Select functionality +\note The SPI Server receives commands as an SPI **Slave** using the **Slave Select** line. The Server’s SPI driver **must +support hardware-monitored Slave Select** functionality. \section spi_server_commands Commands - -Commands are encoded in human readable format (ASCII strings) so they can be viewed by the SPI bus analyzer -and analyzed more easily. - -Supported commands: - - GET VER: used to retrieve version of the SPI Server application - - GET CAP: used to retrieve capabilities of the SPI Server - (the Server auto-detects capabilities upon reception of this command) - - SET BUF: used to initialize receive or transmit buffer content of the SPI Server - - GET BUF: used to retrieve receive or transmit buffer content of the SPI Server - - SET COM: used to specify transfer configuration for the next transfer - - XFER: used to trigger a transfer - - GET CNT: used to retrieve number of transferred items in the last transfer - -\note For details about commands please refer to Abstract.txt file in the -\\\Tools\\SPI_Server\\Board\\MCBSTM32F400 directory. - -Picture below shows a capture of SPI Driver Validation validating functionality of the Master transfer with Slave Select -line not used \image html spi_bus_master_ss_hw_ctrl_out.png - -\section spi_server_porting Porting SPI Server to other targets - -To create SPI Server application for a different target device, follow the steps below: --# Create a new project in µVision for your target device --# In the RTE window enable and configure the following software components: - - CMSIS: CORE - - CMSIS: RTOS2 (API): Keil RTX5 any variant - - CMSIS Driver: SPI (API) - - CMSIS Driver: VIO (API) select Virtual implementation if implementation for your target system is not available - - Generic device specific components (startup, clock system, I/O, ...) as required - (please consult device's documentation for more information) - - Resolve any unresolved dependencies between components --# Copy the SPI_Server.c file from the \\\Tools\\SPI_Server\\Source directory - to the project root and add it to µVision project --# Copy the SPI_Server.h file from the \\\Tools\\SPI_Server\\Include - directory to the project root --# Copy the SPI_Server_Config.h file from the \\\Tools\\SPI_Server\\Config - directory to the project root and adapt this file as required by your device --# Add root of the project to include path (Options for Target -> C/C++ -> Include Paths: .\\) --# Add the main.c file from a template - (Right-click Source Group 1... and select Add New Item to Group, select User Code Template and choose the - CMSIS-RTOS2 'main' function file from CMSIS: RTOS2:Keil RTX5) - and update with code snippet below (replace app_main function): -\code -#include "SPI_Server.h" - -/*---------------------------------------------------------------------------- - * Application main thread - *---------------------------------------------------------------------------*/ -__NO_RETURN static void app_main (void *argument) { - (void)argument; - SPI_Server_Start(); - for (;;) {} -} -\endcode --# Ensure that system has at least 10kB of heap available for the transfer buffers - (this is usually set in the startup file of the device) --# Build and download the ported SPI Server application to the target device +Commands are human-readable (ASCII) for simpler analysis with an SPI bus analyzer. + +- **GET VER** — get Server version +- **GET CAP** — get capabilities (auto-detected) +- **SET BUF** — initialize Rx/Tx buffer content +- **GET BUF** — retrieve Rx/Tx buffer content +- **SET COM** — specify transfer configuration for the next **XFER** +- **XFER** — trigger a transfer +- **GET CNT** — retrieve number of transferred items in the last transfer + +\note For detailed command descriptions, see **README.md** in project root. + +Example capture (Master transfer validation): +\image html spi_bus_master_ss_hw_ctrl_out.png width=100% + +\section spi_server_disc1 Running on STM32F429I-DISC1 board + +Using the [Arm CMSIS Solution](https://marketplace.visualstudio.com/items?itemName=Arm.cmsis-csolution) VS Code extension, +create a new solution from **example**: + +1. In the **CMSIS** extension, click **Create a New Solution**. + \image html server_new_sol_create.png +2. Select an **STM32F429I-DISC1 board** as a **Target Board**. +3. Under **Templates, Reference Applications, and Examples**, + select **SPI Server (CMSIS-Driver Validation SPI Server application for STM32F429I-DISC1 board)**. + \image html spi_server_new_sol_disc1_example.png +4. Choose **Solution Base Folder** and click **Create**. + \image html spi_server_new_sol_disc1_create.png +5. Build and run the **SPI Server application** on the **STM32F429I-DISC1 board**. + +SPI1 pinout (STM32F429I-DISC1): +| SPI function | Pin | +| :------------------------------- | :--: | +| SPI Clock | PA5 | +| Master Output Slave Input (MOSI) | PA7 | +| Master Input Slave Output (MISO) | PB4 | +| Slave Select | PA15 | + +\note **IMPORTANT:** Connect **ground between** the **SPI Server** and the **Device (Driver) Under Test** to ensure a common +reference potential. +\note The STM32F429I-DISC1 SPI Server does **not** support National Semiconductor **Microwire** frame format. +\note The STM32F429I-DISC1 SPI Server for **build-type: Debug** displays command execution on an on-board LCD. + +\section spi_server_template Running on specific hardware +Using the [Arm CMSIS Solution](https://marketplace.visualstudio.com/items?itemName=Arm.cmsis-csolution) VS Code extension, +create a new solution from **template**: + +1. In the **CMSIS** extension, click **Create a New Solution**. + \image html server_new_sol_create.png +2. Select the **Target Board**. +3. Under **Templates, Reference Applications, and Examples**, + select **SPI Server (CMSIS-Driver Validation SPI Server application)**. + \image html spi_server_new_sol_template.png +4. Choose **Solution Base Folder**, click **Create**. + \image html spi_server_new_sol_create.png +5. Select the board layer that provides an SPI Driver. + \image html server_new_sol_layer.png +6. If SPI is not routed to ARDUINO (or a different SPI peripheral is required), + open **SPI_Server_Config.h**, **Open Preview** and edit **Driver_SPI#** to + the required instance. +7. Build and run the **SPI Server application** on your hardware. + +\note **IMPORTANT:** The target board’s SPI CMSIS-Driver must be **fully CMSIS compliant**! +\note The SPI Server for **build-type: Debug** displays command execution on an STDOUT channel (typically Virtual COM port via Debug adapter). \section spi_server_troubleshooting Troubleshooting -Problems and solutions: - 1. SPI Server is not responding to commands - - reset the SPI Server - - check that correct driver instance is selected in the SPI_Server_Config.h file - - reduce bus speed used for communication with the SPI Server (in the DV_SPI_Config.h file) - 2. SPI Server is not responding to commands it reports "Server Start failed!" message - if debug variant is used - - check heap settings - (it has to be larger than 2 * SPI_SERVER_BUF_SIZE specified in the SPI_Server_Config.h file) - - check that RTOS allows allocation of at least 512 bytes for the SPI Server main thread - (Global Dynamic Memory size [bytes] setting in RTX_Config.h file if RTX5 is used) - 3. tests report data mismatch - - check that Slave Select line has a pull-up to Vcc line - - check that wires are separate and short as possible - - insure if possible that SCK and GND wires are a twisted pair - - insure that SPI driver in inactive mode does not drive Slave Select line - -\section spi_server_MCBSTM32F400 SPI Server on the Keil MCBSTM32F400 board - -µVision project and source files for the MCBSTM32F400 board are available in the \\\Tools\\SPI_Server\\Board\\MCBSTM32F400 directory. - -On the Keil MCBSTM32F400 board the SPI2 interface is used, with the following pinout: - -| SPI function | Pin | -| :------------------------------- | :----: | -| SPI Clock | PB10 | -| Master Output Slave Input (MOSI) | PB15 | -| Master Input Slave Output (MISO) | PB14 | -| Slave Select | PI0 | - -\note IMPORTANT: Ground must be connected between SPI Server and Device (Driver) Under Test -so that SPI signals have same ground potential. - -For more information please consult Abstract.txt file in the project root. - -\note SPI Server on the Keil MCBSTM32F400 does not support National Semiconductor Microwire Frame Format. - - -\section spi_server_STM32F429I_DISC1 SPI Server on the STMicroelectronics STM32F429I-DISC1 (32F429IDISCOVERY) board - -µVision project and source files for the STM32F429I-DISC1 board are available in the \\\Tools\\SPI_Server\\Board\\STM32F429I-DISC1 directory. - -On the STMicroelectronics STM32F429I-DISC1 board the SPI1 interface is used, with the following pinout: - -| SPI function | Pin | -| :------------------------------- | :----: | -| SPI Clock | PA5 | -| Master Output Slave Input (MOSI) | PA7 | -| Master Input Slave Output (MISO) | PB4 | -| Slave Select | PA15 | - -\note IMPORTANT: Ground must be connected between SPI Server and Device (Driver) Under Test -so that SPI signals have same ground potential. +1. **Server not responding** + - Reset the Server. + - Verify the correct driver instance in `SPI_Server_Config.h`. + - Reduce bus speed used for communication with the Server (in `DV_SPI_Config.h`). -For more information please consult Abstract.txt file in the project root. +2. Debug message **“Server Start failed!”** (build-type: Debug) + - Check heap (must be > `2 * SPI_SERVER_BUF_SIZE`). + - Verify RTOS allows ≥ **512 bytes** allocation for the Server main thread (e.g., *Global Dynamic Memory size* in `RTX_Config.h` if RTX5). + - Ensure the Server’s SPI driver supports all fixed settings (Slave with hardware-monitored Slave Select, CPOL=0/CPHA=0, 8 bits, MSB to LSB). -\note SPI Server on the STMicroelectronics STM32F429I-DISC1 does not support National Semiconductor Microwire Frame Format. +3. **Tests report data mismatch** + - Ensure Slave Select line has a pull-up to Vcc (3.3 V). + - Keep **wires short and separate**; pair SCK and GND if possible. + - Ensure the SPI driver does not drive Slave Select line while inactive. */ +/*====================================================================================================*/ diff --git a/Documentation/Doxygen/src/images/server_new_sol_create.png b/Documentation/Doxygen/src/images/server_new_sol_create.png new file mode 100644 index 0000000..7f2ecde Binary files /dev/null and b/Documentation/Doxygen/src/images/server_new_sol_create.png differ diff --git a/Documentation/Doxygen/src/images/server_new_sol_layer.png b/Documentation/Doxygen/src/images/server_new_sol_layer.png new file mode 100644 index 0000000..45a77fb Binary files /dev/null and b/Documentation/Doxygen/src/images/server_new_sol_layer.png differ diff --git a/Documentation/Doxygen/src/images/spi_server_config.png b/Documentation/Doxygen/src/images/spi_server_config.png new file mode 100644 index 0000000..346d8b8 Binary files /dev/null and b/Documentation/Doxygen/src/images/spi_server_config.png differ diff --git a/Documentation/Doxygen/src/images/spi_server_new_sol_create.png b/Documentation/Doxygen/src/images/spi_server_new_sol_create.png new file mode 100644 index 0000000..21e8aa4 Binary files /dev/null and b/Documentation/Doxygen/src/images/spi_server_new_sol_create.png differ diff --git a/Documentation/Doxygen/src/images/spi_server_new_sol_disc1_create.png b/Documentation/Doxygen/src/images/spi_server_new_sol_disc1_create.png new file mode 100644 index 0000000..91d9394 Binary files /dev/null and b/Documentation/Doxygen/src/images/spi_server_new_sol_disc1_create.png differ diff --git a/Documentation/Doxygen/src/images/spi_server_new_sol_disc1_example.png b/Documentation/Doxygen/src/images/spi_server_new_sol_disc1_example.png new file mode 100644 index 0000000..6f078fe Binary files /dev/null and b/Documentation/Doxygen/src/images/spi_server_new_sol_disc1_example.png differ diff --git a/Documentation/Doxygen/src/images/spi_server_new_sol_template.png b/Documentation/Doxygen/src/images/spi_server_new_sol_template.png new file mode 100644 index 0000000..d2fcbd0 Binary files /dev/null and b/Documentation/Doxygen/src/images/spi_server_new_sol_template.png differ diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/Abstract.txt b/Tools/SPI_Server/Board/MCBSTM32F400/Abstract.txt deleted file mode 100644 index 61ab7b9..0000000 --- a/Tools/SPI_Server/Board/MCBSTM32F400/Abstract.txt +++ /dev/null @@ -1,115 +0,0 @@ -This is an SPI Server application for the Keil MCBSTM32F400 evaluation board. -The application executes commands sent from the SPI Client over the -SPI interface and is used to physically test compliance of the SPI driver -with the CMSIS SPI driver specification from version 2.0.0 upwards. - -Operation: -The SPI Server (in Slave mode) waits to receive a command over the SPI interface. -After command is received it is executed, and SPI Server again waits to receive -next command. -Command execution finishes by finishing the requested operation or by timeout. -All commands except XFER use fixed communication configuration, and timeout as -specified in the SPI_Server_Config.h configuration file. -Only XFER command is executed using settings configured by SET COM command, -after execution of the XFER command the SPI interface is configured back to -fixed configuration, so next command can be received. -The XFER command is executed until it finishes or until timeout specified in -the command expires. -If timeout is not specified in the command the last specified timeout from -previous XFER command is used. -If timeout was never specified in the XFER command then default timeout setting -is used. - -Fixed SPI interface configuration: - - Mode: Slave mode with Slave Select Hardware monitored - - Clock / Frame Format: Clock Polarity 0, Clock Phase 0 - - Data Bits: 8 - - Bit Order: MSB to LSB - -Hardware configuration of the SPI Server (peripheral SPI2 is used): - Function: Pin: - SCLK PB10 - MOSI PB15 - MISO PB14 - SS PI0 (with external pull-up to Vcc) - GND any ground connection on the board - -SPI Server commands (32 bytes long (zero padding), [] means parameter is optional): - - GET VER <- followed by 16 bytes OUT data phase - - GET CAP <- followed by 32 bytes OUT data phase - - SET BUF RX/TX,len[,pattern] -> followed by optional 'len' bytes IN data phase - - GET BUF RX/TX,len <- followed by 'len' bytes OUT data phase - - SET COM mode,format,bit_num,bit_order,ss_mode,bus_speed - - XFER num[,delay_c][,delay_t][,timeout] <-> followed by 'num' items data IN/OUT transfer - - GET CNT <- followed by 16 bytes OUT data phase - -SPI Server command parameters: - RX/TX: RX = SPI Server's receive buffer, TX = SPI Server's transmit buffer - len: length of content in the following IN/OUT data phase - pattern: value (in hex notation) to pre-fill the buffer with - mode: 0 = Master, 1 = Slave - format: 0 = Clock Polarity 0, Clock Phase 0 - 1 = Clock Polarity 0, Clock Phase 1 - 2 = Clock Polarity 1, Clock Phase 0 - 3 = Clock Polarity 1, Clock Phase 1 - 4 = Texas Instruments Frame Format - 5 = National Semiconductor Microwire Frame Format - bit_num: number of bits (1 .. 32) - bit_order: 0 = MSB to LSB, 1 = LSB to MSB - ss_mode: 0 = unused, 1 = Master driven / Slave monitored - bus_speed: bus speed (in bps) - num: number of items (according CMSIS SPI driver specification) - delay_c: delay before Control function is called, in milliseconds - delay_t: delay after Control function is called but before Transfer function is called, in milliseconds - timeout: total transfer timeout including delay_c and delay_t delays, in milliseconds - -SPI Server responses to commands: - - GET VER: 16 bytes containing string representation in form: - "major.minor.patch" - - GET CAP: 32 bytes containing values representing masks (bit value 1 means supported) or values as follows: - "mode_mask,format_mask,data_bit_mask,bit_order_mask,min_bus_speed_in_kbps,max_bus_speed_in_kbps" - - mode_mask (2 digits in hex): specifies mask of supported modes - - bit 0.: Master - - bit 1.: Slave - - format_mask (2 digits in hex): specifies mask of supported clock/frame formats - - bit 0.: Clock Polarity 0, Clock Phase 0 - - bit 1.: Clock Polarity 0, Clock Phase 1 - - bit 2.: Clock Polarity 1, Clock Phase 0 - - bit 3.: Clock Polarity 1, Clock Phase 1 - - bit 4.: Texas Instruments Frame Format - - bit 5.: National Semiconductor Microwire Frame Format - - data_bit_mask (8 digits in hex): specifies mask of supported data bits - - bit 0.: Data Bits 1 - ... - - bit 31.: Data Bits 32 - - bit_order_mask (1 byte in hex): specifies mask of supported bit orders - - bit 0.: MSB to LSB - - bit 1.: LSB to MSB - - min_bus_speed_in_kbps (dec): minimum supported bus speed (in kbps) - - max_bus_speed_in_kbps (dec): maximum supported bus speed (in kbps) - - GET BUF: 'len' bytes from respective buffer, in binary format - - GET CNT: 16 bytes containing value in decimal notation - -The SPI Server for the Keil MCBSTM32F400 board is available for different targets: - - Release: target with high optimization and no User Interface - - Debug: target with low optimization and User Interface (GLCD, LED) - -Command examples: - Get version: - -> GET VER <- 16 bytes (for example "1.1.0") - Get capabilities: - -> GET CAP <- 32 bytes (for example "03,1F,00008080,03,1000,10000") - Set Tx buffer to 'S': - -> SET BUF TX,0,53 - Set Rx buffer to '?': - -> SET BUF RX,0,3F - Get 16 bytes of Rx buffer content: - -> GET BUF RX,16 <- 16 bytes (for example "????????????????") - Set communication mode to slave, clock phase 0, clock polarity 0, - 8 data bits, MSB first, slave select hardware monitored, 2MBps: - -> SET COM 1,0,8,0,1,2000000 - Transfer 16 bytes in both directions: - -> XFER 16,10,0,100 <-> 16 bytes - Get count: - -> GET CNT <- 16 bytes (for example "16") - diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/Config/SPI_Server_Config.h b/Tools/SPI_Server/Board/MCBSTM32F400/Config/SPI_Server_Config.h deleted file mode 100644 index 1a3c686..0000000 --- a/Tools/SPI_Server/Board/MCBSTM32F400/Config/SPI_Server_Config.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: SPI Server - * Title: SPI Server configuration file - * - * ----------------------------------------------------------------------------- - */ - -#ifndef SPI_SERVER_CONFIG_H_ -#define SPI_SERVER_CONFIG_H_ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// SPI Server -// SPI Server configuration. -// Fixed settings used by the SPI Server for command exchange are: -// Mode: Slave with Slave Select Hardware monitored -// Clock / Frame Format: Clock Polarity 0, Clock Phase 0 -// Data Bits: 8 -// Bit Order: MSB to LSB -// Driver_SPI# <0-255> -// Choose the Driver_SPI# instance. -// For example to use Driver_SPI0 select 0. -// - -#define SPI_SERVER_DRV_NUM 2 -#define SPI_SERVER_BUF_SIZE 4096 -#define SPI_SERVER_CMD_TIMEOUT 100 - -#endif diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/SPI_Server.uvguix b/Tools/SPI_Server/Board/MCBSTM32F400/SPI_Server.uvguix deleted file mode 100644 index ee9564c..0000000 --- a/Tools/SPI_Server/Board/MCBSTM32F400/SPI_Server.uvguix +++ /dev/null @@ -1,3628 +0,0 @@ - - - - -6.1 - -
### uVision Project, (C) Keil Software
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* Copyright (c) 2020 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1.Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2.Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3.Neither the name of Arm nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *------------------------------------------------------------------------------ - * Name: main.c - * Purpose: Main module - *----------------------------------------------------------------------------*/ - -#include "main.h" - -#include -#include - -#include "SPI_Server_Config.h" -#include "SPI_Server.h" - -#include "stm32f4xx_hal.h" - -// Local functions -static void SystemClock_Config(void); -static void Error_Handler(void); - - -// Main function -int32_t main (void) { - - // Hardware Abstraction Layer (HAL) initialization - (void)HAL_Init(); - - // System initialization - SystemClock_Config(); - SystemCoreClockUpdate(); - - // Initialize kernel, create threads and start kernel - (void)osKernelInitialize(); - (void)SPI_Server_Start(); - (void)osKernelStart(); - - for (;;) {} -} - - -#ifdef RTE_CMSIS_RTOS2_RTX5 -/** - * Override default HAL_GetTick function - */ -uint32_t HAL_GetTick (void) { - static uint32_t ticks = 0U; - uint32_t i, ret; - - if (osKernelGetState () == osKernelRunning) { - ret = (uint32_t)osKernelGetTickCount (); - } else { - /* If Kernel is not running wait approximately 1 ms then increment - and return auxiliary tick counter value */ - for (i = (SystemCoreClock >> 14U); i > 0U; i--) { - __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); - } - ticks = ticks + 1U; - ret = ticks; - } - - return ret; -} -#endif - - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (HSE) - * SYSCLK(Hz) = 168000000 - * HCLK(Hz) = 168000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 4 - * APB2 Prescaler = 2 - * HSE Frequency(Hz) = 8000000 - * PLL_M = 25 - * PLL_N = 336 - * PLL_P = 2 - * PLL_Q = 7 - * VDD(V) = 3.3 - * Main regulator output voltage = Scale1 mode - * Flash Latency(WS) = 5 - * @param None - * @retval None - */ -static void SystemClock_Config(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable Power Control clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value - regarding system frequency refer to product datasheet. */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25U; - RCC_OscInitStruct.PLL.PLLN = 336U; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 7U; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - /* Initialization Error */ - Error_Handler(); - } - - /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */ - if (HAL_GetREVID() == 0x1001) - { - /* Enable the Flash prefetch */ - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - } -} - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -static __NO_RETURN void Error_Handler(void) -{ - /* User may add here some code to deal with this error */ - for (;;) - { - } -} - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} - -#endif - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/vio_MCBSTM32F400.c b/Tools/SPI_Server/Board/MCBSTM32F400/vio_MCBSTM32F400.c deleted file mode 100644 index d753f2b..0000000 --- a/Tools/SPI_Server/Board/MCBSTM32F400/vio_MCBSTM32F400.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ----------------------------------------------------------------------------- - * - * Project: SPI Server - * Title: Virtual I/O (VIO) implementation for - * Keil MCBSTM32F400 evaluation board - * - * ----------------------------------------------------------------------------- - */ - -#include -#include -#include -#include "cmsis_os2.h" -#include "cmsis_compiler.h" -#include "cmsis_vio.h" - -#if !defined(CMSIS_VOUT) -#include "Board_LED.h" // ::Board Support:LED -#include "Board_GLCD.h" // ::Board Support:Graphic LCD -#include "GLCD_Config.h" - -extern GLCD_FONT GLCD_Font_6x8; -extern GLCD_FONT GLCD_Font_16x24; -#endif -#if !defined(CMSIS_VIN) -#include "Board_Buttons.h" // ::Board Support:Buttons -#endif - -// VIO input, output definitions -#define VIO_PRINT_MAX_SIZE 64U // maximum size of print memory -#define VIO_PRINT_MEM_NUM 4U // number of print memories -#define VIO_VALUE_NUM 3U // number of values -#define VIO_VALUE_XYZ_NUM 3U // number of XYZ values -#define VIO_IPV4_ADDRESS_NUM 2U // number of IPv4 addresses -#define VIO_IPV6_ADDRESS_NUM 2U // number of IPv6 addresses - -// VIO input, output variables -__USED uint32_t vioSignalIn; -__USED uint32_t vioSignalOut; -__USED char vioPrintMem[VIO_PRINT_MEM_NUM][VIO_PRINT_MAX_SIZE]; -__USED int32_t vioValue [VIO_VALUE_NUM]; -__USED vioValueXYZ_t vioValueXYZ[VIO_VALUE_XYZ_NUM]; -__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM]; -__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM]; - -static uint32_t cursor_x; // GLCD cursor x (horizontal) position (in pixels) -static uint32_t cursor_y; // GLCD cursor y (vertical) position (in pixels) -static osMutexId_t mid_GLCD; // Mutex ID of GLCD mutex - -// Initialize test input, output. -void vioInit (void) { - - vioSignalIn = 0U; - vioSignalOut = 0U; - - memset (vioPrintMem, 0, sizeof(vioPrintMem)); - memset (vioValue, 0, sizeof(vioValue)); - memset (vioValueXYZ, 0, sizeof(vioValueXYZ)); - memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4)); - memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6)); - -#if !defined(CMSIS_VOUT) - (void)LED_Initialize(); - - mid_GLCD = osMutexNew(NULL); // Create GLCD mutex - if (mid_GLCD != NULL) { - (void)GLCD_Initialize(); - (void)GLCD_SetBackgroundColor(GLCD_COLOR_BLUE); - (void)GLCD_SetForegroundColor(GLCD_COLOR_WHITE); - (void)GLCD_ClearScreen(); - } -#endif - -#if !defined(CMSIS_VIN) - (void)Buttons_Initialize(); -#endif -} - -// Print formated string to test terminal. -int32_t vioPrint (uint32_t level, const char *format, ...) { - va_list args; - int32_t ret; - -#if !defined(CMSIS_VOUT) - uint16_t cursor_x, cursor_y; // GLCD cursor position (in pixels) - uint8_t font_w, font_h; - uint8_t i; - char ch; -#endif - - if (level > vioLevelError) { - return (-1); - } - - if (level > VIO_PRINT_MEM_NUM) { - return (-1); - } - - va_start(args, format); - - ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args); - - va_end(args); - -#if !defined(CMSIS_VOUT) - if (mid_GLCD != NULL) { - osMutexAcquire(mid_GLCD, osWaitForever); - switch (level) { - case vioLevelNone: // Normal text - font_w = GLCD_Font_6x8.width; - font_h = GLCD_Font_6x8.height; - cursor_x = 0U; // Normal text starting position - cursor_y = 0U; // 1st text row - (void)GLCD_SetFont (&GLCD_Font_6x8); - (void)GLCD_SetForegroundColor (GLCD_COLOR_WHITE); - break; - case vioLevelHeading: // Heading text - font_w = GLCD_Font_16x24.width; - font_h = GLCD_Font_16x24.height; - cursor_x = 0U; // Heading text starting position - cursor_y = font_h; // 2nd text row - (void)GLCD_SetFont (&GLCD_Font_16x24); - (void)GLCD_SetForegroundColor (GLCD_COLOR_GREEN); - break; - case vioLevelMessage: // Message text - font_w = GLCD_Font_16x24.width; - font_h = GLCD_Font_16x24.height; - cursor_x = 0U; // Message text starting position - cursor_y = font_h * 5U; // 6th text row - (void)GLCD_SetFont (&GLCD_Font_16x24); - (void)GLCD_SetForegroundColor (GLCD_COLOR_WHITE); - break; - case vioLevelError: // Error text - font_w = GLCD_Font_16x24.width; - font_h = GLCD_Font_16x24.height; - cursor_x = 0U; // Error text starting position - cursor_y = font_h * 9U; // 10th text row - (void)GLCD_SetFont (&GLCD_Font_16x24); - (void)GLCD_SetForegroundColor (GLCD_COLOR_RED); - break; - } - - i = 0U; - while (vioPrintMem[level][i] != 0) { - ch = vioPrintMem[level][i]; - i++; - - switch (ch) { - case 0x0A: // Line Feed ('\n') - cursor_y += font_h; - if (cursor_y >= GLCD_HEIGHT) { - // If cursor is out of screen vertically then rollover to vertical 0 - cursor_y = 0U; - } - break; - case 0x0D: // Carriage Return ('\r') - // Move the cursor to horizontal 0 - cursor_x = 0U; - break; - default: // Any other character - // Display current character at the cursor position - (void)GLCD_DrawChar(cursor_x, cursor_y, ch); - // Move the cursor to the next character on the right - cursor_x += font_w; - if (cursor_x >= GLCD_WIDTH) { - // If cursor is out of screen horizontally then rollover to horizontal 0 - // and into new line - cursor_x = 0U; - cursor_y += font_h; - if (cursor_y >= GLCD_HEIGHT) { - // If cursor is out of screen vertically then rollover to vertical 0 - cursor_y = 0U; - } - } - break; - } - } - - osMutexRelease(mid_GLCD); - } -#endif - - return (ret); -} - -// Set signal output. -void vioSetSignal (uint32_t mask, uint32_t signal) { - - vioSignalOut &= ~mask; - vioSignalOut |= mask & signal; - -#if !defined(CMSIS_VOUT) - (void)LED_SetOut(mask & signal); -#endif -} - -// Get signal input. -uint32_t vioGetSignal (uint32_t mask) { - uint32_t signal; - -#if !defined(CMSIS_VIN) - vioSignalIn = Buttons_GetState(); -#endif - signal = vioSignalIn; - - return (signal & mask); -} - -// Set value output. -void vioSetValue (uint32_t id, int32_t value) { - uint32_t index = id; - - if (index >= VIO_VALUE_NUM) { - return; /* return in case of out-of-range index */ - } - - vioValue[index] = value; -} - -// Get value input. -int32_t vioGetValue (uint32_t id) { - uint32_t index = id; - int32_t value = 0; - - if (index >= VIO_VALUE_NUM) { - return value; /* return default in case of out-of-range index */ - } - - value = vioValue[index]; - - return value; -} - -// Set XYZ value output. -void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) { - uint32_t index = id; - - if (index >= VIO_VALUE_XYZ_NUM) { - return; /* return in case of out-of-range index */ - } - - vioValueXYZ[index] = valueXYZ; -} - -// Get XYZ value input. -vioValueXYZ_t vioGetXYZ (uint32_t id) { - uint32_t index = id; - vioValueXYZ_t valueXYZ = {0, 0, 0}; - - if (index >= VIO_VALUE_XYZ_NUM) { - return valueXYZ; /* return default in case of out-of-range index */ - } - - valueXYZ = vioValueXYZ[index]; - - return valueXYZ; -} - -// Set IPv4 address output. -void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) { - uint32_t index = id; - - if (index >= VIO_IPV4_ADDRESS_NUM) { - return; /* return in case of out-of-range index */ - } - - vioAddrIPv4[index] = addrIPv4; -} - -// Get IPv4 address input. -vioAddrIPv4_t vioGetIPv4 (uint32_t id) { - uint32_t index = id; - vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U}; - - if (index >= VIO_IPV4_ADDRESS_NUM) { - return addrIPv4; /* return default in case of out-of-range index */ - } - - addrIPv4 = vioAddrIPv4[index]; - - return addrIPv4; -} - -// Set IPv6 address output. -void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) { - uint32_t index = id; - - if (index >= VIO_IPV6_ADDRESS_NUM) { - return; /* return in case of out-of-range index */ - } - - vioAddrIPv6[index] = addrIPv6; -} - -// Get IPv6 address input. -vioAddrIPv6_t vioGetIPv6 (uint32_t id) { - uint32_t index = id; - vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, - 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; - - if (index >= VIO_IPV6_ADDRESS_NUM) { - return addrIPv6; /* return default in case of out-of-range index */ - } - - addrIPv6 = vioAddrIPv6[index]; - - return addrIPv6; -} diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/Abstract.txt b/Tools/SPI_Server/Board/STM32F429I-DISC1/Abstract.txt deleted file mode 100644 index 49ffb6d..0000000 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/Abstract.txt +++ /dev/null @@ -1,115 +0,0 @@ -This is an SPI Server application for the STMicroelectronics STM32F429I-DISC1 (32F429IDISCOVERY) board. -The application executes commands sent from the SPI Client over the -SPI interface and is used to physically test compliance of the SPI driver -with the CMSIS SPI driver specification from version 2.0.0 upwards. - -Operation: -The SPI Server (in Slave mode) waits to receive a command over the SPI interface. -After command is received it is executed, and SPI Server again waits to receive -next command. -Command execution finishes by finishing the requested operation or by timeout. -All commands except XFER use fixed communication configuration, and timeout as -specified in the SPI_Server_Config.h configuration file. -Only XFER command is executed using settings configured by SET COM command, -after execution of the XFER command the SPI interface is configured back to -fixed configuration, so next command can be received. -The XFER command is executed until it finishes or until timeout specified in -the command expires. -If timeout is not specified in the command the last specified timeout from -previous XFER command is used. -If timeout was never specified in the XFER command then default timeout setting -is used. - -Fixed SPI interface configuration: - - Mode: Slave mode with Slave Select Hardware monitored - - Clock / Frame Format: Clock Polarity 0, Clock Phase 0 - - Data Bits: 8 - - Bit Order: MSB to LSB - -Hardware configuration of the SPI Server (peripheral SPI1 is used): - Function: Pin: - SCLK PA5 - MOSI PA7 - MISO PB4 - SS PA15 (with external pull-up to Vcc) - GND any ground connection on the board - -SPI Server commands (32 bytes long (zero padding), [] means parameter is optional): - - GET VER <- followed by 16 bytes OUT data phase - - GET CAP <- followed by 32 bytes OUT data phase - - SET BUF RX/TX,len[,pattern] -> followed by optional 'len' bytes IN data phase - - GET BUF RX/TX,len <- followed by 'len' bytes OUT data phase - - SET COM mode,format,bit_num,bit_order,ss_mode,bus_speed - - XFER num[,delay_c][,delay_t][,timeout] <-> followed by 'num' items data IN/OUT transfer - - GET CNT <- followed by 16 bytes OUT data phase - -SPI Server command parameters: - RX/TX: RX = SPI Server's receive buffer, TX = SPI Server's transmit buffer - len: length of content in the following IN/OUT data phase - pattern: value (in hex notation) to pre-fill the buffer with - mode: 0 = Master, 1 = Slave - format: 0 = Clock Polarity 0, Clock Phase 0 - 1 = Clock Polarity 0, Clock Phase 1 - 2 = Clock Polarity 1, Clock Phase 0 - 3 = Clock Polarity 1, Clock Phase 1 - 4 = Texas Instruments Frame Format - 5 = National Semiconductor Microwire Frame Format - bit_num: number of bits (1 .. 32) - bit_order: 0 = MSB to LSB, 1 = LSB to MSB - ss_mode: 0 = unused, 1 = Master driven / Slave monitored - bus_speed: bus speed (in bps) - num: number of items (according CMSIS SPI driver specification) - delay_c: delay before Control function is called, in milliseconds - delay_t: delay after Control function is called but before Transfer function is called, in milliseconds - timeout: total transfer timeout including delay_c and delay_t delays, in milliseconds - -SPI Server responses to commands: - - GET VER: 16 bytes containing string representation in form: - "major.minor.patch" - - GET CAP: 32 bytes containing values representing masks (bit value 1 means supported) or values as follows: - "mode_mask,format_mask,data_bit_mask,bit_order_mask,min_bus_speed_in_kbps,max_bus_speed_in_kbps" - - mode_mask (2 digits in hex): specifies mask of supported modes - - bit 0.: Master - - bit 1.: Slave - - format_mask (2 digits in hex): specifies mask of supported clock/frame formats - - bit 0.: Clock Polarity 0, Clock Phase 0 - - bit 1.: Clock Polarity 0, Clock Phase 1 - - bit 2.: Clock Polarity 1, Clock Phase 0 - - bit 3.: Clock Polarity 1, Clock Phase 1 - - bit 4.: Texas Instruments Frame Format - - bit 5.: National Semiconductor Microwire Frame Format - - data_bit_mask (8 digits in hex): specifies mask of supported data bits - - bit 0.: Data Bits 1 - ... - - bit 31.: Data Bits 32 - - bit_order_mask (1 byte in hex): specifies mask of supported bit orders - - bit 0.: MSB to LSB - - bit 1.: LSB to MSB - - min_bus_speed_in_kbps (dec): minimum supported bus speed (in kbps) - - max_bus_speed_in_kbps (dec): maximum supported bus speed (in kbps) - - GET BUF: 'len' bytes from respective buffer, in binary format - - GET CNT: 16 bytes containing value in decimal notation - -The SPI Server for the STMicroelectronics STM32F429I-DISC1 (32F429IDISCOVERY) board is available for different targets: - - Release: target with high optimization and no User Interface - - Debug: target with low optimization and User Interface (GLCD, LED) - -Command examples: - Get version: - -> GET VER <- 16 bytes (for example "1.1.0") - Get capabilities: - -> GET CAP <- 32 bytes (for example "03,1F,00008080,03,1000,10000") - Set Tx buffer to 'S': - -> SET BUF TX,0,53 - Set Rx buffer to '?': - -> SET BUF RX,0,3F - Get 16 bytes of Rx buffer content: - -> GET BUF RX,16 <- 16 bytes (for example "????????????????") - Set communication mode to slave, clock phase 0, clock polarity 0, - 8 data bits, MSB first, slave select hardware monitored, 2MBps: - -> SET COM 1,0,8,0,1,2000000 - Transfer 16 bytes in both directions: - -> XFER 16,10,0,100 <-> 16 bytes - Get count: - -> GET CNT <- 16 bytes (for example "16") - diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/SPI_Server.uvguix b/Tools/SPI_Server/Board/STM32F429I-DISC1/SPI_Server.uvguix deleted file mode 100644 index 829ad63..0000000 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/SPI_Server.uvguix +++ /dev/null @@ -1,3628 +0,0 @@ - - - - -6.1 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RTE\CMSIS\RTX_Config.c - - - - - - - - - RTE\CMSIS\RTX_Config.h - - - - - - - - - RTE\Device\STM32F429ZITx\RTE_Device.h - - - - - - - - - RTE\Device\STM32F429ZITx\startup_stm32f429xx.s - - - - - - - - - RTE\Device\STM32F429ZITx\stm32f4xx_hal_conf.h - - - - - - - - - RTE\Device\STM32F429ZITx\system_stm32f4xx.c - - - - - - - - - - - - - - SPI_Server - 1 - - - - - diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/main.h b/Tools/SPI_Server/Board/STM32F429I-DISC1/main.h deleted file mode 100644 index 3393f3e..0000000 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/main.h +++ /dev/null @@ -1,51 +0,0 @@ -/*------------------------------------------------------------------------------ - * Copyright (c) 2020 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1.Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2.Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3.Neither the name of Arm nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *------------------------------------------------------------------------------ - * Name: main.h - * Purpose: Main header file - *----------------------------------------------------------------------------*/ - -#ifndef MAIN_H -#define MAIN_H - -#include - -#ifdef _RTE_ -#include "RTE_Components.h" // Component selection -#endif -#include CMSIS_device_header -#ifdef RTE_CMSIS_RTOS2 // when RTE component CMSIS RTOS2 is used -#include "cmsis_os2.h" // ::CMSIS:RTOS2 -#endif - - -// Global functions -extern int32_t main (void); - -#endif diff --git a/Tools/SPI_Server/STM32F429I-DISC1/.cmsis/SPI_Server+STM32F429ZITx.dbgconf b/Tools/SPI_Server/STM32F429I-DISC1/.cmsis/SPI_Server+STM32F429ZITx.dbgconf new file mode 100644 index 0000000..c518755 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/.cmsis/SPI_Server+STM32F429ZITx.dbgconf @@ -0,0 +1,48 @@ +// File: STM32F405_415_407_417_427_437_429_439.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090) +// refer to STM32F40x STM32F41x datasheets +// refer to STM32F42x STM32F43x datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug Standby Mode +// DBG_STOP Debug Stop Mode +// DBG_SLEEP Debug Sleep Mode +// +DbgMCU_CR = 0x00000007; + +// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) +// Reserved bits must be kept at reset value +// DBG_CAN2_STOP CAN2 stopped when core is halted +// DBG_CAN1_STOP CAN2 stopped when core is halted +// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted +// DBG_IWDG_STOP Independent watchdog stopped when core is halted +// DBG_WWDG_STOP Window watchdog stopped when core is halted +// DBG_RTC_STOP RTC stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// +DbgMCU_APB1_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB2_Fz = 0x00000000; + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/Tools/SPI_Server/STM32F429I-DISC1/.cmsis/SPI_Server+STM32F429ZITx.dbgconf.base@0.0.0 b/Tools/SPI_Server/STM32F429I-DISC1/.cmsis/SPI_Server+STM32F429ZITx.dbgconf.base@0.0.0 new file mode 100644 index 0000000..c518755 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/.cmsis/SPI_Server+STM32F429ZITx.dbgconf.base@0.0.0 @@ -0,0 +1,48 @@ +// File: STM32F405_415_407_417_427_437_429_439.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090) +// refer to STM32F40x STM32F41x datasheets +// refer to STM32F42x STM32F43x datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug Standby Mode +// DBG_STOP Debug Stop Mode +// DBG_SLEEP Debug Sleep Mode +// +DbgMCU_CR = 0x00000007; + +// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) +// Reserved bits must be kept at reset value +// DBG_CAN2_STOP CAN2 stopped when core is halted +// DBG_CAN1_STOP CAN2 stopped when core is halted +// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted +// DBG_IWDG_STOP Independent watchdog stopped when core is halted +// DBG_WWDG_STOP Window watchdog stopped when core is halted +// DBG_RTC_STOP RTC stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// +DbgMCU_APB1_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB2_Fz = 0x00000000; + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/Board.clayer.yml b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/Board.clayer.yml new file mode 100644 index 0000000..498763b --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/Board.clayer.yml @@ -0,0 +1,72 @@ +layer: + type: Board + description: STM32F429I-DISC1 board setup + for-board: STMicroelectronics::STM32F429I-DISC1 + + connections: + - connect: STM32F429I-DISC1 Board + provides: + - CMSIS_SPI + - CMSIS_USART + - CMSIS_VIO + - STDIN + - STDOUT + - STDERR + - Heap: 16384 + + define: + - CMSIS_target_header: \"STM32F429I-DISC1.h\" + + packs: + - pack: Keil::STM32F4xx_DFP@2.16.0 + - pack: ARM::CMSIS@5.9.0 + - pack: ARM::CMSIS-Compiler@^2.0.0 + - pack: Keil::MDK-Middleware@7.13.0 + + components: + - component: Device:Startup + + - component: Device:STM32Cube Framework:Classic + - component: Device:STM32Cube HAL:Common + - component: Device:STM32Cube HAL:Cortex + - component: Device:STM32Cube HAL:DMA2D + - component: Device:STM32Cube HAL:DMA + - component: Device:STM32Cube HAL:GPIO + - component: Device:STM32Cube HAL:I2C + - component: Device:STM32Cube HAL:LTDC + - component: Device:STM32Cube HAL:PWR + - component: Device:STM32Cube HAL:RCC + - component: Device:STM32Cube HAL:SDRAM + - component: Device:STM32Cube HAL:SPI + - component: Device:STM32Cube HAL:UART + - component: Device:STM32Cube HAL:USART + + - component: Board Support&STM32F429I-Discovery:Components:ILI9341 + - component: Board Support&STM32F429I-Discovery:Drivers:Basic I/O + - component: Board Support&STM32F429I-Discovery:Drivers:LCD + - component: Board Support&STM32F429I-Discovery:Drivers:SDRAM + - component: Board Support&STM32F429I-Discovery:LED + + - component: CMSIS:CORE + + - component: CMSIS Driver:SPI + - component: CMSIS Driver:USART + - component: CMSIS Driver:VIO:Custom + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:Custom + - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDIN:Custom + + groups: + - group: Board + files: + - file: main.c + - file: STM32F429I-DISC1.h + - file: retarget_stdio.c + - file: vio_STM32F429I.c + + linker: + - script: ./RTE/Device/STM32F429ZITx/ac6_linker_script.sct.src + regions: ./RTE/Device/STM32F429ZITx/regions_STM32F429I-Discovery.h + for-compiler: AC6 diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h similarity index 97% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h index 789ece1..c65b936 100644 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h @@ -1,2693 +1,2693 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2018 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 9. April 2018 - * $Revision: V2.4.5 - * - * Project: RTE Device Configuration for ST STM32F4xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT0 GPIOA -#define GPIO_PORT1 GPIOB -#define GPIO_PORT2 GPIOC -#define GPIO_PORT3 GPIOD -#define GPIO_PORT4 GPIOE -#define GPIO_PORT5 GPIOF -#define GPIO_PORT6 GPIOG -#define GPIO_PORT7 GPIOH -#define GPIO_PORT8 GPIOI -#define GPIO_PORT9 GPIOJ -#define GPIO_PORT10 GPIOK - -#define GPIO_PORT(num) GPIO_PORT##num - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>Not Used <1=>PA9 <2=>PA15 <3=>PB6 +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2018 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 9. April 2018 + * $Revision: V2.4.5 + * + * Project: RTE Device Configuration for ST STM32F4xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT0 GPIOA +#define GPIO_PORT1 GPIOB +#define GPIO_PORT2 GPIOC +#define GPIO_PORT3 GPIOD +#define GPIO_PORT4 GPIOE +#define GPIO_PORT5 GPIOF +#define GPIO_PORT6 GPIOG +#define GPIO_PORT7 GPIOH +#define GPIO_PORT8 GPIOI +#define GPIO_PORT9 GPIOJ +#define GPIO_PORT10 GPIOK + +#define GPIO_PORT(num) GPIO_PORT##num + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 1 + +// USART1_TX Pin <0=>Not Used <1=>PA9 <2=>PA15 <3=>PB6 #define RTE_USART1_TX_ID 1 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX 0 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 2) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 15 -#elif (RTE_USART1_TX_ID == 3) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PA10 <2=>PB3 <3=>PB7 +#if (RTE_USART1_TX_ID == 0) +#define RTE_USART1_TX 0 +#elif (RTE_USART1_TX_ID == 1) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 9 +#elif (RTE_USART1_TX_ID == 2) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 15 +#elif (RTE_USART1_TX_ID == 3) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 <2=>PB3 <3=>PB7 #define RTE_USART1_RX_ID 1 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX 0 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 2) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 3 -#elif (RTE_USART1_RX_ID == 3) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// USART1_CK Pin <0=>Not Used <1=>PA8 +#if (RTE_USART1_RX_ID == 0) +#define RTE_USART1_RX 0 +#elif (RTE_USART1_RX_ID == 1) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOA +#define RTE_USART1_RX_BIT 10 +#elif (RTE_USART1_RX_ID == 2) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 3 +#elif (RTE_USART1_RX_ID == 3) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 #define RTE_USART1_CK_ID 1 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK 0 -#elif (RTE_USART1_CK_ID == 1) -#define RTE_USART1_CK 1 -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// USART1_CTS Pin <0=>Not Used <1=>PA11 +#if (RTE_USART1_CK_ID == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_ID == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT GPIOA +#define RTE_USART1_CK_BIT 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 #define RTE_USART1_CTS_ID 1 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS 0 -#elif (RTE_USART1_CTS_ID == 1) -#define RTE_USART1_CTS 1 -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif - -// USART1_RTS Pin <0=>Not Used <1=>PA12 +#if (RTE_USART1_CTS_ID == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_ID == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT GPIOA +#define RTE_USART1_CTS_BIT 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 #define RTE_USART1_RTS_ID 1 -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS 0 -#elif (RTE_USART1_RTS_ID == 1) -#define RTE_USART1_RTS 1 -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// +#if (RTE_USART1_RTS_ID == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_ID == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT GPIOA +#define RTE_USART1_RTS_BIT 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <5=>5 +// Selects DMA Stream (only Stream 2 or 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// #define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// +#define RTE_USART1_RX_DMA_NUMBER 2 +#define RTE_USART1_RX_DMA_STREAM 2 +#define RTE_USART1_RX_DMA_CHANNEL 4 +#define RTE_USART1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// #define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>Not Used <1=>PA2 <2=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX 0 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX 1 -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 2) -#define RTE_USART2_TX 1 -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PA3 <2=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX 0 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX 1 -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 2) -#define RTE_USART2_RX 1 -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PA4 <2=>PD7 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK 0 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK 1 -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 2) -#define RTE_USART2_CK 1 -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PA0 <2=>PD3 -#define RTE_USART2_CTS_ID 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS 1 -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 2) -#define RTE_USART2_CTS 1 -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PA1 <2=>PD4 -#define RTE_USART2_RTS_ID 0 -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS 0 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS 1 -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 2) -#define RTE_USART2_RTS 1 -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <4=>4 <6=>6 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 0 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 0 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>Not Used <1=>PB10 <2=>PC10 <3=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX 0 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 3) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PB11 <2=>PC11 <3=>PD9 <4=>PC5 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX 0 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 3) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#elif (RTE_USART3_RX_ID == 4) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 5 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PB12 <2=>PC12 <3=>PD10 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK 0 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 3) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PB13 <2=>PD11 -#define RTE_USART3_CTS_ID 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS 0 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS 1 -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 2) -#define RTE_USART3_CTS 1 -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PB14 <2=>PD12 -#define RTE_USART3_RTS_ID 0 -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS 0 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS 1 -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 2) -#define RTE_USART3_RTS 1 -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <4=>4 -// Selects DMA Stream (only Stream 1 or 4 can be used) -// Channel <4=>4 <7=>7 -// Selects DMA Channel (only Channel 4 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 0 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 <4=>4 -// Selects DMA Stream (only Stream 3 or 4 can be used) -// Channel <4=>4 <7=>7 -// Selects DMA Channel (only Channel 4 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 0 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] -// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>Not Used <1=>PA0 <2=>PC10 <3=>PD10 <4=>PA12 <5=>PD1 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 2) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#elif (RTE_UART4_TX_ID == 3) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOD -#define RTE_UART4_TX_BIT 10 -#elif (RTE_UART4_TX_ID == 4) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 12 -#elif (RTE_UART4_TX_ID == 5) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOD -#define RTE_UART4_TX_BIT 1 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>Not Used <1=>PA1 <2=>PC11 <3=>PA11 <4=>PD0 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX 0 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 2) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#elif (RTE_UART4_RX_ID == 3) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 11 -#elif (RTE_UART4_RX_ID == 4) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOD -#define RTE_UART4_RX_BIT 0 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 0 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 0 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] -// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>Not Used <1=>PC12 <2=>PB6 <3=>PB9 <4=>PB13 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX 0 -#elif (RTE_UART5_TX_ID == 1) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#elif (RTE_UART5_TX_ID == 2) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 6 -#elif (RTE_UART5_TX_ID == 3) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 9 -#elif (RTE_UART5_TX_ID == 4) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 13 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>Not Used <1=>PD2 <2=>PB5 <3=>PB8 <4=>PB12 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX 0 -#elif (RTE_UART5_RX_ID == 1) -#define RTE_UART5_RX 1 -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#elif (RTE_UART5_TX_ID == 2) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 5 -#elif (RTE_UART5_TX_ID == 3) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 8 -#elif (RTE_UART5_TX_ID == 4) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 0 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 <8=>8 -// Selects DMA Channel (only Channel 4 or 8 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 0 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_USART6] -// Configuration settings for Driver_USART6 in component ::CMSIS Driver:USART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>Not Used <1=>PA11 <2=>PC6 <3=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX 0 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOA -#define RTE_USART6_TX_BIT 11 -#elif (RTE_USART6_TX_ID == 2) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 3) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>Not Used <1=>PA12 <2=>PC7 <3=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX 0 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOA -#define RTE_USART6_RX_BIT 12 -#elif (RTE_USART6_RX_ID == 2) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 3) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// USART6_CK Pin <0=>Not Used <1=>PC8 <2=>PG7 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK 0 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK 1 -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 2) -#define RTE_USART6_CK 1 -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// USART6_CTS Pin <0=>Not Used <1=>PG13 <2=>PG15 -#define RTE_USART6_CTS_ID 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS 0 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS 1 -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 2) -#define RTE_USART6_CTS 1 -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif - -// USART6_RTS Pin <0=>Not Used <1=>PG8 <2=>PG12 -#define RTE_USART6_RTS_ID 0 -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS 0 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS 1 -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 2) -#define RTE_USART6_RTS 1 -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 0 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 0 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - -// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] -// Configuration settings for Driver_USART7 in component ::CMSIS Driver:USART -#define RTE_UART7 0 - -// UART7_TX Pin <0=>Not Used <1=>PF7 <2=>PE8 <3=>PA15 <4=>PB4 -#define RTE_UART7_TX_ID 0 -#if (RTE_UART7_TX_ID == 0) -#define RTE_UART7_TX 0 -#elif (RTE_UART7_TX_ID == 1) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOF -#define RTE_UART7_TX_BIT 7 -#elif (RTE_UART7_TX_ID == 2) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOE -#define RTE_UART7_TX_BIT 8 -#elif (RTE_UART7_TX_ID == 3) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOA -#define RTE_UART7_TX_BIT 15 -#elif (RTE_UART7_TX_ID == 4) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOB -#define RTE_UART7_TX_BIT 4 -#else -#error "Invalid UART7_TX Pin Configuration!" -#endif - -// UART7_RX Pin <0=>Not Used <1=>PF6 <2=>PE7 <3=>PA8 <4=>PB3 -#define RTE_UART7_RX_ID 0 -#if (RTE_UART7_RX_ID == 0) -#define RTE_UART7_RX 0 -#elif (RTE_UART7_RX_ID == 1) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOF -#define RTE_UART7_RX_BIT 6 -#elif (RTE_UART7_RX_ID == 2) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOE -#define RTE_UART7_RX_BIT 7 -#elif (RTE_UART7_RX_ID == 3) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOA -#define RTE_UART7_RX_BIT 8 -#elif (RTE_UART7_RX_ID == 4) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOB -#define RTE_UART7_RX_BIT 3 -#else -#error "Invalid UART7_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART7_RX_DMA 0 -#define RTE_UART7_RX_DMA_NUMBER 1 -#define RTE_UART7_RX_DMA_STREAM 3 -#define RTE_UART7_RX_DMA_CHANNEL 5 -#define RTE_UART7_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART7_TX_DMA 0 -#define RTE_UART7_TX_DMA_NUMBER 1 -#define RTE_UART7_TX_DMA_STREAM 1 -#define RTE_UART7_TX_DMA_CHANNEL 5 -#define RTE_UART7_TX_DMA_PRIORITY 0 - -// - -// UART8 (Universal asynchronous receiver transmitter) [Driver_USART8] -// Configuration settings for Driver_USART8 in component ::CMSIS Driver:USART -#define RTE_UART8 0 - -// UART8_TX Pin <0=>Not Used <1=>PE1 <2=>PF9 -#define RTE_UART8_TX_ID 0 -#if (RTE_UART8_TX_ID == 0) -#define RTE_UART8_TX 0 -#elif (RTE_UART8_TX_ID == 1) -#define RTE_UART8_TX 1 -#define RTE_UART8_TX_PORT GPIOE -#define RTE_UART8_TX_BIT 1 -#elif (RTE_UART8_TX_ID == 2) -#define RTE_UART8_TX 1 -#define RTE_UART8_TX_PORT GPIOF -#define RTE_UART8_TX_BIT 9 -#else -#error "Invalid UART8_TX Pin Configuration!" -#endif - -// UART8_RX Pin <0=>Not Used <1=>PE0 <2=>PF8 -#define RTE_UART8_RX_ID 0 -#if (RTE_UART8_RX_ID == 0) -#define RTE_UART8_RX 0 -#elif (RTE_UART8_RX_ID == 1) -#define RTE_UART8_RX 1 -#define RTE_UART8_RX_PORT GPIOE -#define RTE_UART8_RX_BIT 0 -#elif (RTE_UART8_RX_ID == 2) -#define RTE_UART8_RX 1 -#define RTE_UART8_RX_PORT GPIOF -#define RTE_UART8_RX_BIT 8 -#else -#error "Invalid UART8_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART8_RX_DMA 0 -#define RTE_UART8_RX_DMA_NUMBER 1 -#define RTE_UART8_RX_DMA_STREAM 6 -#define RTE_UART8_RX_DMA_CHANNEL 5 -#define RTE_UART8_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART8_TX_DMA 0 -#define RTE_UART8_TX_DMA_NUMBER 1 -#define RTE_UART8_TX_DMA_STREAM 0 -#define RTE_UART8_TX_DMA_CHANNEL 5 -#define RTE_UART8_TX_DMA_PRIORITY 0 - -// - -// UART9 (Universal asynchronous receiver transmitter) [Driver_USART9] -// Configuration settings for Driver_USART9 in component ::CMSIS Driver:USART -#define RTE_UART9 0 - -// UART9_TX Pin <0=>Not Used <1=>PD15 <2=>PG1 -#define RTE_UART9_TX_ID 0 -#if (RTE_UART9_TX_ID == 0) -#define RTE_UART9_TX 0 -#elif (RTE_UART9_TX_ID == 1) -#define RTE_UART9_TX 1 -#define RTE_UART9_TX_PORT GPIOD -#define RTE_UART9_TX_BIT 15 -#elif (RTE_UART9_TX_ID == 2) -#define RTE_UART9_TX 1 -#define RTE_UART9_TX_PORT GPIOG -#define RTE_UART9_TX_BIT 1 -#else -#error "Invalid UART9_TX Pin Configuration!" -#endif - -// UART9_RX Pin <0=>Not Used <1=>PD14 <2=>PG0 -#define RTE_UART9_RX_ID 0 -#if (RTE_UART9_RX_ID == 0) -#define RTE_UART9_RX 0 -#elif (RTE_UART9_RX_ID == 1) -#define RTE_UART9_RX 1 -#define RTE_UART9_RX_PORT GPIOD -#define RTE_UART9_RX_BIT 14 -#elif (RTE_UART9_RX_ID == 2) -#define RTE_UART9_RX 1 -#define RTE_UART9_RX_PORT GPIOG -#define RTE_UART9_RX_BIT 0 -#else -#error "Invalid UART9_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART9_RX_DMA 0 -#define RTE_UART9_RX_DMA_NUMBER 1 -#define RTE_UART9_RX_DMA_STREAM 6 -#define RTE_UART9_RX_DMA_CHANNEL 5 -#define RTE_UART9_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART9_TX_DMA 0 -#define RTE_UART9_TX_DMA_NUMBER 1 -#define RTE_UART9_TX_DMA_STREAM 0 -#define RTE_UART9_TX_DMA_CHANNEL 5 -#define RTE_UART9_TX_DMA_PRIORITY 0 - -// - -// UART10 (Universal asynchronous receiver transmitter) [Driver_USART10] -// Configuration settings for Driver_USART10 in component ::CMSIS Driver:USART -#define RTE_UART10 0 - -// UART10_TX Pin <0=>Not Used <1=>PE3 <2=>PG12 -#define RTE_UART10_TX_ID 0 -#if (RTE_UART10_TX_ID == 0) -#define RTE_UART10_TX 0 -#elif (RTE_UART10_TX_ID == 1) -#define RTE_UART10_TX 1 -#define RTE_UART10_TX_PORT GPIOE -#define RTE_UART10_TX_BIT 3 -#elif (RTE_UART10_TX_ID == 2) -#define RTE_UART10_TX 1 -#define RTE_UART10_TX_PORT GPIOG -#define RTE_UART10_TX_BIT 12 -#else -#error "Invalid UART10_TX Pin Configuration!" -#endif - -// UART10_RX Pin <0=>Not Used <1=>PE2 <2=>PG11 -#define RTE_UART10_RX_ID 0 -#if (RTE_UART10_RX_ID == 0) -#define RTE_UART10_RX 0 -#elif (RTE_UART10_RX_ID == 1) -#define RTE_UART10_RX 1 -#define RTE_UART10_RX_PORT GPIOE -#define RTE_UART10_RX_BIT 2 -#elif (RTE_UART10_RX_ID == 2) -#define RTE_UART10_RX 1 -#define RTE_UART10_RX_PORT GPIOG -#define RTE_UART10_RX_BIT 11 -#else -#error "Invalid UART10_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <3=>3 -// Selects DMA Stream (only Stream 0 or 3 can be used) -// Channel <5=>5 <9=>9 -// Selects DMA Channel (only Channel 5 or 9 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART10_RX_DMA 0 -#define RTE_UART10_RX_DMA_NUMBER 1 -#define RTE_UART10_RX_DMA_STREAM 6 -#define RTE_UART10_RX_DMA_CHANNEL 5 -#define RTE_UART10_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 <3=>5 -// Selects DMA Stream (only Stream 7 or 5 can be used) -// Channel <6=>6 <9=>9 -// Selects DMA Channel (only Channel 6 or 9 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART10_TX_DMA 0 -#define RTE_UART10_TX_DMA_NUMBER 1 -#define RTE_UART10_TX_DMA_STREAM 0 -#define RTE_UART10_TX_DMA_CHANNEL 5 -#define RTE_UART10_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 0 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <6=>6 <7=>7 -// Selects DMA Stream (only Stream 1 or 6 or 7 can be used) -// Channel <0=>0 <1=>1 -// Selects DMA Channel (only Channel 0 or 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 0 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 <3=>PB3 <4=>PB9 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#elif (RTE_I2C2_SDA_PORT_ID == 3) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 3 -#elif (RTE_I2C2_SDA_PORT_ID == 4) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 9 -#else -#error "Invalid I2C2_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 0 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 0 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::CMSIS Driver:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 <2=>PB4 <3=>PB8 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#elif (RTE_I2C3_SDA_PORT_ID == 2) -#define RTE_I2C3_SDA_PORT GPIOB -#define RTE_I2C3_SDA_BIT 4 -#elif (RTE_I2C3_SDA_PORT_ID == 3) -#define RTE_I2C3_SDA_PORT GPIOB -#define RTE_I2C3_SDA_BIT 8 -#else -#error "Invalid I2C3_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <1=>1 <3=>3 -// Selects DMA Channel (only Channel 1 or 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 0 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 <5=>5 -// Selects DMA Stream (only Stream 4 or 5 can be used) -// Channel <3=>3 <6=>6 -// Selects DMA Channel (only Channel 3 or 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 0 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_USART1_TX_DMA_NUMBER 2 +#define RTE_USART1_TX_DMA_STREAM 7 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 + +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 1 + +// USART2_TX Pin <0=>Not Used <1=>PA2 <2=>PD5 +#define RTE_USART2_TX_ID 2 +#if (RTE_USART2_TX_ID == 0) +#define RTE_USART2_TX 0 +#elif (RTE_USART2_TX_ID == 1) +#define RTE_USART2_TX 1 +#define RTE_USART2_TX_PORT GPIOA +#define RTE_USART2_TX_BIT 2 +#elif (RTE_USART2_TX_ID == 2) +#define RTE_USART2_TX 1 +#define RTE_USART2_TX_PORT GPIOD +#define RTE_USART2_TX_BIT 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 <2=>PD6 +#define RTE_USART2_RX_ID 2 +#if (RTE_USART2_RX_ID == 0) +#define RTE_USART2_RX 0 +#elif (RTE_USART2_RX_ID == 1) +#define RTE_USART2_RX 1 +#define RTE_USART2_RX_PORT GPIOA +#define RTE_USART2_RX_BIT 3 +#elif (RTE_USART2_RX_ID == 2) +#define RTE_USART2_RX 1 +#define RTE_USART2_RX_PORT GPIOD +#define RTE_USART2_RX_BIT 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 <2=>PD7 +#define RTE_USART2_CK_ID 0 +#if (RTE_USART2_CK_ID == 0) +#define RTE_USART2_CK 0 +#elif (RTE_USART2_CK_ID == 1) +#define RTE_USART2_CK 1 +#define RTE_USART2_CK_PORT GPIOA +#define RTE_USART2_CK_BIT 4 +#elif (RTE_USART2_CK_ID == 2) +#define RTE_USART2_CK 1 +#define RTE_USART2_CK_PORT GPIOD +#define RTE_USART2_CK_BIT 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 <2=>PD3 +#define RTE_USART2_CTS_ID 0 +#if (RTE_USART2_CTS_ID == 0) +#define RTE_USART2_CTS 0 +#elif (RTE_USART2_CTS_ID == 1) +#define RTE_USART2_CTS 1 +#define RTE_USART2_CTS_PORT GPIOA +#define RTE_USART2_CTS_BIT 0 +#elif (RTE_USART2_CTS_ID == 2) +#define RTE_USART2_CTS 1 +#define RTE_USART2_CTS_PORT GPIOD +#define RTE_USART2_CTS_BIT 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 <2=>PD4 +#define RTE_USART2_RTS_ID 0 +#if (RTE_USART2_RTS_ID == 0) +#define RTE_USART2_RTS 0 +#elif (RTE_USART2_RTS_ID == 1) +#define RTE_USART2_RTS 1 +#define RTE_USART2_RTS_PORT GPIOA +#define RTE_USART2_RTS_BIT 1 +#elif (RTE_USART2_RTS_ID == 2) +#define RTE_USART2_RTS 1 +#define RTE_USART2_RTS_PORT GPIOD +#define RTE_USART2_RTS_BIT 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <4=>4 <6=>6 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_STREAM 5 +#define RTE_USART2_RX_DMA_CHANNEL 4 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_STREAM 6 +#define RTE_USART2_TX_DMA_CHANNEL 4 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 <2=>PC10 <3=>PD8 +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) +#define RTE_USART3_TX 0 +#elif (RTE_USART3_TX_ID == 1) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOB +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 2) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOC +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 3) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOD +#define RTE_USART3_TX_BIT 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 <2=>PC11 <3=>PD9 <4=>PC5 +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) +#define RTE_USART3_RX 0 +#elif (RTE_USART3_RX_ID == 1) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOB +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 2) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 3) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOD +#define RTE_USART3_RX_BIT 9 +#elif (RTE_USART3_RX_ID == 4) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 5 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 <2=>PC12 <3=>PD10 +#define RTE_USART3_CK_ID 0 +#if (RTE_USART3_CK_ID == 0) +#define RTE_USART3_CK 0 +#elif (RTE_USART3_CK_ID == 1) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOB +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 2) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOC +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 3) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOD +#define RTE_USART3_CK_BIT 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 <2=>PD11 +#define RTE_USART3_CTS_ID 0 +#if (RTE_USART3_CTS_ID == 0) +#define RTE_USART3_CTS 0 +#elif (RTE_USART3_CTS_ID == 1) +#define RTE_USART3_CTS 1 +#define RTE_USART3_CTS_PORT GPIOB +#define RTE_USART3_CTS_BIT 13 +#elif (RTE_USART3_CTS_ID == 2) +#define RTE_USART3_CTS 1 +#define RTE_USART3_CTS_PORT GPIOD +#define RTE_USART3_CTS_BIT 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 <2=>PD12 +#define RTE_USART3_RTS_ID 0 +#if (RTE_USART3_RTS_ID == 0) +#define RTE_USART3_RTS 0 +#elif (RTE_USART3_RTS_ID == 1) +#define RTE_USART3_RTS 1 +#define RTE_USART3_RTS_PORT GPIOB +#define RTE_USART3_RTS_BIT 14 +#elif (RTE_USART3_RTS_ID == 2) +#define RTE_USART3_RTS 1 +#define RTE_USART3_RTS_PORT GPIOD +#define RTE_USART3_RTS_BIT 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <4=>4 +// Selects DMA Stream (only Stream 1 or 4 can be used) +// Channel <4=>4 <7=>7 +// Selects DMA Channel (only Channel 4 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_STREAM 1 +#define RTE_USART3_RX_DMA_CHANNEL 4 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 <4=>4 +// Selects DMA Stream (only Stream 3 or 4 can be used) +// Channel <4=>4 <7=>7 +// Selects DMA Channel (only Channel 4 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_STREAM 3 +#define RTE_USART3_TX_DMA_CHANNEL 4 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 + +// UART4_TX Pin <0=>Not Used <1=>PA0 <2=>PC10 <3=>PD10 <4=>PA12 <5=>PD1 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 0 +#elif (RTE_UART4_TX_ID == 2) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#elif (RTE_UART4_TX_ID == 3) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOD +#define RTE_UART4_TX_BIT 10 +#elif (RTE_UART4_TX_ID == 4) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 12 +#elif (RTE_UART4_TX_ID == 5) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOD +#define RTE_UART4_TX_BIT 1 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PA1 <2=>PC11 <3=>PA11 <4=>PD0 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 1 +#elif (RTE_UART4_RX_ID == 2) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#elif (RTE_UART4_RX_ID == 3) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 11 +#elif (RTE_UART4_RX_ID == 4) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOD +#define RTE_UART4_RX_BIT 0 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 1 +#define RTE_UART4_RX_DMA_STREAM 2 +#define RTE_UART4_RX_DMA_CHANNEL 4 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 1 +#define RTE_UART4_TX_DMA_STREAM 4 +#define RTE_UART4_TX_DMA_CHANNEL 4 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 + +// UART5_TX Pin <0=>Not Used <1=>PC12 <2=>PB6 <3=>PB9 <4=>PB13 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#elif (RTE_UART5_TX_ID == 2) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 6 +#elif (RTE_UART5_TX_ID == 3) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 9 +#elif (RTE_UART5_TX_ID == 4) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 13 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 <2=>PB5 <3=>PB8 <4=>PB12 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#elif (RTE_UART5_TX_ID == 2) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 5 +#elif (RTE_UART5_TX_ID == 3) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 8 +#elif (RTE_UART5_TX_ID == 4) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_RX_DMA 0 +#define RTE_UART5_RX_DMA_NUMBER 1 +#define RTE_UART5_RX_DMA_STREAM 0 +#define RTE_UART5_RX_DMA_CHANNEL 4 +#define RTE_UART5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 <8=>8 +// Selects DMA Channel (only Channel 4 or 8 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_TX_DMA 0 +#define RTE_UART5_TX_DMA_NUMBER 1 +#define RTE_UART5_TX_DMA_STREAM 7 +#define RTE_UART5_TX_DMA_CHANNEL 4 +#define RTE_UART5_TX_DMA_PRIORITY 0 + +// + + +// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::CMSIS Driver:USART +#define RTE_USART6 0 + +// USART6_TX Pin <0=>Not Used <1=>PA11 <2=>PC6 <3=>PG14 +#define RTE_USART6_TX_ID 0 +#if (RTE_USART6_TX_ID == 0) +#define RTE_USART6_TX 0 +#elif (RTE_USART6_TX_ID == 1) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOA +#define RTE_USART6_TX_BIT 11 +#elif (RTE_USART6_TX_ID == 2) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOC +#define RTE_USART6_TX_BIT 6 +#elif (RTE_USART6_TX_ID == 3) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOG +#define RTE_USART6_TX_BIT 14 +#else +#error "Invalid USART6_TX Pin Configuration!" +#endif + +// USART6_RX Pin <0=>Not Used <1=>PA12 <2=>PC7 <3=>PG9 +#define RTE_USART6_RX_ID 0 +#if (RTE_USART6_RX_ID == 0) +#define RTE_USART6_RX 0 +#elif (RTE_USART6_RX_ID == 1) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOA +#define RTE_USART6_RX_BIT 12 +#elif (RTE_USART6_RX_ID == 2) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOC +#define RTE_USART6_RX_BIT 7 +#elif (RTE_USART6_RX_ID == 3) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOG +#define RTE_USART6_RX_BIT 9 +#else +#error "Invalid USART6_RX Pin Configuration!" +#endif + +// USART6_CK Pin <0=>Not Used <1=>PC8 <2=>PG7 +#define RTE_USART6_CK_ID 0 +#if (RTE_USART6_CK_ID == 0) +#define RTE_USART6_CK 0 +#elif (RTE_USART6_CK_ID == 1) +#define RTE_USART6_CK 1 +#define RTE_USART6_CK_PORT GPIOC +#define RTE_USART6_CK_BIT 8 +#elif (RTE_USART6_CK_ID == 2) +#define RTE_USART6_CK 1 +#define RTE_USART6_CK_PORT GPIOG +#define RTE_USART6_CK_BIT 7 +#else +#error "Invalid USART6_CK Pin Configuration!" +#endif + +// USART6_CTS Pin <0=>Not Used <1=>PG13 <2=>PG15 +#define RTE_USART6_CTS_ID 0 +#if (RTE_USART6_CTS_ID == 0) +#define RTE_USART6_CTS 0 +#elif (RTE_USART6_CTS_ID == 1) +#define RTE_USART6_CTS 1 +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 13 +#elif (RTE_USART6_CTS_ID == 2) +#define RTE_USART6_CTS 1 +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 15 +#else +#error "Invalid USART6_CTS Pin Configuration!" +#endif + +// USART6_RTS Pin <0=>Not Used <1=>PG8 <2=>PG12 +#define RTE_USART6_RTS_ID 0 +#if (RTE_USART6_RTS_ID == 0) +#define RTE_USART6_RTS 0 +#elif (RTE_USART6_RTS_ID == 1) +#define RTE_USART6_RTS 1 +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 8 +#elif (RTE_USART6_RTS_ID == 2) +#define RTE_USART6_RTS 1 +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 12 +#else +#error "Invalid USART6_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_RX_DMA 0 +#define RTE_USART6_RX_DMA_NUMBER 2 +#define RTE_USART6_RX_DMA_STREAM 1 +#define RTE_USART6_RX_DMA_CHANNEL 5 +#define RTE_USART6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_TX_DMA 0 +#define RTE_USART6_TX_DMA_NUMBER 2 +#define RTE_USART6_TX_DMA_STREAM 6 +#define RTE_USART6_TX_DMA_CHANNEL 5 +#define RTE_USART6_TX_DMA_PRIORITY 0 + +// + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::CMSIS Driver:USART +#define RTE_UART7 0 + +// UART7_TX Pin <0=>Not Used <1=>PF7 <2=>PE8 <3=>PA15 <4=>PB4 +#define RTE_UART7_TX_ID 0 +#if (RTE_UART7_TX_ID == 0) +#define RTE_UART7_TX 0 +#elif (RTE_UART7_TX_ID == 1) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOF +#define RTE_UART7_TX_BIT 7 +#elif (RTE_UART7_TX_ID == 2) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOE +#define RTE_UART7_TX_BIT 8 +#elif (RTE_UART7_TX_ID == 3) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOA +#define RTE_UART7_TX_BIT 15 +#elif (RTE_UART7_TX_ID == 4) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOB +#define RTE_UART7_TX_BIT 4 +#else +#error "Invalid UART7_TX Pin Configuration!" +#endif + +// UART7_RX Pin <0=>Not Used <1=>PF6 <2=>PE7 <3=>PA8 <4=>PB3 +#define RTE_UART7_RX_ID 0 +#if (RTE_UART7_RX_ID == 0) +#define RTE_UART7_RX 0 +#elif (RTE_UART7_RX_ID == 1) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOF +#define RTE_UART7_RX_BIT 6 +#elif (RTE_UART7_RX_ID == 2) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOE +#define RTE_UART7_RX_BIT 7 +#elif (RTE_UART7_RX_ID == 3) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOA +#define RTE_UART7_RX_BIT 8 +#elif (RTE_UART7_RX_ID == 4) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOB +#define RTE_UART7_RX_BIT 3 +#else +#error "Invalid UART7_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART7_RX_DMA 0 +#define RTE_UART7_RX_DMA_NUMBER 1 +#define RTE_UART7_RX_DMA_STREAM 3 +#define RTE_UART7_RX_DMA_CHANNEL 5 +#define RTE_UART7_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART7_TX_DMA 0 +#define RTE_UART7_TX_DMA_NUMBER 1 +#define RTE_UART7_TX_DMA_STREAM 1 +#define RTE_UART7_TX_DMA_CHANNEL 5 +#define RTE_UART7_TX_DMA_PRIORITY 0 + +// + +// UART8 (Universal asynchronous receiver transmitter) [Driver_USART8] +// Configuration settings for Driver_USART8 in component ::CMSIS Driver:USART +#define RTE_UART8 0 + +// UART8_TX Pin <0=>Not Used <1=>PE1 <2=>PF9 +#define RTE_UART8_TX_ID 0 +#if (RTE_UART8_TX_ID == 0) +#define RTE_UART8_TX 0 +#elif (RTE_UART8_TX_ID == 1) +#define RTE_UART8_TX 1 +#define RTE_UART8_TX_PORT GPIOE +#define RTE_UART8_TX_BIT 1 +#elif (RTE_UART8_TX_ID == 2) +#define RTE_UART8_TX 1 +#define RTE_UART8_TX_PORT GPIOF +#define RTE_UART8_TX_BIT 9 +#else +#error "Invalid UART8_TX Pin Configuration!" +#endif + +// UART8_RX Pin <0=>Not Used <1=>PE0 <2=>PF8 +#define RTE_UART8_RX_ID 0 +#if (RTE_UART8_RX_ID == 0) +#define RTE_UART8_RX 0 +#elif (RTE_UART8_RX_ID == 1) +#define RTE_UART8_RX 1 +#define RTE_UART8_RX_PORT GPIOE +#define RTE_UART8_RX_BIT 0 +#elif (RTE_UART8_RX_ID == 2) +#define RTE_UART8_RX 1 +#define RTE_UART8_RX_PORT GPIOF +#define RTE_UART8_RX_BIT 8 +#else +#error "Invalid UART8_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART8_RX_DMA 0 +#define RTE_UART8_RX_DMA_NUMBER 1 +#define RTE_UART8_RX_DMA_STREAM 6 +#define RTE_UART8_RX_DMA_CHANNEL 5 +#define RTE_UART8_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART8_TX_DMA 0 +#define RTE_UART8_TX_DMA_NUMBER 1 +#define RTE_UART8_TX_DMA_STREAM 0 +#define RTE_UART8_TX_DMA_CHANNEL 5 +#define RTE_UART8_TX_DMA_PRIORITY 0 + +// + +// UART9 (Universal asynchronous receiver transmitter) [Driver_USART9] +// Configuration settings for Driver_USART9 in component ::CMSIS Driver:USART +#define RTE_UART9 0 + +// UART9_TX Pin <0=>Not Used <1=>PD15 <2=>PG1 +#define RTE_UART9_TX_ID 0 +#if (RTE_UART9_TX_ID == 0) +#define RTE_UART9_TX 0 +#elif (RTE_UART9_TX_ID == 1) +#define RTE_UART9_TX 1 +#define RTE_UART9_TX_PORT GPIOD +#define RTE_UART9_TX_BIT 15 +#elif (RTE_UART9_TX_ID == 2) +#define RTE_UART9_TX 1 +#define RTE_UART9_TX_PORT GPIOG +#define RTE_UART9_TX_BIT 1 +#else +#error "Invalid UART9_TX Pin Configuration!" +#endif + +// UART9_RX Pin <0=>Not Used <1=>PD14 <2=>PG0 +#define RTE_UART9_RX_ID 0 +#if (RTE_UART9_RX_ID == 0) +#define RTE_UART9_RX 0 +#elif (RTE_UART9_RX_ID == 1) +#define RTE_UART9_RX 1 +#define RTE_UART9_RX_PORT GPIOD +#define RTE_UART9_RX_BIT 14 +#elif (RTE_UART9_RX_ID == 2) +#define RTE_UART9_RX 1 +#define RTE_UART9_RX_PORT GPIOG +#define RTE_UART9_RX_BIT 0 +#else +#error "Invalid UART9_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART9_RX_DMA 0 +#define RTE_UART9_RX_DMA_NUMBER 1 +#define RTE_UART9_RX_DMA_STREAM 6 +#define RTE_UART9_RX_DMA_CHANNEL 5 +#define RTE_UART9_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART9_TX_DMA 0 +#define RTE_UART9_TX_DMA_NUMBER 1 +#define RTE_UART9_TX_DMA_STREAM 0 +#define RTE_UART9_TX_DMA_CHANNEL 5 +#define RTE_UART9_TX_DMA_PRIORITY 0 + +// + +// UART10 (Universal asynchronous receiver transmitter) [Driver_USART10] +// Configuration settings for Driver_USART10 in component ::CMSIS Driver:USART +#define RTE_UART10 0 + +// UART10_TX Pin <0=>Not Used <1=>PE3 <2=>PG12 +#define RTE_UART10_TX_ID 0 +#if (RTE_UART10_TX_ID == 0) +#define RTE_UART10_TX 0 +#elif (RTE_UART10_TX_ID == 1) +#define RTE_UART10_TX 1 +#define RTE_UART10_TX_PORT GPIOE +#define RTE_UART10_TX_BIT 3 +#elif (RTE_UART10_TX_ID == 2) +#define RTE_UART10_TX 1 +#define RTE_UART10_TX_PORT GPIOG +#define RTE_UART10_TX_BIT 12 +#else +#error "Invalid UART10_TX Pin Configuration!" +#endif + +// UART10_RX Pin <0=>Not Used <1=>PE2 <2=>PG11 +#define RTE_UART10_RX_ID 0 +#if (RTE_UART10_RX_ID == 0) +#define RTE_UART10_RX 0 +#elif (RTE_UART10_RX_ID == 1) +#define RTE_UART10_RX 1 +#define RTE_UART10_RX_PORT GPIOE +#define RTE_UART10_RX_BIT 2 +#elif (RTE_UART10_RX_ID == 2) +#define RTE_UART10_RX 1 +#define RTE_UART10_RX_PORT GPIOG +#define RTE_UART10_RX_BIT 11 +#else +#error "Invalid UART10_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <3=>3 +// Selects DMA Stream (only Stream 0 or 3 can be used) +// Channel <5=>5 <9=>9 +// Selects DMA Channel (only Channel 5 or 9 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART10_RX_DMA 0 +#define RTE_UART10_RX_DMA_NUMBER 1 +#define RTE_UART10_RX_DMA_STREAM 6 +#define RTE_UART10_RX_DMA_CHANNEL 5 +#define RTE_UART10_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 <3=>5 +// Selects DMA Stream (only Stream 7 or 5 can be used) +// Channel <6=>6 <9=>9 +// Selects DMA Channel (only Channel 6 or 9 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART10_TX_DMA 0 +#define RTE_UART10_TX_DMA_NUMBER 1 +#define RTE_UART10_TX_DMA_STREAM 0 +#define RTE_UART10_TX_DMA_CHANNEL 5 +#define RTE_UART10_TX_DMA_PRIORITY 0 + +// + + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 <1=>PB8 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 <1=>PB9 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 9 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_STREAM 0 +#define RTE_I2C1_RX_DMA_CHANNEL 1 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <6=>6 <7=>7 +// Selects DMA Stream (only Stream 1 or 6 or 7 can be used) +// Channel <0=>0 <1=>1 +// Selects DMA Channel (only Channel 0 or 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_STREAM 6 +#define RTE_I2C1_TX_DMA_CHANNEL 1 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 + +// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOF +#define RTE_I2C2_SCL_BIT 1 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT GPIOH +#define RTE_I2C2_SCL_BIT 4 +#elif (RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 <3=>PB3 <4=>PB9 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOF +#define RTE_I2C2_SDA_BIT 0 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT GPIOH +#define RTE_I2C2_SDA_BIT 5 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#elif (RTE_I2C2_SDA_PORT_ID == 3) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 3 +#elif (RTE_I2C2_SDA_PORT_ID == 4) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 9 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 <3=>3 +// Selects DMA Stream (only Stream 2 or 3 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 0 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_STREAM 2 +#define RTE_I2C2_RX_DMA_CHANNEL 7 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 0 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_STREAM 7 +#define RTE_I2C2_TX_DMA_CHANNEL 7 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::CMSIS Driver:I2C +#define RTE_I2C3 0 + +// I2C3_SCL Pin <0=>PH7 <1=>PA8 +#define RTE_I2C3_SCL_PORT_ID 0 +#if (RTE_I2C3_SCL_PORT_ID == 0) +#define RTE_I2C3_SCL_PORT GPIOH +#define RTE_I2C3_SCL_BIT 7 +#elif (RTE_I2C3_SCL_PORT_ID == 1) +#define RTE_I2C3_SCL_PORT GPIOA +#define RTE_I2C3_SCL_BIT 8 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// I2C3_SDA Pin <0=>PH8 <1=>PC9 <2=>PB4 <3=>PB8 +#define RTE_I2C3_SDA_PORT_ID 0 +#if (RTE_I2C3_SDA_PORT_ID == 0) +#define RTE_I2C3_SDA_PORT GPIOH +#define RTE_I2C3_SDA_BIT 8 +#elif (RTE_I2C3_SDA_PORT_ID == 1) +#define RTE_I2C3_SDA_PORT GPIOC +#define RTE_I2C3_SDA_BIT 9 +#elif (RTE_I2C3_SDA_PORT_ID == 2) +#define RTE_I2C3_SDA_PORT GPIOB +#define RTE_I2C3_SDA_BIT 4 +#elif (RTE_I2C3_SDA_PORT_ID == 3) +#define RTE_I2C3_SDA_PORT GPIOB +#define RTE_I2C3_SDA_BIT 8 +#else +#error "Invalid I2C3_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <1=>1 <3=>3 +// Selects DMA Channel (only Channel 1 or 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_RX_DMA 0 +#define RTE_I2C3_RX_DMA_NUMBER 1 +#define RTE_I2C3_RX_DMA_STREAM 2 +#define RTE_I2C3_RX_DMA_CHANNEL 3 +#define RTE_I2C3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 <5=>5 +// Selects DMA Stream (only Stream 4 or 5 can be used) +// Channel <3=>3 <6=>6 +// Selects DMA Channel (only Channel 3 or 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_TX_DMA 0 +#define RTE_I2C3_TX_DMA_NUMBER 1 +#define RTE_I2C3_TX_DMA_STREAM 4 +#define RTE_I2C3_TX_DMA_CHANNEL 3 +#define RTE_I2C3_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI #define RTE_SPI1 1 - -// SPI1_MISO Pin <0=>Not Used <1=>PA6 <2=>PB4 + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 <2=>PB4 #define RTE_SPI1_MISO_PORT_ID 2 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO 0 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO 1 -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 2) -#define RTE_SPI1_MISO 1 -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>Not Used <1=>PA7 <2=>PB5 +#if (RTE_SPI1_MISO_PORT_ID == 0) +#define RTE_SPI1_MISO 0 +#elif (RTE_SPI1_MISO_PORT_ID == 1) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOA +#define RTE_SPI1_MISO_BIT 6 +#elif (RTE_SPI1_MISO_PORT_ID == 2) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOB +#define RTE_SPI1_MISO_BIT 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 <2=>PB5 #define RTE_SPI1_MOSI_PORT_ID 1 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI 0 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI 1 -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 2) -#define RTE_SPI1_MOSI 1 -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MOSI Pin Configuration!" -#endif - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 +#if (RTE_SPI1_MOSI_PORT_ID == 0) +#define RTE_SPI1_MOSI 0 +#elif (RTE_SPI1_MOSI_PORT_ID == 1) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOA +#define RTE_SPI1_MOSI_BIT 7 +#elif (RTE_SPI1_MOSI_PORT_ID == 2) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOB +#define RTE_SPI1_MOSI_BIT 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// SPI1_SCK Pin <0=>PA5 <1=>PB3 +#define RTE_SPI1_SCL_PORT_ID 0 +#if (RTE_SPI1_SCL_PORT_ID == 0) +#define RTE_SPI1_SCL_PORT GPIOA +#define RTE_SPI1_SCL_BIT 5 +#elif (RTE_SPI1_SCL_PORT_ID == 1) +#define RTE_SPI1_SCL_PORT GPIOB +#define RTE_SPI1_SCL_BIT 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 #define RTE_SPI1_NSS_PORT_ID 2 -#if (RTE_SPI1_NSS_PORT_ID == 0) -#define RTE_SPI1_NSS_PIN 0 -#elif (RTE_SPI1_NSS_PORT_ID == 1) -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIOA -#define RTE_SPI1_NSS_BIT 4 -#elif (RTE_SPI1_NSS_PORT_ID == 2) -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIOA -#define RTE_SPI1_NSS_BIT 15 -#else -#error "Invalid SPI1_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// +#if (RTE_SPI1_NSS_PORT_ID == 0) +#define RTE_SPI1_NSS_PIN 0 +#elif (RTE_SPI1_NSS_PORT_ID == 1) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOA +#define RTE_SPI1_NSS_BIT 4 +#elif (RTE_SPI1_NSS_PORT_ID == 2) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOA +#define RTE_SPI1_NSS_BIT 15 +#else +#error "Invalid SPI1_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// #define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <3=>3 <5=>5 -// Selects DMA Stream (only Stream 2 or 3 or 5 can be used) -// Channel <2=>2 <3=>3 -// Selects DMA Channel (only Channel 2 or 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// +#define RTE_SPI1_RX_DMA_NUMBER 2 +#define RTE_SPI1_RX_DMA_STREAM 0 +#define RTE_SPI1_RX_DMA_CHANNEL 3 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <3=>3 <5=>5 +// Selects DMA Stream (only Stream 2 or 3 or 5 can be used) +// Channel <2=>2 <3=>3 +// Selects DMA Channel (only Channel 2 or 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// #define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI -#define RTE_SPI2 0 - -// SPI2_MISO Pin <0=>Not Used <1=>PB14 <2=>PC2 <3=>PI2 <4=>PA12 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO 0 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 3) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 4) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOA -#define RTE_SPI2_MISO_BIT 12 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>Not Used <1=>PB15 <2=>PC3 <3=>PI3 <4=>PA10 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI 0 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 3) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 4) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOA -#define RTE_SPI2_MOSI_BIT 10 -#else -#error "Invalid SPI2_MOSI Pin Configuration!" -#endif - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PC7 <3=>PD3 <4=>PI1 <5=>PA9 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOC -#define RTE_SPI2_SCL_BIT 7 -#elif (RTE_SPI2_SCL_PORT_ID == 3) -#define RTE_SPI2_SCL_PORT GPIOD -#define RTE_SPI2_SCL_BIT 3 -#elif (RTE_SPI2_SCL_PORT_ID == 4) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#elif (RTE_SPI2_SCL_PORT_ID == 5) -#define RTE_SPI2_SCL_PORT GPIOA -#define RTE_SPI2_SCL_BIT 9 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_NSS Pin <0=>Not Used <1=>PB9 <2=>PB12 <3=>PI0 <4=>PA11 -#define RTE_SPI2_NSS_PORT_ID 0 -#if (RTE_SPI2_NSS_PORT_ID == 0) -#define RTE_SPI2_NSS_PIN 0 -#elif (RTE_SPI2_NSS_PORT_ID == 1) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOB -#define RTE_SPI2_NSS_BIT 9 -#elif (RTE_SPI2_NSS_PORT_ID == 2) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOB -#define RTE_SPI2_NSS_BIT 12 -#elif (RTE_SPI2_NSS_PORT_ID == 3) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOI -#define RTE_SPI2_NSS_BIT 0 -#elif (RTE_SPI2_NSS_PORT_ID == 4) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOA -#define RTE_SPI2_NSS_BIT 11 -#else -#error "Invalid SPI2_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 0 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 3 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 0 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 4 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI -#define RTE_SPI3 0 - -// SPI3_MISO Pin <0=>Not Used <1=>PB4 <2=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO 0 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO 1 -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 2) -#define RTE_SPI3_MISO 1 -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>Not Used <1=>PB5 <2=>PC12 <3=>PD6 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI 0 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 2) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#elif (RTE_SPI3_MOSI_PORT_ID == 3) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOD -#define RTE_SPI3_MOSI_BIT 6 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// SPI3_SCK Pin <0=>PB3 <1=>PB12 <2=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 12 -#elif (RTE_SPI3_SCL_PORT_ID == 2) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 -#define RTE_SPI3_NSS_PORT_ID 0 -#if (RTE_SPI3_NSS_PORT_ID == 0) -#define RTE_SPI3_NSS_PIN 0 -#elif (RTE_SPI3_NSS_PORT_ID == 1) -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIOA -#define RTE_SPI3_NSS_BIT 4 -#elif (RTE_SPI3_NSS_PORT_ID == 2) -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIOA -#define RTE_SPI3_NSS_BIT 15 -#else -#error "Invalid SPI3_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 0 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 0 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] -// Configuration settings for Driver_SPI4 in component ::CMSIS Driver:SPI -#define RTE_SPI4 0 - -// SPI4_MISO Pin <0=>Not Used <1=>PA11 <2=>PE5 <3=>PE13 -#define RTE_SPI4_MISO_PORT_ID 0 -#if (RTE_SPI4_MISO_PORT_ID == 0) -#define RTE_SPI4_MISO 0 -#elif (RTE_SPI4_MISO_PORT_ID == 1) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOA -#define RTE_SPI4_MISO_BIT 11 -#elif (RTE_SPI4_MISO_PORT_ID == 2) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOE -#define RTE_SPI4_MISO_BIT 5 -#elif (RTE_SPI4_MISO_PORT_ID == 3) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOE -#define RTE_SPI4_MISO_BIT 13 -#else -#error "Invalid SPI4_MISO Pin Configuration!" -#endif - -// SPI4_MOSI Pin <0=>Not Used <1=>PA1 <2=>PE6 <3=>PE14 -#define RTE_SPI4_MOSI_PORT_ID 0 -#if (RTE_SPI4_MOSI_PORT_ID == 0) -#define RTE_SPI4_MOSI 0 -#elif (RTE_SPI4_MOSI_PORT_ID == 1) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOA -#define RTE_SPI4_MOSI_BIT 1 -#elif (RTE_SPI4_MOSI_PORT_ID == 2) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOE -#define RTE_SPI4_MOSI_BIT 6 -#elif (RTE_SPI4_MOSI_PORT_ID == 3) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOE -#define RTE_SPI4_MOSI_BIT 14 -#else -#error "Invalid SPI4_MOSI Pin Configuration!" -#endif - -// SPI4_SCK Pin <0=>PB13 <1=>PE2 <2=>PE12 -#define RTE_SPI4_SCL_PORT_ID 0 -#if (RTE_SPI4_SCL_PORT_ID == 0) -#define RTE_SPI4_SCL_PORT GPIOB -#define RTE_SPI4_SCL_BIT 13 -#elif (RTE_SPI4_SCL_PORT_ID == 1) -#define RTE_SPI4_SCL_PORT GPIOE -#define RTE_SPI4_SCL_BIT 2 -#elif (RTE_SPI4_SCL_PORT_ID == 2) -#define RTE_SPI4_SCL_PORT GPIOE -#define RTE_SPI4_SCL_BIT 12 -#else -#error "Invalid SPI4_SCK Pin Configuration!" -#endif - -// SPI4_NSS Pin <0=>Not Used <1=>PB12 <2=>PE4 <3=>PE11 -#define RTE_SPI4_NSS_PORT_ID 0 -#if (RTE_SPI4_NSS_PORT_ID == 0) -#define RTE_SPI4_NSS_PIN 0 -#elif (RTE_SPI4_NSS_PORT_ID == 1) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOB -#define RTE_SPI4_NSS_BIT 12 -#elif (RTE_SPI4_NSS_PORT_ID == 2) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOE -#define RTE_SPI4_NSS_BIT 4 -#elif (RTE_SPI4_NSS_PORT_ID == 3) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOE -#define RTE_SPI4_NSS_BIT 11 -#else -#error "Invalid SPI4_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <3=>3 <4=>4 -// Selects DMA Stream (only Stream 0 or 3 can be used) -// Channel <4=>4 <5=>5 -// Selects DMA Channel (only Channel 4 or 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI4_RX_DMA 0 -#define RTE_SPI4_RX_DMA_NUMBER 1 -#define RTE_SPI4_RX_DMA_STREAM 0 -#define RTE_SPI4_RX_DMA_CHANNEL 0 -#define RTE_SPI4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <4=>4 -// Selects DMA Stream (only Stream 1 or 4 can be used) -// Channel <4=>4 <5=>5 -// Selects DMA Channel (only Channel 4 or 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI4_TX_DMA 0 -#define RTE_SPI4_TX_DMA_NUMBER 1 -#define RTE_SPI4_TX_DMA_STREAM 5 -#define RTE_SPI4_TX_DMA_CHANNEL 0 -#define RTE_SPI4_TX_DMA_PRIORITY 0 - -// - - -// SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] -// Configuration settings for Driver_SPI5 in component ::CMSIS Driver:SPI -#define RTE_SPI5 0 - -// SPI5_MISO Pin <0=>Not Used <1=>PA12 <2=>PE5 <3=>PE13 <4=>PF8 <5=>PH7 -#define RTE_SPI5_MISO_PORT_ID 0 -#if (RTE_SPI5_MISO_PORT_ID == 0) -#define RTE_SPI5_MISO 0 -#elif (RTE_SPI5_MISO_PORT_ID == 1) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOA -#define RTE_SPI5_MISO_BIT 12 -#elif (RTE_SPI5_MISO_PORT_ID == 2) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOE -#define RTE_SPI5_MISO_BIT 5 -#elif (RTE_SPI5_MISO_PORT_ID == 3) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOE -#define RTE_SPI5_MISO_BIT 13 -#elif (RTE_SPI5_MISO_PORT_ID == 4) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOF -#define RTE_SPI5_MISO_BIT 8 -#elif (RTE_SPI5_MISO_PORT_ID == 5) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOH -#define RTE_SPI5_MISO_BIT 7 -#else -#error "Invalid SPI5_MISO Pin Configuration!" -#endif - -// SPI5_MOSI Pin <0=>Not Used <1=>PA10 <2=>PB8 <3=>PE6 <4=>PE14 <5=>PF9 <6=>PF11 -#define RTE_SPI5_MOSI_PORT_ID 0 -#if (RTE_SPI5_MOSI_PORT_ID == 0) -#define RTE_SPI5_MOSI 0 -#elif (RTE_SPI5_MOSI_PORT_ID == 1) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOA -#define RTE_SPI5_MOSI_BIT 10 -#elif (RTE_SPI5_MOSI_PORT_ID == 2) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOB -#define RTE_SPI5_MOSI_BIT 8 -#elif (RTE_SPI5_MOSI_PORT_ID == 3) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOE -#define RTE_SPI5_MOSI_BIT 6 -#elif (RTE_SPI5_MOSI_PORT_ID == 4) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOE -#define RTE_SPI5_MOSI_BIT 14 -#elif (RTE_SPI5_MOSI_PORT_ID == 5) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOF -#define RTE_SPI5_MOSI_BIT 9 -#elif (RTE_SPI5_MOSI_PORT_ID == 6) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOF -#define RTE_SPI5_MOSI_BIT 11 -#else -#error "Invalid SPI5_MOSI Pin Configuration!" -#endif - -// SPI5_SCK Pin <0=>PB0 <1=>PE2 <2=>PE12 <3=>PF7 <4=>PH6 -#define RTE_SPI5_SCL_PORT_ID 0 -#if (RTE_SPI5_SCL_PORT_ID == 0) -#define RTE_SPI5_SCL_PORT GPIOB -#define RTE_SPI5_SCL_BIT 0 -#elif (RTE_SPI5_SCL_PORT_ID == 1) -#define RTE_SPI5_SCL_PORT GPIOE -#define RTE_SPI5_SCL_BIT 2 -#elif (RTE_SPI5_SCL_PORT_ID == 2) -#define RTE_SPI5_SCL_PORT GPIOE -#define RTE_SPI5_SCL_BIT 12 -#elif (RTE_SPI5_SCL_PORT_ID == 3) -#define RTE_SPI5_SCL_PORT GPIOF -#define RTE_SPI5_SCL_BIT 7 -#elif (RTE_SPI5_SCL_PORT_ID == 4) -#define RTE_SPI5_SCL_PORT GPIOH -#define RTE_SPI5_SCL_BIT 6 -#else -#error "Invalid SPI5_SCK Pin Configuration!" -#endif - -// SPI5_NSS Pin <0=>Not Used <1=>PB1 <2=>PE4 <3=>PE11 <4=>PF6 <5=>PH5 -#define RTE_SPI5_NSS_PORT_ID 0 -#if (RTE_SPI5_NSS_PORT_ID == 0) -#define RTE_SPI5_NSS_PIN 0 -#elif (RTE_SPI5_NSS_PORT_ID == 1) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOB -#define RTE_SPI5_NSS_BIT 1 -#elif (RTE_SPI5_NSS_PORT_ID == 2) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOE -#define RTE_SPI5_NSS_BIT 4 -#elif (RTE_SPI5_NSS_PORT_ID == 3) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOE -#define RTE_SPI5_NSS_BIT 11 -#elif (RTE_SPI5_NSS_PORT_ID == 4) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOF -#define RTE_SPI5_NSS_BIT 6 -#elif (RTE_SPI5_NSS_PORT_ID == 5) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOH -#define RTE_SPI5_NSS_BIT 5 -#else -#error "Invalid SPI5_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <2=>2 <7=>7 -// Selects DMA Channel (only Channel 2 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI5_RX_DMA 0 -#define RTE_SPI5_RX_DMA_NUMBER 2 -#define RTE_SPI5_RX_DMA_STREAM 3 -#define RTE_SPI5_RX_DMA_CHANNEL 2 -#define RTE_SPI5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <4=>4 <5=>5 <6=>6 -// Selects DMA Stream (only Stream 4 or 6 can be used) -// Channel <2=>2 <5=>5 <7=>7 -// Selects DMA Channel (only Channel 2 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI5_TX_DMA 0 -#define RTE_SPI5_TX_DMA_NUMBER 2 -#define RTE_SPI5_TX_DMA_STREAM 4 -#define RTE_SPI5_TX_DMA_CHANNEL 2 -#define RTE_SPI5_TX_DMA_PRIORITY 0 - -// - - -// SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] -// Configuration settings for Driver_SPI6 in component ::CMSIS Driver:SPI -#define RTE_SPI6 0 - -// SPI6_MISO Pin <0=>Not Used <1=>PG12 -#define RTE_SPI6_MISO_PORT_ID 0 -#if (RTE_SPI6_MISO_PORT_ID == 0) -#define RTE_SPI6_MISO 0 -#elif (RTE_SPI6_MISO_PORT_ID == 1) -#define RTE_SPI6_MISO 1 -#define RTE_SPI6_MISO_PORT GPIOG -#define RTE_SPI6_MISO_BIT 12 -#else -#error "Invalid SPI6_MISO Pin Configuration!" -#endif - -// SPI6_MOSI Pin <0=>Not Used <1=>PG14 -#define RTE_SPI6_MOSI_PORT_ID 0 -#if (RTE_SPI6_MOSI_PORT_ID == 0) -#define RTE_SPI6_MOSI 0 -#elif (RTE_SPI6_MOSI_PORT_ID == 1) -#define RTE_SPI6_MOSI 1 -#define RTE_SPI6_MOSI_PORT GPIOG -#define RTE_SPI6_MOSI_BIT 14 -#else -#error "Invalid SPI6_MOSI Pin Configuration!" -#endif - -// SPI6_SCK Pin <0=>PG13 -#define RTE_SPI6_SCL_PORT_ID 0 -#if (RTE_SPI6_SCL_PORT_ID == 0) -#define RTE_SPI6_SCL_PORT GPIOG -#define RTE_SPI6_SCL_BIT 13 -#else -#error "Invalid SPI6_SCK Pin Configuration!" -#endif - -// SPI6_NSS Pin <0=>Not Used <1=>PG8 -#define RTE_SPI6_NSS_PORT_ID 0 -#if (RTE_SPI6_NSS_PORT_ID == 0) -#define RTE_SPI6_NSS_PIN 0 -#elif (RTE_SPI6_NSS_PORT_ID == 1) -#define RTE_SPI6_NSS_PIN 1 -#define RTE_SPI6_NSS_PORT GPIOG -#define RTE_SPI6_NSS_BIT 8 -#else -#error "Invalid SPI6_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI6_RX_DMA 0 -#define RTE_SPI6_RX_DMA_NUMBER 2 -#define RTE_SPI6_RX_DMA_STREAM 6 -#define RTE_SPI6_RX_DMA_CHANNEL 1 -#define RTE_SPI6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI6_TX_DMA 0 -#define RTE_SPI6_TX_DMA_NUMBER 2 -#define RTE_SPI6_TX_DMA_STREAM 5 -#define RTE_SPI6_TX_DMA_CHANNEL 1 -#define RTE_SPI6_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI -#define RTE_SDIO 0 - -// SDIO Peripheral Bus -// SDIO_CK Pin <0=>PC12 <1=>PB15 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) - #define RTE_SDIO_CK_PORT GPIOC - #define RTE_SDIO_CK_PIN GPIO_PIN_12 -#elif (RTE_SDIO_CK_PORT_ID == 1) - #define RTE_SDIO_CK_PORT GPIOB - #define RTE_SDIO_CK_PIN GPIO_PIN_15 -#else - #error "Invalid SD_CLK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 <1=>PA6 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) - #define RTE_SDIO_CMD_PORT GPIOD - #define RTE_SDIO_CMD_PIN GPIO_PIN_2 -#elif (RTE_SDIO_CMD_PORT_ID == 1) - #define RTE_SDIO_CMD_PORT GPIOA - #define RTE_SDIO_CMD_PIN GPIO_PIN_6 -#else - #error "Invalid SD_CMD Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 <1=>PB4 <2=>PB6 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) - #define RTE_SDIO_D0_PORT GPIOC - #define RTE_SDIO_D0_PIN GPIO_PIN_8 -#elif (RTE_SDIO_D0_PORT_ID == 1) - #define RTE_SDIO_D0_PORT GPIOB - #define RTE_SDIO_D0_PIN GPIO_PIN_4 -#elif (RTE_SDIO_D0_PORT_ID == 2) - #define RTE_SDIO_D0_PORT GPIOB - #define RTE_SDIO_D0_PIN GPIO_PIN_6 -#else - #error "Invalid SD_DAT0 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -#define RTE_SDIO_BUS_WIDTH_4 1 -// SDIO_D1 Pin <0=>PC9 <1=>PA8 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) - #define RTE_SDIO_D1_PORT GPIOC - #define RTE_SDIO_D1_PIN GPIO_PIN_9 -#elif (RTE_SDIO_D1_PORT_ID == 1) - #define RTE_SDIO_D1_PORT GPIOA - #define RTE_SDIO_D1_PIN GPIO_PIN_8 -#else - #error "Invalid SD_DAT1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 <1=>PA9 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) - #define RTE_SDIO_D2_PORT GPIOC - #define RTE_SDIO_D2_PIN GPIO_PIN_10 -#elif (RTE_SDIO_D2_PORT_ID == 1) - #define RTE_SDIO_D2_PORT GPIOA - #define RTE_SDIO_D2_PIN GPIO_PIN_9 -#else - #error "Invalid SD_DAT2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 <1=>PB5 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) - #define RTE_SDIO_D3_PORT GPIOC - #define RTE_SDIO_D3_PIN GPIO_PIN_11 -#elif (RTE_SDIO_D3_PORT_ID == 1) - #define RTE_SDIO_D3_PORT GPIOB - #define RTE_SDIO_D3_PIN GPIO_PIN_5 -#else - #error "Invalid SD_DAT3 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -// SDIO_D[4 .. 7] -#define RTE_SDIO_BUS_WIDTH_8 0 -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) - #define RTE_SDIO_D4_PORT GPIOB - #define RTE_SDIO_D4_PIN GPIO_PIN_8 -#else - #error "Invalid SD_DAT4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) - #define RTE_SDIO_D5_PORT GPIOB - #define RTE_SDIO_D5_PIN GPIO_PIN_9 -#else - #error "Invalid SD_DAT5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 <1=>PB14 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) - #define RTE_SDIO_D6_PORT GPIOC - #define RTE_SDIO_D6_PIN GPIO_PIN_6 -#elif (RTE_SDIO_D6_PORT_ID == 1) - #define RTE_SDIO_D6_PORT GPIOB - #define RTE_SDIO_D6_PIN GPIO_PIN_14 -#else - #error "Invalid SD_DAT6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 <1=>PB10 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) - #define RTE_SDIO_D7_PORT GPIOC - #define RTE_SDIO_D7_PIN GPIO_PIN_7 -#elif (RTE_SDIO_D7_PORT_ID == 1) - #define RTE_SDIO_D7_PORT GPIOB - #define RTE_SDIO_D7_PIN GPIO_PIN_10 -#else - #error "Invalid SD_DAT7 Pin Configuration!" -#endif -// SDIO_D[4 .. 7] -// SDIO Peripheral Bus - -// Card Detect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN_EN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_PIN 15 - -// Write Protect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_EN 0 -#define RTE_SDIO_WP_ACTIVE 1 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_PIN 10 - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_RX_DMA 1 -#define RTE_SDIO_RX_DMA_NUMBER 2 -#define RTE_SDIO_RX_DMA_STREAM 3 -#define RTE_SDIO_RX_DMA_CHANNEL 4 -#define RTE_SDIO_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_TX_DMA 1 -#define RTE_SDIO_TX_DMA_NUMBER 2 -#define RTE_SDIO_TX_DMA_STREAM 6 -#define RTE_SDIO_TX_DMA_CHANNEL 4 -#define RTE_SDIO_TX_DMA_PRIORITY 0 - -// - - -// CAN1 (Controller Area Network 1) [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN -#define RTE_CAN1 0 - -// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 <3=>PI9 <4=>PG0 -#define RTE_CAN1_RX_PORT_ID 0 -#if (RTE_CAN1_RX_PORT_ID == 0) -#define RTE_CAN1_RX_PORT GPIOA -#define RTE_CAN1_RX_BIT GPIO_PIN_11 -#elif (RTE_CAN1_RX_PORT_ID == 1) -#define RTE_CAN1_RX_PORT GPIOB -#define RTE_CAN1_RX_BIT GPIO_PIN_8 -#elif (RTE_CAN1_RX_PORT_ID == 2) -#define RTE_CAN1_RX_PORT GPIOD -#define RTE_CAN1_RX_BIT GPIO_PIN_0 -#elif (RTE_CAN1_RX_PORT_ID == 3) -#define RTE_CAN1_RX_PORT GPIOI -#define RTE_CAN1_RX_BIT GPIO_PIN_9 -#elif (RTE_CAN1_RX_PORT_ID == 4) -#define RTE_CAN1_RX_PORT GPIOG -#define RTE_CAN1_RX_BIT GPIO_PIN_0 -#else -#error "Invalid CAN1_RX Pin Configuration!" -#endif - -// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 <3=>PH13 <4=>PG1 -#define RTE_CAN1_TX_PORT_ID 0 -#if (RTE_CAN1_TX_PORT_ID == 0) -#define RTE_CAN1_TX_PORT GPIOA -#define RTE_CAN1_TX_BIT GPIO_PIN_12 -#elif (RTE_CAN1_TX_PORT_ID == 1) -#define RTE_CAN1_TX_PORT GPIOB -#define RTE_CAN1_TX_BIT GPIO_PIN_9 -#elif (RTE_CAN1_TX_PORT_ID == 2) -#define RTE_CAN1_TX_PORT GPIOD -#define RTE_CAN1_TX_BIT GPIO_PIN_1 -#elif (RTE_CAN1_TX_PORT_ID == 3) -#define RTE_CAN1_TX_PORT GPIOH -#define RTE_CAN1_TX_BIT GPIO_PIN_13 -#elif (RTE_CAN1_TX_PORT_ID == 4) -#define RTE_CAN1_TX_PORT GPIOG -#define RTE_CAN1_TX_BIT GPIO_PIN_1 -#else -#error "Invalid CAN1_TX Pin Configuration!" -#endif - -// - - -// CAN2 (Controller Area Network 2) [Driver_CAN2] -// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN -#define RTE_CAN2 0 - -// CAN2_RX Pin <0=>PB5 <1=>PB12 <2=>PG11 -#define RTE_CAN2_RX_PORT_ID 0 -#if (RTE_CAN2_RX_PORT_ID == 0) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT GPIO_PIN_5 -#elif (RTE_CAN2_RX_PORT_ID == 1) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT GPIO_PIN_12 -#elif (RTE_CAN2_RX_PORT_ID == 2) -#define RTE_CAN2_RX_PORT GPIOG -#define RTE_CAN2_RX_BIT GPIO_PIN_11 -#else -#error "Invalid CAN2_RX Pin Configuration!" -#endif - -// CAN2_TX Pin <0=>PB6 <1=>PB13 <2=>PG12 -#define RTE_CAN2_TX_PORT_ID 0 -#if (RTE_CAN2_TX_PORT_ID == 0) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT GPIO_PIN_6 -#elif (RTE_CAN2_TX_PORT_ID == 1) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT GPIO_PIN_13 -#elif (RTE_CAN2_TX_PORT_ID == 2) -#define RTE_CAN2_TX_PORT GPIOG -#define RTE_CAN2_TX_BIT GPIO_PIN_12 -#else -#error "Invalid CAN2_TX Pin Configuration!" -#endif - -// - - -// CAN3 (Controller Area Network 3) [Driver_CAN3] -// Configuration settings for Driver_CAN3 in component ::CMSIS Driver:CAN -// Available only on STM32F413xx and STM32F423xx device series -#define RTE_CAN3 0 - -// CAN3_RX Pin <0=>PA8 <1=>PB3 -#define RTE_CAN3_RX_PORT_ID 0 -#if (RTE_CAN3_RX_PORT_ID == 0) -#define RTE_CAN3_RX_PORT GPIOA -#define RTE_CAN3_RX_BIT GPIO_PIN_8 -#elif (RTE_CAN3_RX_PORT_ID == 1) -#define RTE_CAN3_RX_PORT GPIOB -#define RTE_CAN3_RX_BIT GPIO_PIN_3 -#else -#error "Invalid CAN3_RX Pin Configuration!" -#endif - -// CAN3_TX Pin <0=>PA15 <1=>PB4 -#define RTE_CAN3_TX_PORT_ID 0 -#if (RTE_CAN3_TX_PORT_ID == 0) -#define RTE_CAN3_TX_PORT GPIOA -#define RTE_CAN3_TX_BIT GPIO_PIN_15 -#elif (RTE_CAN3_TX_PORT_ID == 1) -#define RTE_CAN3_TX_PORT GPIOB -#define RTE_CAN3_TX_BIT GPIO_PIN_4 -#else -#error "Invalid CAN3_TX Pin Configuration!" -#endif - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC -#define RTE_ETH 0 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 1 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RX_ER_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 0 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 0 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 0 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 0 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::CMSIS Driver:USB Device - -#define RTE_USB_OTG_FS_DEVICE 1 - -// VBUS Sensing Pin -// Enable or disable VBUS sensing -#define RTE_OTG_FS_VBUS_SENSING_PIN 1 -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::CMSIS Driver:USB Host - -#define RTE_USB_OTG_FS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC3 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 3 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::CMSIS Driver:USB Device - -#define RTE_USB_OTG_HS_DEVICE 0 - -// VBUS Sensing Pin -// Enable or disable VBUS sensing -// Relevant only if PHY Interface On-chip full-speed PHY is selected -#define RTE_OTG_HS_VBUS_SENSING_PIN 0 -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::CMSIS Driver:USB Host -#define RTE_USB_OTG_HS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 0 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(2) -#define RTE_OTG_HS_OC_BIT 5 -// - -// DMA -// Use dedicated DMA for transfers -// If DMA is used all USB transfer data buffers have to be 4-byte aligned. -#define RTE_OTG_HS_DMA 0 - -// - - -#endif /* __RTE_DEVICE_H */ +#define RTE_SPI1_TX_DMA_NUMBER 2 +#define RTE_SPI1_TX_DMA_STREAM 5 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 <2=>PC2 <3=>PI2 <4=>PA12 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#elif (RTE_SPI2_MISO_PORT_ID == 2) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOC +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 3) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOI +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 4) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOA +#define RTE_SPI2_MISO_BIT 12 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 <2=>PC3 <3=>PI3 <4=>PA10 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#elif (RTE_SPI2_MOSI_PORT_ID == 2) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 3) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOI +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 4) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOA +#define RTE_SPI2_MOSI_BIT 10 +#else +#error "Invalid SPI2_MOSI Pin Configuration!" +#endif + +// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PC7 <3=>PD3 <4=>PI1 <5=>PA9 +#define RTE_SPI2_SCL_PORT_ID 0 +#if (RTE_SPI2_SCL_PORT_ID == 0) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 10 +#elif (RTE_SPI2_SCL_PORT_ID == 1) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 13 +#elif (RTE_SPI2_SCL_PORT_ID == 2) +#define RTE_SPI2_SCL_PORT GPIOC +#define RTE_SPI2_SCL_BIT 7 +#elif (RTE_SPI2_SCL_PORT_ID == 3) +#define RTE_SPI2_SCL_PORT GPIOD +#define RTE_SPI2_SCL_BIT 3 +#elif (RTE_SPI2_SCL_PORT_ID == 4) +#define RTE_SPI2_SCL_PORT GPIOI +#define RTE_SPI2_SCL_BIT 1 +#elif (RTE_SPI2_SCL_PORT_ID == 5) +#define RTE_SPI2_SCL_PORT GPIOA +#define RTE_SPI2_SCL_BIT 9 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_NSS Pin <0=>Not Used <1=>PB9 <2=>PB12 <3=>PI0 <4=>PA11 +#define RTE_SPI2_NSS_PORT_ID 0 +#if (RTE_SPI2_NSS_PORT_ID == 0) +#define RTE_SPI2_NSS_PIN 0 +#elif (RTE_SPI2_NSS_PORT_ID == 1) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 9 +#elif (RTE_SPI2_NSS_PORT_ID == 2) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 12 +#elif (RTE_SPI2_NSS_PORT_ID == 3) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOI +#define RTE_SPI2_NSS_BIT 0 +#elif (RTE_SPI2_NSS_PORT_ID == 4) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOA +#define RTE_SPI2_NSS_BIT 11 +#else +#error "Invalid SPI2_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_STREAM 3 +#define RTE_SPI2_RX_DMA_CHANNEL 0 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_STREAM 4 +#define RTE_SPI2_TX_DMA_CHANNEL 0 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 <2=>PC11 +#define RTE_SPI3_MISO_PORT_ID 0 +#if (RTE_SPI3_MISO_PORT_ID == 0) +#define RTE_SPI3_MISO 0 +#elif (RTE_SPI3_MISO_PORT_ID == 1) +#define RTE_SPI3_MISO 1 +#define RTE_SPI3_MISO_PORT GPIOB +#define RTE_SPI3_MISO_BIT 4 +#elif (RTE_SPI3_MISO_PORT_ID == 2) +#define RTE_SPI3_MISO 1 +#define RTE_SPI3_MISO_PORT GPIOC +#define RTE_SPI3_MISO_BIT 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI Pin <0=>Not Used <1=>PB5 <2=>PC12 <3=>PD6 +#define RTE_SPI3_MOSI_PORT_ID 0 +#if (RTE_SPI3_MOSI_PORT_ID == 0) +#define RTE_SPI3_MOSI 0 +#elif (RTE_SPI3_MOSI_PORT_ID == 1) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 5 +#elif (RTE_SPI3_MOSI_PORT_ID == 2) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOC +#define RTE_SPI3_MOSI_BIT 12 +#elif (RTE_SPI3_MOSI_PORT_ID == 3) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOD +#define RTE_SPI3_MOSI_BIT 6 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3_SCK Pin <0=>PB3 <1=>PB12 <2=>PC10 +#define RTE_SPI3_SCL_PORT_ID 0 +#if (RTE_SPI3_SCL_PORT_ID == 0) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 3 +#elif (RTE_SPI3_SCL_PORT_ID == 1) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 12 +#elif (RTE_SPI3_SCL_PORT_ID == 2) +#define RTE_SPI3_SCL_PORT GPIOC +#define RTE_SPI3_SCL_BIT 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 +#define RTE_SPI3_NSS_PORT_ID 0 +#if (RTE_SPI3_NSS_PORT_ID == 0) +#define RTE_SPI3_NSS_PIN 0 +#elif (RTE_SPI3_NSS_PORT_ID == 1) +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIOA +#define RTE_SPI3_NSS_BIT 4 +#elif (RTE_SPI3_NSS_PORT_ID == 2) +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIOA +#define RTE_SPI3_NSS_BIT 15 +#else +#error "Invalid SPI3_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 1 +#define RTE_SPI3_RX_DMA_STREAM 0 +#define RTE_SPI3_RX_DMA_CHANNEL 0 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 1 +#define RTE_SPI3_TX_DMA_STREAM 5 +#define RTE_SPI3_TX_DMA_CHANNEL 0 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] +// Configuration settings for Driver_SPI4 in component ::CMSIS Driver:SPI +#define RTE_SPI4 0 + +// SPI4_MISO Pin <0=>Not Used <1=>PA11 <2=>PE5 <3=>PE13 +#define RTE_SPI4_MISO_PORT_ID 0 +#if (RTE_SPI4_MISO_PORT_ID == 0) +#define RTE_SPI4_MISO 0 +#elif (RTE_SPI4_MISO_PORT_ID == 1) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOA +#define RTE_SPI4_MISO_BIT 11 +#elif (RTE_SPI4_MISO_PORT_ID == 2) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOE +#define RTE_SPI4_MISO_BIT 5 +#elif (RTE_SPI4_MISO_PORT_ID == 3) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOE +#define RTE_SPI4_MISO_BIT 13 +#else +#error "Invalid SPI4_MISO Pin Configuration!" +#endif + +// SPI4_MOSI Pin <0=>Not Used <1=>PA1 <2=>PE6 <3=>PE14 +#define RTE_SPI4_MOSI_PORT_ID 0 +#if (RTE_SPI4_MOSI_PORT_ID == 0) +#define RTE_SPI4_MOSI 0 +#elif (RTE_SPI4_MOSI_PORT_ID == 1) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOA +#define RTE_SPI4_MOSI_BIT 1 +#elif (RTE_SPI4_MOSI_PORT_ID == 2) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOE +#define RTE_SPI4_MOSI_BIT 6 +#elif (RTE_SPI4_MOSI_PORT_ID == 3) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOE +#define RTE_SPI4_MOSI_BIT 14 +#else +#error "Invalid SPI4_MOSI Pin Configuration!" +#endif + +// SPI4_SCK Pin <0=>PB13 <1=>PE2 <2=>PE12 +#define RTE_SPI4_SCL_PORT_ID 0 +#if (RTE_SPI4_SCL_PORT_ID == 0) +#define RTE_SPI4_SCL_PORT GPIOB +#define RTE_SPI4_SCL_BIT 13 +#elif (RTE_SPI4_SCL_PORT_ID == 1) +#define RTE_SPI4_SCL_PORT GPIOE +#define RTE_SPI4_SCL_BIT 2 +#elif (RTE_SPI4_SCL_PORT_ID == 2) +#define RTE_SPI4_SCL_PORT GPIOE +#define RTE_SPI4_SCL_BIT 12 +#else +#error "Invalid SPI4_SCK Pin Configuration!" +#endif + +// SPI4_NSS Pin <0=>Not Used <1=>PB12 <2=>PE4 <3=>PE11 +#define RTE_SPI4_NSS_PORT_ID 0 +#if (RTE_SPI4_NSS_PORT_ID == 0) +#define RTE_SPI4_NSS_PIN 0 +#elif (RTE_SPI4_NSS_PORT_ID == 1) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOB +#define RTE_SPI4_NSS_BIT 12 +#elif (RTE_SPI4_NSS_PORT_ID == 2) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOE +#define RTE_SPI4_NSS_BIT 4 +#elif (RTE_SPI4_NSS_PORT_ID == 3) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOE +#define RTE_SPI4_NSS_BIT 11 +#else +#error "Invalid SPI4_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <3=>3 <4=>4 +// Selects DMA Stream (only Stream 0 or 3 can be used) +// Channel <4=>4 <5=>5 +// Selects DMA Channel (only Channel 4 or 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI4_RX_DMA 0 +#define RTE_SPI4_RX_DMA_NUMBER 1 +#define RTE_SPI4_RX_DMA_STREAM 0 +#define RTE_SPI4_RX_DMA_CHANNEL 0 +#define RTE_SPI4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <4=>4 +// Selects DMA Stream (only Stream 1 or 4 can be used) +// Channel <4=>4 <5=>5 +// Selects DMA Channel (only Channel 4 or 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI4_TX_DMA 0 +#define RTE_SPI4_TX_DMA_NUMBER 1 +#define RTE_SPI4_TX_DMA_STREAM 5 +#define RTE_SPI4_TX_DMA_CHANNEL 0 +#define RTE_SPI4_TX_DMA_PRIORITY 0 + +// + + +// SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] +// Configuration settings for Driver_SPI5 in component ::CMSIS Driver:SPI +#define RTE_SPI5 0 + +// SPI5_MISO Pin <0=>Not Used <1=>PA12 <2=>PE5 <3=>PE13 <4=>PF8 <5=>PH7 +#define RTE_SPI5_MISO_PORT_ID 0 +#if (RTE_SPI5_MISO_PORT_ID == 0) +#define RTE_SPI5_MISO 0 +#elif (RTE_SPI5_MISO_PORT_ID == 1) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOA +#define RTE_SPI5_MISO_BIT 12 +#elif (RTE_SPI5_MISO_PORT_ID == 2) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOE +#define RTE_SPI5_MISO_BIT 5 +#elif (RTE_SPI5_MISO_PORT_ID == 3) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOE +#define RTE_SPI5_MISO_BIT 13 +#elif (RTE_SPI5_MISO_PORT_ID == 4) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOF +#define RTE_SPI5_MISO_BIT 8 +#elif (RTE_SPI5_MISO_PORT_ID == 5) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOH +#define RTE_SPI5_MISO_BIT 7 +#else +#error "Invalid SPI5_MISO Pin Configuration!" +#endif + +// SPI5_MOSI Pin <0=>Not Used <1=>PA10 <2=>PB8 <3=>PE6 <4=>PE14 <5=>PF9 <6=>PF11 +#define RTE_SPI5_MOSI_PORT_ID 0 +#if (RTE_SPI5_MOSI_PORT_ID == 0) +#define RTE_SPI5_MOSI 0 +#elif (RTE_SPI5_MOSI_PORT_ID == 1) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOA +#define RTE_SPI5_MOSI_BIT 10 +#elif (RTE_SPI5_MOSI_PORT_ID == 2) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOB +#define RTE_SPI5_MOSI_BIT 8 +#elif (RTE_SPI5_MOSI_PORT_ID == 3) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOE +#define RTE_SPI5_MOSI_BIT 6 +#elif (RTE_SPI5_MOSI_PORT_ID == 4) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOE +#define RTE_SPI5_MOSI_BIT 14 +#elif (RTE_SPI5_MOSI_PORT_ID == 5) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOF +#define RTE_SPI5_MOSI_BIT 9 +#elif (RTE_SPI5_MOSI_PORT_ID == 6) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOF +#define RTE_SPI5_MOSI_BIT 11 +#else +#error "Invalid SPI5_MOSI Pin Configuration!" +#endif + +// SPI5_SCK Pin <0=>PB0 <1=>PE2 <2=>PE12 <3=>PF7 <4=>PH6 +#define RTE_SPI5_SCL_PORT_ID 0 +#if (RTE_SPI5_SCL_PORT_ID == 0) +#define RTE_SPI5_SCL_PORT GPIOB +#define RTE_SPI5_SCL_BIT 0 +#elif (RTE_SPI5_SCL_PORT_ID == 1) +#define RTE_SPI5_SCL_PORT GPIOE +#define RTE_SPI5_SCL_BIT 2 +#elif (RTE_SPI5_SCL_PORT_ID == 2) +#define RTE_SPI5_SCL_PORT GPIOE +#define RTE_SPI5_SCL_BIT 12 +#elif (RTE_SPI5_SCL_PORT_ID == 3) +#define RTE_SPI5_SCL_PORT GPIOF +#define RTE_SPI5_SCL_BIT 7 +#elif (RTE_SPI5_SCL_PORT_ID == 4) +#define RTE_SPI5_SCL_PORT GPIOH +#define RTE_SPI5_SCL_BIT 6 +#else +#error "Invalid SPI5_SCK Pin Configuration!" +#endif + +// SPI5_NSS Pin <0=>Not Used <1=>PB1 <2=>PE4 <3=>PE11 <4=>PF6 <5=>PH5 +#define RTE_SPI5_NSS_PORT_ID 0 +#if (RTE_SPI5_NSS_PORT_ID == 0) +#define RTE_SPI5_NSS_PIN 0 +#elif (RTE_SPI5_NSS_PORT_ID == 1) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOB +#define RTE_SPI5_NSS_BIT 1 +#elif (RTE_SPI5_NSS_PORT_ID == 2) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOE +#define RTE_SPI5_NSS_BIT 4 +#elif (RTE_SPI5_NSS_PORT_ID == 3) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOE +#define RTE_SPI5_NSS_BIT 11 +#elif (RTE_SPI5_NSS_PORT_ID == 4) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOF +#define RTE_SPI5_NSS_BIT 6 +#elif (RTE_SPI5_NSS_PORT_ID == 5) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOH +#define RTE_SPI5_NSS_BIT 5 +#else +#error "Invalid SPI5_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <2=>2 <7=>7 +// Selects DMA Channel (only Channel 2 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI5_RX_DMA 0 +#define RTE_SPI5_RX_DMA_NUMBER 2 +#define RTE_SPI5_RX_DMA_STREAM 3 +#define RTE_SPI5_RX_DMA_CHANNEL 2 +#define RTE_SPI5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <4=>4 <5=>5 <6=>6 +// Selects DMA Stream (only Stream 4 or 6 can be used) +// Channel <2=>2 <5=>5 <7=>7 +// Selects DMA Channel (only Channel 2 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI5_TX_DMA 0 +#define RTE_SPI5_TX_DMA_NUMBER 2 +#define RTE_SPI5_TX_DMA_STREAM 4 +#define RTE_SPI5_TX_DMA_CHANNEL 2 +#define RTE_SPI5_TX_DMA_PRIORITY 0 + +// + + +// SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] +// Configuration settings for Driver_SPI6 in component ::CMSIS Driver:SPI +#define RTE_SPI6 0 + +// SPI6_MISO Pin <0=>Not Used <1=>PG12 +#define RTE_SPI6_MISO_PORT_ID 0 +#if (RTE_SPI6_MISO_PORT_ID == 0) +#define RTE_SPI6_MISO 0 +#elif (RTE_SPI6_MISO_PORT_ID == 1) +#define RTE_SPI6_MISO 1 +#define RTE_SPI6_MISO_PORT GPIOG +#define RTE_SPI6_MISO_BIT 12 +#else +#error "Invalid SPI6_MISO Pin Configuration!" +#endif + +// SPI6_MOSI Pin <0=>Not Used <1=>PG14 +#define RTE_SPI6_MOSI_PORT_ID 0 +#if (RTE_SPI6_MOSI_PORT_ID == 0) +#define RTE_SPI6_MOSI 0 +#elif (RTE_SPI6_MOSI_PORT_ID == 1) +#define RTE_SPI6_MOSI 1 +#define RTE_SPI6_MOSI_PORT GPIOG +#define RTE_SPI6_MOSI_BIT 14 +#else +#error "Invalid SPI6_MOSI Pin Configuration!" +#endif + +// SPI6_SCK Pin <0=>PG13 +#define RTE_SPI6_SCL_PORT_ID 0 +#if (RTE_SPI6_SCL_PORT_ID == 0) +#define RTE_SPI6_SCL_PORT GPIOG +#define RTE_SPI6_SCL_BIT 13 +#else +#error "Invalid SPI6_SCK Pin Configuration!" +#endif + +// SPI6_NSS Pin <0=>Not Used <1=>PG8 +#define RTE_SPI6_NSS_PORT_ID 0 +#if (RTE_SPI6_NSS_PORT_ID == 0) +#define RTE_SPI6_NSS_PIN 0 +#elif (RTE_SPI6_NSS_PORT_ID == 1) +#define RTE_SPI6_NSS_PIN 1 +#define RTE_SPI6_NSS_PORT GPIOG +#define RTE_SPI6_NSS_BIT 8 +#else +#error "Invalid SPI6_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI6_RX_DMA 0 +#define RTE_SPI6_RX_DMA_NUMBER 2 +#define RTE_SPI6_RX_DMA_STREAM 6 +#define RTE_SPI6_RX_DMA_CHANNEL 1 +#define RTE_SPI6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI6_TX_DMA 0 +#define RTE_SPI6_TX_DMA_NUMBER 2 +#define RTE_SPI6_TX_DMA_STREAM 5 +#define RTE_SPI6_TX_DMA_CHANNEL 1 +#define RTE_SPI6_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 <1=>PB15 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN GPIO_PIN_12 +#elif (RTE_SDIO_CK_PORT_ID == 1) + #define RTE_SDIO_CK_PORT GPIOB + #define RTE_SDIO_CK_PIN GPIO_PIN_15 +#else + #error "Invalid SD_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 <1=>PA6 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN GPIO_PIN_2 +#elif (RTE_SDIO_CMD_PORT_ID == 1) + #define RTE_SDIO_CMD_PORT GPIOA + #define RTE_SDIO_CMD_PIN GPIO_PIN_6 +#else + #error "Invalid SD_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 <1=>PB4 <2=>PB6 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN GPIO_PIN_8 +#elif (RTE_SDIO_D0_PORT_ID == 1) + #define RTE_SDIO_D0_PORT GPIOB + #define RTE_SDIO_D0_PIN GPIO_PIN_4 +#elif (RTE_SDIO_D0_PORT_ID == 2) + #define RTE_SDIO_D0_PORT GPIOB + #define RTE_SDIO_D0_PIN GPIO_PIN_6 +#else + #error "Invalid SD_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 <1=>PA8 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN GPIO_PIN_9 +#elif (RTE_SDIO_D1_PORT_ID == 1) + #define RTE_SDIO_D1_PORT GPIOA + #define RTE_SDIO_D1_PIN GPIO_PIN_8 +#else + #error "Invalid SD_DAT1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 <1=>PA9 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN GPIO_PIN_10 +#elif (RTE_SDIO_D2_PORT_ID == 1) + #define RTE_SDIO_D2_PORT GPIOA + #define RTE_SDIO_D2_PIN GPIO_PIN_9 +#else + #error "Invalid SD_DAT2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 <1=>PB5 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN GPIO_PIN_11 +#elif (RTE_SDIO_D3_PORT_ID == 1) + #define RTE_SDIO_D3_PORT GPIOB + #define RTE_SDIO_D3_PIN GPIO_PIN_5 +#else + #error "Invalid SD_DAT3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN GPIO_PIN_8 +#else + #error "Invalid SD_DAT4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN GPIO_PIN_9 +#else + #error "Invalid SD_DAT5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 <1=>PB14 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN GPIO_PIN_6 +#elif (RTE_SDIO_D6_PORT_ID == 1) + #define RTE_SDIO_D6_PORT GPIOB + #define RTE_SDIO_D6_PIN GPIO_PIN_14 +#else + #error "Invalid SD_DAT6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 <1=>PB10 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN GPIO_PIN_7 +#elif (RTE_SDIO_D7_PORT_ID == 1) + #define RTE_SDIO_D7_PORT GPIOB + #define RTE_SDIO_D7_PIN GPIO_PIN_10 +#else + #error "Invalid SD_DAT7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_PIN_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(7) +#define RTE_SDIO_CD_PIN 15 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(7) +#define RTE_SDIO_WP_PIN 10 + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_RX_DMA 1 +#define RTE_SDIO_RX_DMA_NUMBER 2 +#define RTE_SDIO_RX_DMA_STREAM 3 +#define RTE_SDIO_RX_DMA_CHANNEL 4 +#define RTE_SDIO_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_TX_DMA 1 +#define RTE_SDIO_TX_DMA_NUMBER 2 +#define RTE_SDIO_TX_DMA_STREAM 6 +#define RTE_SDIO_TX_DMA_CHANNEL 4 +#define RTE_SDIO_TX_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 <3=>PI9 <4=>PG0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT GPIO_PIN_11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT GPIO_PIN_8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT GPIO_PIN_0 +#elif (RTE_CAN1_RX_PORT_ID == 3) +#define RTE_CAN1_RX_PORT GPIOI +#define RTE_CAN1_RX_BIT GPIO_PIN_9 +#elif (RTE_CAN1_RX_PORT_ID == 4) +#define RTE_CAN1_RX_PORT GPIOG +#define RTE_CAN1_RX_BIT GPIO_PIN_0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 <3=>PH13 <4=>PG1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT GPIO_PIN_12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT GPIO_PIN_9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT GPIO_PIN_1 +#elif (RTE_CAN1_TX_PORT_ID == 3) +#define RTE_CAN1_TX_PORT GPIOH +#define RTE_CAN1_TX_BIT GPIO_PIN_13 +#elif (RTE_CAN1_TX_PORT_ID == 4) +#define RTE_CAN1_TX_PORT GPIOG +#define RTE_CAN1_TX_BIT GPIO_PIN_1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 <2=>PG11 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT GPIO_PIN_5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT GPIO_PIN_12 +#elif (RTE_CAN2_RX_PORT_ID == 2) +#define RTE_CAN2_RX_PORT GPIOG +#define RTE_CAN2_RX_BIT GPIO_PIN_11 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 <2=>PG12 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT GPIO_PIN_6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT GPIO_PIN_13 +#elif (RTE_CAN2_TX_PORT_ID == 2) +#define RTE_CAN2_TX_PORT GPIOG +#define RTE_CAN2_TX_BIT GPIO_PIN_12 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// CAN3 (Controller Area Network 3) [Driver_CAN3] +// Configuration settings for Driver_CAN3 in component ::CMSIS Driver:CAN +// Available only on STM32F413xx and STM32F423xx device series +#define RTE_CAN3 0 + +// CAN3_RX Pin <0=>PA8 <1=>PB3 +#define RTE_CAN3_RX_PORT_ID 0 +#if (RTE_CAN3_RX_PORT_ID == 0) +#define RTE_CAN3_RX_PORT GPIOA +#define RTE_CAN3_RX_BIT GPIO_PIN_8 +#elif (RTE_CAN3_RX_PORT_ID == 1) +#define RTE_CAN3_RX_PORT GPIOB +#define RTE_CAN3_RX_BIT GPIO_PIN_3 +#else +#error "Invalid CAN3_RX Pin Configuration!" +#endif + +// CAN3_TX Pin <0=>PA15 <1=>PB4 +#define RTE_CAN3_TX_PORT_ID 0 +#if (RTE_CAN3_TX_PORT_ID == 0) +#define RTE_CAN3_TX_PORT GPIOA +#define RTE_CAN3_TX_BIT GPIO_PIN_15 +#elif (RTE_CAN3_TX_PORT_ID == 1) +#define RTE_CAN3_TX_PORT GPIOB +#define RTE_CAN3_TX_BIT GPIO_PIN_4 +#else +#error "Invalid CAN3_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +#define RTE_ETH_MII 1 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) +#define RTE_ETH_MII_TXD0_PORT GPIOG +#define RTE_ETH_MII_TXD0_PIN 13 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) +#define RTE_ETH_MII_TXD1_PORT GPIOG +#define RTE_ETH_MII_TXD1_PIN 14 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) +#define RTE_ETH_MII_TXD3_PORT GPIOE +#define RTE_ETH_MII_TXD3_PIN 2 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) +#define RTE_ETH_MII_TX_EN_PORT GPIOG +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_PORT_ID 0 +#if (RTE_ETH_MII_RXD0_PORT_ID == 0) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_PORT_ID 0 +#if (RTE_ETH_MII_RXD1_PORT_ID == 0) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif +// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 +#define RTE_ETH_MII_RXD2_PORT_ID 0 +#if (RTE_ETH_MII_RXD2_PORT_ID == 0) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) +#define RTE_ETH_MII_RXD2_PORT GPIOH +#define RTE_ETH_MII_RXD2_PIN 6 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 +#define RTE_ETH_MII_RXD3_PORT_ID 0 +#if (RTE_ETH_MII_RXD3_PORT_ID == 0) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RXD3_PORT GPIOH +#define RTE_ETH_MII_RXD3_PIN 7 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_PORT_ID 0 +#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif +// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#elif (RTE_ETH_MII_RX_ER_PORT_ID == 1) +#define RTE_ETH_MII_RX_ER_PORT GPIOI +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#elif (RTE_ETH_MII_CRS_PORT_ID == 1) +#define RTE_ETH_MII_CRS_PORT GPIOH +#define RTE_ETH_MII_CRS_PIN 2 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 <1=>PH3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#elif (RTE_ETH_MII_COL_PORT_ID == 1) +#define RTE_ETH_MII_COL_PORT GPIOH +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) +#define RTE_ETH_RMII_TXD0_PORT GPIOG +#define RTE_ETH_RMII_TXD0_PIN 13 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) +#define RTE_ETH_RMII_TXD1_PORT GPIOG +#define RTE_ETH_RMII_TXD1_PIN 14 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) +#define RTE_ETH_RMII_TX_EN_PORT GPIOG +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_PORT_ID 0 +#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_PORT_ID 0 +#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 +#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::CMSIS Driver:USB Device + +#define RTE_USB_OTG_FS_DEVICE 1 + +// VBUS Sensing Pin +// Enable or disable VBUS sensing +#define RTE_OTG_FS_VBUS_SENSING_PIN 1 +// + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::CMSIS Driver:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) +#define RTE_OTG_FS_VBUS_BIT 5 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_FS_OC_BIT 11 +// + +// + + +// USB OTG High-speed +#define RTE_USB_OTG_HS 0 + +// PHY (Physical Layer) + +// PHY Interface +// <0=>On-chip full-speed PHY +// <1=>External ULPI high-speed PHY +#define RTE_USB_OTG_HS_PHY 1 + +// External ULPI Pins (UTMI+ Low Pin Interface) + +// OTG_HS_ULPI_CK Pin <0=>PA5 +#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" +#endif +// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 +#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 +#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 +#else +#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" +#endif +// OTG_HS_ULPI_STP Pin <0=>PC0 +#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" +#endif +// OTG_HS_ULPI_NXT Pin <0=>PC3 <1=>PH4 +#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 +#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 3 +#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 +#else +#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" +#endif +// OTG_HS_ULPI_D0 Pin <0=>PA3 +#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 +#else +#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" +#endif +// OTG_HS_ULPI_D1 Pin <0=>PB0 +#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" +#endif +// OTG_HS_ULPI_D2 Pin <0=>PB1 +#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 +#else +#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" +#endif +// OTG_HS_ULPI_D3 Pin <0=>PB10 +#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 +#else +#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" +#endif +// OTG_HS_ULPI_D4 Pin <0=>PB11 +#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 +#else +#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" +#endif +// OTG_HS_ULPI_D5 Pin <0=>PB12 +#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 +#else +#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" +#endif +// OTG_HS_ULPI_D6 Pin <0=>PB13 +#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 +#else +#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" +#endif +// OTG_HS_ULPI_D7 Pin <0=>PB5 +#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" +#endif + +// + +// + +// Device [Driver_USBD1] +// Configuration settings for Driver_USBD1 in component ::CMSIS Driver:USB Device + +#define RTE_USB_OTG_HS_DEVICE 0 + +// VBUS Sensing Pin +// Enable or disable VBUS sensing +// Relevant only if PHY Interface On-chip full-speed PHY is selected +#define RTE_OTG_HS_VBUS_SENSING_PIN 0 +// + +// Host [Driver_USBH1] +// Configuration settings for Driver_USBH1 in component ::CMSIS Driver:USB Host +#define RTE_USB_OTG_HS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_VBUS_PIN 1 +#define RTE_OTG_HS_VBUS_ACTIVE 0 +#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_HS_VBUS_BIT 2 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_OC_PIN 0 +#define RTE_OTG_HS_OC_ACTIVE 0 +#define RTE_OTG_HS_OC_PORT GPIO_PORT(2) +#define RTE_OTG_HS_OC_BIT 5 +// + +// DMA +// Use dedicated DMA for transfers +// If DMA is used all USB transfer data buffers have to be 4-byte aligned. +#define RTE_OTG_HS_DMA 0 + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/RTE_Device.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h.base@2.4.5 similarity index 96% rename from Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/RTE_Device.h rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h.base@2.4.5 index 1031339..e42f603 100644 --- a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/RTE_Device.h +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/RTE_Device.h.base@2.4.5 @@ -1,2693 +1,2693 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2018 Arm Limited (or its affiliates). All - * rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 9. April 2018 - * $Revision: V2.4.5 - * - * Project: RTE Device Configuration for ST STM32F4xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT0 GPIOA -#define GPIO_PORT1 GPIOB -#define GPIO_PORT2 GPIOC -#define GPIO_PORT3 GPIOD -#define GPIO_PORT4 GPIOE -#define GPIO_PORT5 GPIOF -#define GPIO_PORT6 GPIOG -#define GPIO_PORT7 GPIOH -#define GPIO_PORT8 GPIOI -#define GPIO_PORT9 GPIOJ -#define GPIO_PORT10 GPIOK - -#define GPIO_PORT(num) GPIO_PORT##num - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>Not Used <1=>PA9 <2=>PA15 <3=>PB6 -#define RTE_USART1_TX_ID 3 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX 0 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 2) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 15 -#elif (RTE_USART1_TX_ID == 3) -#define RTE_USART1_TX 1 -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>Not Used <1=>PA10 <2=>PB3 <3=>PB7 -#define RTE_USART1_RX_ID 3 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX 0 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 2) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 3 -#elif (RTE_USART1_RX_ID == 3) -#define RTE_USART1_RX 1 -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// USART1_CK Pin <0=>Not Used <1=>PA8 -#define RTE_USART1_CK_ID 1 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK 0 -#elif (RTE_USART1_CK_ID == 1) -#define RTE_USART1_CK 1 -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// USART1_CTS Pin <0=>Not Used <1=>PA11 -#define RTE_USART1_CTS_ID 1 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS 0 -#elif (RTE_USART1_CTS_ID == 1) -#define RTE_USART1_CTS 1 -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif - -// USART1_RTS Pin <0=>Not Used <1=>PA12 -#define RTE_USART1_RTS_ID 1 -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS 0 -#elif (RTE_USART1_RTS_ID == 1) -#define RTE_USART1_RTS 1 -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>Not Used <1=>PA2 <2=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX 0 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX 1 -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 2) -#define RTE_USART2_TX 1 -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>Not Used <1=>PA3 <2=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX 0 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX 1 -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 2) -#define RTE_USART2_RX 1 -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// USART2_CK Pin <0=>Not Used <1=>PA4 <2=>PD7 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK 0 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK 1 -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 2) -#define RTE_USART2_CK 1 -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// USART2_CTS Pin <0=>Not Used <1=>PA0 <2=>PD3 -#define RTE_USART2_CTS_ID 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS 1 -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 2) -#define RTE_USART2_CTS 1 -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif - -// USART2_RTS Pin <0=>Not Used <1=>PA1 <2=>PD4 -#define RTE_USART2_RTS_ID 0 -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS 0 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS 1 -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 2) -#define RTE_USART2_RTS 1 -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <4=>4 <6=>6 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 0 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 0 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>Not Used <1=>PB10 <2=>PC10 <3=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX 0 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 3) -#define RTE_USART3_TX 1 -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>Not Used <1=>PB11 <2=>PC11 <3=>PD9 <4=>PC5 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX 0 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 3) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#elif (RTE_USART3_RX_ID == 4) -#define RTE_USART3_RX 1 -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 5 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// USART3_CK Pin <0=>Not Used <1=>PB12 <2=>PC12 <3=>PD10 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK 0 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 3) -#define RTE_USART3_CK 1 -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// USART3_CTS Pin <0=>Not Used <1=>PB13 <2=>PD11 -#define RTE_USART3_CTS_ID 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS 0 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS 1 -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 2) -#define RTE_USART3_CTS 1 -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif - -// USART3_RTS Pin <0=>Not Used <1=>PB14 <2=>PD12 -#define RTE_USART3_RTS_ID 0 -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS 0 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS 1 -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 2) -#define RTE_USART3_RTS 1 -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <4=>4 -// Selects DMA Stream (only Stream 1 or 4 can be used) -// Channel <4=>4 <7=>7 -// Selects DMA Channel (only Channel 4 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 0 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 <4=>4 -// Selects DMA Stream (only Stream 3 or 4 can be used) -// Channel <4=>4 <7=>7 -// Selects DMA Channel (only Channel 4 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 0 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] -// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>Not Used <1=>PA0 <2=>PC10 <3=>PD10 <4=>PA12 <5=>PD1 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 2) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#elif (RTE_UART4_TX_ID == 3) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOD -#define RTE_UART4_TX_BIT 10 -#elif (RTE_UART4_TX_ID == 4) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 12 -#elif (RTE_UART4_TX_ID == 5) -#define RTE_UART4_TX 1 -#define RTE_UART4_TX_PORT GPIOD -#define RTE_UART4_TX_BIT 1 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>Not Used <1=>PA1 <2=>PC11 <3=>PA11 <4=>PD0 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX 0 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 2) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#elif (RTE_UART4_RX_ID == 3) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 11 -#elif (RTE_UART4_RX_ID == 4) -#define RTE_UART4_RX 1 -#define RTE_UART4_RX_PORT GPIOD -#define RTE_UART4_RX_BIT 0 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 0 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 0 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] -// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>Not Used <1=>PC12 <2=>PB6 <3=>PB9 <4=>PB13 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX 0 -#elif (RTE_UART5_TX_ID == 1) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#elif (RTE_UART5_TX_ID == 2) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 6 -#elif (RTE_UART5_TX_ID == 3) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 9 -#elif (RTE_UART5_TX_ID == 4) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 13 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>Not Used <1=>PD2 <2=>PB5 <3=>PB8 <4=>PB12 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX 0 -#elif (RTE_UART5_RX_ID == 1) -#define RTE_UART5_RX 1 -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#elif (RTE_UART5_TX_ID == 2) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 5 -#elif (RTE_UART5_TX_ID == 3) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 8 -#elif (RTE_UART5_TX_ID == 4) -#define RTE_UART5_TX 1 -#define RTE_UART5_TX_PORT GPIOB -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 0 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 <8=>8 -// Selects DMA Channel (only Channel 4 or 8 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 0 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_USART6] -// Configuration settings for Driver_USART6 in component ::CMSIS Driver:USART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>Not Used <1=>PA11 <2=>PC6 <3=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX 0 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOA -#define RTE_USART6_TX_BIT 11 -#elif (RTE_USART6_TX_ID == 2) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 3) -#define RTE_USART6_TX 1 -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>Not Used <1=>PA12 <2=>PC7 <3=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX 0 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOA -#define RTE_USART6_RX_BIT 12 -#elif (RTE_USART6_RX_ID == 2) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 3) -#define RTE_USART6_RX 1 -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// USART6_CK Pin <0=>Not Used <1=>PC8 <2=>PG7 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK 0 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK 1 -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 2) -#define RTE_USART6_CK 1 -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// USART6_CTS Pin <0=>Not Used <1=>PG13 <2=>PG15 -#define RTE_USART6_CTS_ID 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS 0 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS 1 -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 2) -#define RTE_USART6_CTS 1 -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif - -// USART6_RTS Pin <0=>Not Used <1=>PG8 <2=>PG12 -#define RTE_USART6_RTS_ID 0 -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS 0 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS 1 -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 2) -#define RTE_USART6_RTS 1 -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 0 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 0 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - -// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] -// Configuration settings for Driver_USART7 in component ::CMSIS Driver:USART -#define RTE_UART7 0 - -// UART7_TX Pin <0=>Not Used <1=>PF7 <2=>PE8 <3=>PA15 <4=>PB4 -#define RTE_UART7_TX_ID 0 -#if (RTE_UART7_TX_ID == 0) -#define RTE_UART7_TX 0 -#elif (RTE_UART7_TX_ID == 1) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOF -#define RTE_UART7_TX_BIT 7 -#elif (RTE_UART7_TX_ID == 2) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOE -#define RTE_UART7_TX_BIT 8 -#elif (RTE_UART7_TX_ID == 3) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOA -#define RTE_UART7_TX_BIT 15 -#elif (RTE_UART7_TX_ID == 4) -#define RTE_UART7_TX 1 -#define RTE_UART7_TX_PORT GPIOB -#define RTE_UART7_TX_BIT 4 -#else -#error "Invalid UART7_TX Pin Configuration!" -#endif - -// UART7_RX Pin <0=>Not Used <1=>PF6 <2=>PE7 <3=>PA8 <4=>PB3 -#define RTE_UART7_RX_ID 0 -#if (RTE_UART7_RX_ID == 0) -#define RTE_UART7_RX 0 -#elif (RTE_UART7_RX_ID == 1) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOF -#define RTE_UART7_RX_BIT 6 -#elif (RTE_UART7_RX_ID == 2) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOE -#define RTE_UART7_RX_BIT 7 -#elif (RTE_UART7_RX_ID == 3) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOA -#define RTE_UART7_RX_BIT 8 -#elif (RTE_UART7_RX_ID == 4) -#define RTE_UART7_RX 1 -#define RTE_UART7_RX_PORT GPIOB -#define RTE_UART7_RX_BIT 3 -#else -#error "Invalid UART7_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART7_RX_DMA 0 -#define RTE_UART7_RX_DMA_NUMBER 1 -#define RTE_UART7_RX_DMA_STREAM 3 -#define RTE_UART7_RX_DMA_CHANNEL 5 -#define RTE_UART7_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART7_TX_DMA 0 -#define RTE_UART7_TX_DMA_NUMBER 1 -#define RTE_UART7_TX_DMA_STREAM 1 -#define RTE_UART7_TX_DMA_CHANNEL 5 -#define RTE_UART7_TX_DMA_PRIORITY 0 - -// - -// UART8 (Universal asynchronous receiver transmitter) [Driver_USART8] -// Configuration settings for Driver_USART8 in component ::CMSIS Driver:USART -#define RTE_UART8 0 - -// UART8_TX Pin <0=>Not Used <1=>PE1 <2=>PF9 -#define RTE_UART8_TX_ID 0 -#if (RTE_UART8_TX_ID == 0) -#define RTE_UART8_TX 0 -#elif (RTE_UART8_TX_ID == 1) -#define RTE_UART8_TX 1 -#define RTE_UART8_TX_PORT GPIOE -#define RTE_UART8_TX_BIT 1 -#elif (RTE_UART8_TX_ID == 2) -#define RTE_UART8_TX 1 -#define RTE_UART8_TX_PORT GPIOF -#define RTE_UART8_TX_BIT 9 -#else -#error "Invalid UART8_TX Pin Configuration!" -#endif - -// UART8_RX Pin <0=>Not Used <1=>PE0 <2=>PF8 -#define RTE_UART8_RX_ID 0 -#if (RTE_UART8_RX_ID == 0) -#define RTE_UART8_RX 0 -#elif (RTE_UART8_RX_ID == 1) -#define RTE_UART8_RX 1 -#define RTE_UART8_RX_PORT GPIOE -#define RTE_UART8_RX_BIT 0 -#elif (RTE_UART8_RX_ID == 2) -#define RTE_UART8_RX 1 -#define RTE_UART8_RX_PORT GPIOF -#define RTE_UART8_RX_BIT 8 -#else -#error "Invalid UART8_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART8_RX_DMA 0 -#define RTE_UART8_RX_DMA_NUMBER 1 -#define RTE_UART8_RX_DMA_STREAM 6 -#define RTE_UART8_RX_DMA_CHANNEL 5 -#define RTE_UART8_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART8_TX_DMA 0 -#define RTE_UART8_TX_DMA_NUMBER 1 -#define RTE_UART8_TX_DMA_STREAM 0 -#define RTE_UART8_TX_DMA_CHANNEL 5 -#define RTE_UART8_TX_DMA_PRIORITY 0 - -// - -// UART9 (Universal asynchronous receiver transmitter) [Driver_USART9] -// Configuration settings for Driver_USART9 in component ::CMSIS Driver:USART -#define RTE_UART9 0 - -// UART9_TX Pin <0=>Not Used <1=>PD15 <2=>PG1 -#define RTE_UART9_TX_ID 0 -#if (RTE_UART9_TX_ID == 0) -#define RTE_UART9_TX 0 -#elif (RTE_UART9_TX_ID == 1) -#define RTE_UART9_TX 1 -#define RTE_UART9_TX_PORT GPIOD -#define RTE_UART9_TX_BIT 15 -#elif (RTE_UART9_TX_ID == 2) -#define RTE_UART9_TX 1 -#define RTE_UART9_TX_PORT GPIOG -#define RTE_UART9_TX_BIT 1 -#else -#error "Invalid UART9_TX Pin Configuration!" -#endif - -// UART9_RX Pin <0=>Not Used <1=>PD14 <2=>PG0 -#define RTE_UART9_RX_ID 0 -#if (RTE_UART9_RX_ID == 0) -#define RTE_UART9_RX 0 -#elif (RTE_UART9_RX_ID == 1) -#define RTE_UART9_RX 1 -#define RTE_UART9_RX_PORT GPIOD -#define RTE_UART9_RX_BIT 14 -#elif (RTE_UART9_RX_ID == 2) -#define RTE_UART9_RX 1 -#define RTE_UART9_RX_PORT GPIOG -#define RTE_UART9_RX_BIT 0 -#else -#error "Invalid UART9_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART9_RX_DMA 0 -#define RTE_UART9_RX_DMA_NUMBER 1 -#define RTE_UART9_RX_DMA_STREAM 6 -#define RTE_UART9_RX_DMA_CHANNEL 5 -#define RTE_UART9_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART9_TX_DMA 0 -#define RTE_UART9_TX_DMA_NUMBER 1 -#define RTE_UART9_TX_DMA_STREAM 0 -#define RTE_UART9_TX_DMA_CHANNEL 5 -#define RTE_UART9_TX_DMA_PRIORITY 0 - -// - -// UART10 (Universal asynchronous receiver transmitter) [Driver_USART10] -// Configuration settings for Driver_USART10 in component ::CMSIS Driver:USART -#define RTE_UART10 0 - -// UART10_TX Pin <0=>Not Used <1=>PE3 <2=>PG12 -#define RTE_UART10_TX_ID 0 -#if (RTE_UART10_TX_ID == 0) -#define RTE_UART10_TX 0 -#elif (RTE_UART10_TX_ID == 1) -#define RTE_UART10_TX 1 -#define RTE_UART10_TX_PORT GPIOE -#define RTE_UART10_TX_BIT 3 -#elif (RTE_UART10_TX_ID == 2) -#define RTE_UART10_TX 1 -#define RTE_UART10_TX_PORT GPIOG -#define RTE_UART10_TX_BIT 12 -#else -#error "Invalid UART10_TX Pin Configuration!" -#endif - -// UART10_RX Pin <0=>Not Used <1=>PE2 <2=>PG11 -#define RTE_UART10_RX_ID 0 -#if (RTE_UART10_RX_ID == 0) -#define RTE_UART10_RX 0 -#elif (RTE_UART10_RX_ID == 1) -#define RTE_UART10_RX 1 -#define RTE_UART10_RX_PORT GPIOE -#define RTE_UART10_RX_BIT 2 -#elif (RTE_UART10_RX_ID == 2) -#define RTE_UART10_RX 1 -#define RTE_UART10_RX_PORT GPIOG -#define RTE_UART10_RX_BIT 11 -#else -#error "Invalid UART10_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <3=>3 -// Selects DMA Stream (only Stream 0 or 3 can be used) -// Channel <5=>5 <9=>9 -// Selects DMA Channel (only Channel 5 or 9 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART10_RX_DMA 0 -#define RTE_UART10_RX_DMA_NUMBER 1 -#define RTE_UART10_RX_DMA_STREAM 6 -#define RTE_UART10_RX_DMA_CHANNEL 5 -#define RTE_UART10_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 <3=>5 -// Selects DMA Stream (only Stream 7 or 5 can be used) -// Channel <6=>6 <9=>9 -// Selects DMA Channel (only Channel 6 or 9 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART10_TX_DMA 0 -#define RTE_UART10_TX_DMA_NUMBER 1 -#define RTE_UART10_TX_DMA_STREAM 0 -#define RTE_UART10_TX_DMA_CHANNEL 5 -#define RTE_UART10_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 0 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <6=>6 <7=>7 -// Selects DMA Stream (only Stream 1 or 6 or 7 can be used) -// Channel <0=>0 <1=>1 -// Selects DMA Channel (only Channel 0 or 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 0 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 <3=>PB3 <4=>PB9 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#elif (RTE_I2C2_SDA_PORT_ID == 3) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 3 -#elif (RTE_I2C2_SDA_PORT_ID == 4) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 9 -#else -#error "Invalid I2C2_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 0 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 0 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::CMSIS Driver:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 <2=>PB4 <3=>PB8 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#elif (RTE_I2C3_SDA_PORT_ID == 2) -#define RTE_I2C3_SDA_PORT GPIOB -#define RTE_I2C3_SDA_BIT 4 -#elif (RTE_I2C3_SDA_PORT_ID == 3) -#define RTE_I2C3_SDA_PORT GPIOB -#define RTE_I2C3_SDA_BIT 8 -#else -#error "Invalid I2C3_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <1=>1 <3=>3 -// Selects DMA Channel (only Channel 1 or 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 0 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 <5=>5 -// Selects DMA Stream (only Stream 4 or 5 can be used) -// Channel <3=>3 <6=>6 -// Selects DMA Channel (only Channel 3 or 6 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 0 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI -#define RTE_SPI1 0 - -// SPI1_MISO Pin <0=>Not Used <1=>PA6 <2=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO 0 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO 1 -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 2) -#define RTE_SPI1_MISO 1 -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>Not Used <1=>PA7 <2=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI 0 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI 1 -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 2) -#define RTE_SPI1_MOSI 1 -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MOSI Pin Configuration!" -#endif - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 -#define RTE_SPI1_NSS_PORT_ID 0 -#if (RTE_SPI1_NSS_PORT_ID == 0) -#define RTE_SPI1_NSS_PIN 0 -#elif (RTE_SPI1_NSS_PORT_ID == 1) -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIOA -#define RTE_SPI1_NSS_BIT 4 -#elif (RTE_SPI1_NSS_PORT_ID == 2) -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIOA -#define RTE_SPI1_NSS_BIT 15 -#else -#error "Invalid SPI1_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 0 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <3=>3 <5=>5 -// Selects DMA Stream (only Stream 2 or 3 or 5 can be used) -// Channel <2=>2 <3=>3 -// Selects DMA Channel (only Channel 2 or 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 0 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI -#define RTE_SPI2 1 - -// SPI2_MISO Pin <0=>Not Used <1=>PB14 <2=>PC2 <3=>PI2 <4=>PA12 -#define RTE_SPI2_MISO_PORT_ID 1 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO 0 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 3) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 4) -#define RTE_SPI2_MISO 1 -#define RTE_SPI2_MISO_PORT GPIOA -#define RTE_SPI2_MISO_BIT 12 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>Not Used <1=>PB15 <2=>PC3 <3=>PI3 <4=>PA10 -#define RTE_SPI2_MOSI_PORT_ID 1 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI 0 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 3) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 4) -#define RTE_SPI2_MOSI 1 -#define RTE_SPI2_MOSI_PORT GPIOA -#define RTE_SPI2_MOSI_BIT 10 -#else -#error "Invalid SPI2_MOSI Pin Configuration!" -#endif - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PC7 <3=>PD3 <4=>PI1 <5=>PA9 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOC -#define RTE_SPI2_SCL_BIT 7 -#elif (RTE_SPI2_SCL_PORT_ID == 3) -#define RTE_SPI2_SCL_PORT GPIOD -#define RTE_SPI2_SCL_BIT 3 -#elif (RTE_SPI2_SCL_PORT_ID == 4) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#elif (RTE_SPI2_SCL_PORT_ID == 5) -#define RTE_SPI2_SCL_PORT GPIOA -#define RTE_SPI2_SCL_BIT 9 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_NSS Pin <0=>Not Used <1=>PB9 <2=>PB12 <3=>PI0 <4=>PA11 -#define RTE_SPI2_NSS_PORT_ID 3 -#if (RTE_SPI2_NSS_PORT_ID == 0) -#define RTE_SPI2_NSS_PIN 0 -#elif (RTE_SPI2_NSS_PORT_ID == 1) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOB -#define RTE_SPI2_NSS_BIT 9 -#elif (RTE_SPI2_NSS_PORT_ID == 2) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOB -#define RTE_SPI2_NSS_BIT 12 -#elif (RTE_SPI2_NSS_PORT_ID == 3) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOI -#define RTE_SPI2_NSS_BIT 0 -#elif (RTE_SPI2_NSS_PORT_ID == 4) -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIOA -#define RTE_SPI2_NSS_BIT 11 -#else -#error "Invalid SPI2_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 3 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 4 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI -#define RTE_SPI3 0 - -// SPI3_MISO Pin <0=>Not Used <1=>PB4 <2=>PC11 -#define RTE_SPI3_MISO_PORT_ID 2 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO 0 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO 1 -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 2) -#define RTE_SPI3_MISO 1 -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>Not Used <1=>PB5 <2=>PC12 <3=>PD6 -#define RTE_SPI3_MOSI_PORT_ID 2 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI 0 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 2) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#elif (RTE_SPI3_MOSI_PORT_ID == 3) -#define RTE_SPI3_MOSI 1 -#define RTE_SPI3_MOSI_PORT GPIOD -#define RTE_SPI3_MOSI_BIT 6 -#else -#error "Invalid SPI3_MOSI Pin Configuration!" -#endif - -// SPI3_SCK Pin <0=>PB3 <1=>PB12 <2=>PC10 -#define RTE_SPI3_SCL_PORT_ID 2 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 12 -#elif (RTE_SPI3_SCL_PORT_ID == 2) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 -#define RTE_SPI3_NSS_PORT_ID 1 -#if (RTE_SPI3_NSS_PORT_ID == 0) -#define RTE_SPI3_NSS_PIN 0 -#elif (RTE_SPI3_NSS_PORT_ID == 1) -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIOA -#define RTE_SPI3_NSS_BIT 4 -#elif (RTE_SPI3_NSS_PORT_ID == 2) -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIOA -#define RTE_SPI3_NSS_BIT 15 -#else -#error "Invalid SPI3_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] -// Configuration settings for Driver_SPI4 in component ::CMSIS Driver:SPI -#define RTE_SPI4 0 - -// SPI4_MISO Pin <0=>Not Used <1=>PA11 <2=>PE5 <3=>PE13 -#define RTE_SPI4_MISO_PORT_ID 0 -#if (RTE_SPI4_MISO_PORT_ID == 0) -#define RTE_SPI4_MISO 0 -#elif (RTE_SPI4_MISO_PORT_ID == 1) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOA -#define RTE_SPI4_MISO_BIT 11 -#elif (RTE_SPI4_MISO_PORT_ID == 2) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOE -#define RTE_SPI4_MISO_BIT 5 -#elif (RTE_SPI4_MISO_PORT_ID == 3) -#define RTE_SPI4_MISO 1 -#define RTE_SPI4_MISO_PORT GPIOE -#define RTE_SPI4_MISO_BIT 13 -#else -#error "Invalid SPI4_MISO Pin Configuration!" -#endif - -// SPI4_MOSI Pin <0=>Not Used <1=>PA1 <2=>PE6 <3=>PE14 -#define RTE_SPI4_MOSI_PORT_ID 0 -#if (RTE_SPI4_MOSI_PORT_ID == 0) -#define RTE_SPI4_MOSI 0 -#elif (RTE_SPI4_MOSI_PORT_ID == 1) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOA -#define RTE_SPI4_MOSI_BIT 1 -#elif (RTE_SPI4_MOSI_PORT_ID == 2) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOE -#define RTE_SPI4_MOSI_BIT 6 -#elif (RTE_SPI4_MOSI_PORT_ID == 3) -#define RTE_SPI4_MOSI 1 -#define RTE_SPI4_MOSI_PORT GPIOE -#define RTE_SPI4_MOSI_BIT 14 -#else -#error "Invalid SPI4_MOSI Pin Configuration!" -#endif - -// SPI4_SCK Pin <0=>PB13 <1=>PE2 <2=>PE12 -#define RTE_SPI4_SCL_PORT_ID 0 -#if (RTE_SPI4_SCL_PORT_ID == 0) -#define RTE_SPI4_SCL_PORT GPIOB -#define RTE_SPI4_SCL_BIT 13 -#elif (RTE_SPI4_SCL_PORT_ID == 1) -#define RTE_SPI4_SCL_PORT GPIOE -#define RTE_SPI4_SCL_BIT 2 -#elif (RTE_SPI4_SCL_PORT_ID == 2) -#define RTE_SPI4_SCL_PORT GPIOE -#define RTE_SPI4_SCL_BIT 12 -#else -#error "Invalid SPI4_SCK Pin Configuration!" -#endif - -// SPI4_NSS Pin <0=>Not Used <1=>PB12 <2=>PE4 <3=>PE11 -#define RTE_SPI4_NSS_PORT_ID 0 -#if (RTE_SPI4_NSS_PORT_ID == 0) -#define RTE_SPI4_NSS_PIN 0 -#elif (RTE_SPI4_NSS_PORT_ID == 1) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOB -#define RTE_SPI4_NSS_BIT 12 -#elif (RTE_SPI4_NSS_PORT_ID == 2) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOE -#define RTE_SPI4_NSS_BIT 4 -#elif (RTE_SPI4_NSS_PORT_ID == 3) -#define RTE_SPI4_NSS_PIN 1 -#define RTE_SPI4_NSS_PORT GPIOE -#define RTE_SPI4_NSS_BIT 11 -#else -#error "Invalid SPI4_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <3=>3 <4=>4 -// Selects DMA Stream (only Stream 0 or 3 can be used) -// Channel <4=>4 <5=>5 -// Selects DMA Channel (only Channel 4 or 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI4_RX_DMA 0 -#define RTE_SPI4_RX_DMA_NUMBER 1 -#define RTE_SPI4_RX_DMA_STREAM 0 -#define RTE_SPI4_RX_DMA_CHANNEL 0 -#define RTE_SPI4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <4=>4 -// Selects DMA Stream (only Stream 1 or 4 can be used) -// Channel <4=>4 <5=>5 -// Selects DMA Channel (only Channel 4 or 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI4_TX_DMA 0 -#define RTE_SPI4_TX_DMA_NUMBER 1 -#define RTE_SPI4_TX_DMA_STREAM 5 -#define RTE_SPI4_TX_DMA_CHANNEL 0 -#define RTE_SPI4_TX_DMA_PRIORITY 0 - -// - - -// SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] -// Configuration settings for Driver_SPI5 in component ::CMSIS Driver:SPI -#define RTE_SPI5 0 - -// SPI5_MISO Pin <0=>Not Used <1=>PA12 <2=>PE5 <3=>PE13 <4=>PF8 <5=>PH7 -#define RTE_SPI5_MISO_PORT_ID 0 -#if (RTE_SPI5_MISO_PORT_ID == 0) -#define RTE_SPI5_MISO 0 -#elif (RTE_SPI5_MISO_PORT_ID == 1) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOA -#define RTE_SPI5_MISO_BIT 12 -#elif (RTE_SPI5_MISO_PORT_ID == 2) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOE -#define RTE_SPI5_MISO_BIT 5 -#elif (RTE_SPI5_MISO_PORT_ID == 3) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOE -#define RTE_SPI5_MISO_BIT 13 -#elif (RTE_SPI5_MISO_PORT_ID == 4) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOF -#define RTE_SPI5_MISO_BIT 8 -#elif (RTE_SPI5_MISO_PORT_ID == 5) -#define RTE_SPI5_MISO 1 -#define RTE_SPI5_MISO_PORT GPIOH -#define RTE_SPI5_MISO_BIT 7 -#else -#error "Invalid SPI5_MISO Pin Configuration!" -#endif - -// SPI5_MOSI Pin <0=>Not Used <1=>PA10 <2=>PB8 <3=>PE6 <4=>PE14 <5=>PF9 <6=>PF11 -#define RTE_SPI5_MOSI_PORT_ID 0 -#if (RTE_SPI5_MOSI_PORT_ID == 0) -#define RTE_SPI5_MOSI 0 -#elif (RTE_SPI5_MOSI_PORT_ID == 1) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOA -#define RTE_SPI5_MOSI_BIT 10 -#elif (RTE_SPI5_MOSI_PORT_ID == 2) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOB -#define RTE_SPI5_MOSI_BIT 8 -#elif (RTE_SPI5_MOSI_PORT_ID == 3) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOE -#define RTE_SPI5_MOSI_BIT 6 -#elif (RTE_SPI5_MOSI_PORT_ID == 4) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOE -#define RTE_SPI5_MOSI_BIT 14 -#elif (RTE_SPI5_MOSI_PORT_ID == 5) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOF -#define RTE_SPI5_MOSI_BIT 9 -#elif (RTE_SPI5_MOSI_PORT_ID == 6) -#define RTE_SPI5_MOSI 1 -#define RTE_SPI5_MOSI_PORT GPIOF -#define RTE_SPI5_MOSI_BIT 11 -#else -#error "Invalid SPI5_MOSI Pin Configuration!" -#endif - -// SPI5_SCK Pin <0=>PB0 <1=>PE2 <2=>PE12 <3=>PF7 <4=>PH6 -#define RTE_SPI5_SCL_PORT_ID 0 -#if (RTE_SPI5_SCL_PORT_ID == 0) -#define RTE_SPI5_SCL_PORT GPIOB -#define RTE_SPI5_SCL_BIT 0 -#elif (RTE_SPI5_SCL_PORT_ID == 1) -#define RTE_SPI5_SCL_PORT GPIOE -#define RTE_SPI5_SCL_BIT 2 -#elif (RTE_SPI5_SCL_PORT_ID == 2) -#define RTE_SPI5_SCL_PORT GPIOE -#define RTE_SPI5_SCL_BIT 12 -#elif (RTE_SPI5_SCL_PORT_ID == 3) -#define RTE_SPI5_SCL_PORT GPIOF -#define RTE_SPI5_SCL_BIT 7 -#elif (RTE_SPI5_SCL_PORT_ID == 4) -#define RTE_SPI5_SCL_PORT GPIOH -#define RTE_SPI5_SCL_BIT 6 -#else -#error "Invalid SPI5_SCK Pin Configuration!" -#endif - -// SPI5_NSS Pin <0=>Not Used <1=>PB1 <2=>PE4 <3=>PE11 <4=>PF6 <5=>PH5 -#define RTE_SPI5_NSS_PORT_ID 0 -#if (RTE_SPI5_NSS_PORT_ID == 0) -#define RTE_SPI5_NSS_PIN 0 -#elif (RTE_SPI5_NSS_PORT_ID == 1) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOB -#define RTE_SPI5_NSS_BIT 1 -#elif (RTE_SPI5_NSS_PORT_ID == 2) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOE -#define RTE_SPI5_NSS_BIT 4 -#elif (RTE_SPI5_NSS_PORT_ID == 3) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOE -#define RTE_SPI5_NSS_BIT 11 -#elif (RTE_SPI5_NSS_PORT_ID == 4) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOF -#define RTE_SPI5_NSS_BIT 6 -#elif (RTE_SPI5_NSS_PORT_ID == 5) -#define RTE_SPI5_NSS_PIN 1 -#define RTE_SPI5_NSS_PORT GPIOH -#define RTE_SPI5_NSS_BIT 5 -#else -#error "Invalid SPI5_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <2=>2 <7=>7 -// Selects DMA Channel (only Channel 2 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI5_RX_DMA 0 -#define RTE_SPI5_RX_DMA_NUMBER 2 -#define RTE_SPI5_RX_DMA_STREAM 3 -#define RTE_SPI5_RX_DMA_CHANNEL 2 -#define RTE_SPI5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <4=>4 <5=>5 <6=>6 -// Selects DMA Stream (only Stream 4 or 6 can be used) -// Channel <2=>2 <5=>5 <7=>7 -// Selects DMA Channel (only Channel 2 or 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI5_TX_DMA 0 -#define RTE_SPI5_TX_DMA_NUMBER 2 -#define RTE_SPI5_TX_DMA_STREAM 4 -#define RTE_SPI5_TX_DMA_CHANNEL 2 -#define RTE_SPI5_TX_DMA_PRIORITY 0 - -// - - -// SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] -// Configuration settings for Driver_SPI6 in component ::CMSIS Driver:SPI -#define RTE_SPI6 0 - -// SPI6_MISO Pin <0=>Not Used <1=>PG12 -#define RTE_SPI6_MISO_PORT_ID 0 -#if (RTE_SPI6_MISO_PORT_ID == 0) -#define RTE_SPI6_MISO 0 -#elif (RTE_SPI6_MISO_PORT_ID == 1) -#define RTE_SPI6_MISO 1 -#define RTE_SPI6_MISO_PORT GPIOG -#define RTE_SPI6_MISO_BIT 12 -#else -#error "Invalid SPI6_MISO Pin Configuration!" -#endif - -// SPI6_MOSI Pin <0=>Not Used <1=>PG14 -#define RTE_SPI6_MOSI_PORT_ID 0 -#if (RTE_SPI6_MOSI_PORT_ID == 0) -#define RTE_SPI6_MOSI 0 -#elif (RTE_SPI6_MOSI_PORT_ID == 1) -#define RTE_SPI6_MOSI 1 -#define RTE_SPI6_MOSI_PORT GPIOG -#define RTE_SPI6_MOSI_BIT 14 -#else -#error "Invalid SPI6_MOSI Pin Configuration!" -#endif - -// SPI6_SCK Pin <0=>PG13 -#define RTE_SPI6_SCL_PORT_ID 0 -#if (RTE_SPI6_SCL_PORT_ID == 0) -#define RTE_SPI6_SCL_PORT GPIOG -#define RTE_SPI6_SCL_BIT 13 -#else -#error "Invalid SPI6_SCK Pin Configuration!" -#endif - -// SPI6_NSS Pin <0=>Not Used <1=>PG8 -#define RTE_SPI6_NSS_PORT_ID 0 -#if (RTE_SPI6_NSS_PORT_ID == 0) -#define RTE_SPI6_NSS_PIN 0 -#elif (RTE_SPI6_NSS_PORT_ID == 1) -#define RTE_SPI6_NSS_PIN 1 -#define RTE_SPI6_NSS_PORT GPIOG -#define RTE_SPI6_NSS_BIT 8 -#else -#error "Invalid SPI6_NSS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI6_RX_DMA 0 -#define RTE_SPI6_RX_DMA_NUMBER 2 -#define RTE_SPI6_RX_DMA_STREAM 6 -#define RTE_SPI6_RX_DMA_CHANNEL 1 -#define RTE_SPI6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI6_TX_DMA 0 -#define RTE_SPI6_TX_DMA_NUMBER 2 -#define RTE_SPI6_TX_DMA_STREAM 5 -#define RTE_SPI6_TX_DMA_CHANNEL 1 -#define RTE_SPI6_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI -#define RTE_SDIO 0 - -// SDIO Peripheral Bus -// SDIO_CK Pin <0=>PC12 <1=>PB15 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) - #define RTE_SDIO_CK_PORT GPIOC - #define RTE_SDIO_CK_PIN GPIO_PIN_12 -#elif (RTE_SDIO_CK_PORT_ID == 1) - #define RTE_SDIO_CK_PORT GPIOB - #define RTE_SDIO_CK_PIN GPIO_PIN_15 -#else - #error "Invalid SD_CLK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 <1=>PA6 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) - #define RTE_SDIO_CMD_PORT GPIOD - #define RTE_SDIO_CMD_PIN GPIO_PIN_2 -#elif (RTE_SDIO_CMD_PORT_ID == 1) - #define RTE_SDIO_CMD_PORT GPIOA - #define RTE_SDIO_CMD_PIN GPIO_PIN_6 -#else - #error "Invalid SD_CMD Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 <1=>PB4 <2=>PB6 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) - #define RTE_SDIO_D0_PORT GPIOC - #define RTE_SDIO_D0_PIN GPIO_PIN_8 -#elif (RTE_SDIO_D0_PORT_ID == 1) - #define RTE_SDIO_D0_PORT GPIOB - #define RTE_SDIO_D0_PIN GPIO_PIN_4 -#elif (RTE_SDIO_D0_PORT_ID == 2) - #define RTE_SDIO_D0_PORT GPIOB - #define RTE_SDIO_D0_PIN GPIO_PIN_6 -#else - #error "Invalid SD_DAT0 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -#define RTE_SDIO_BUS_WIDTH_4 1 -// SDIO_D1 Pin <0=>PC9 <1=>PA8 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) - #define RTE_SDIO_D1_PORT GPIOC - #define RTE_SDIO_D1_PIN GPIO_PIN_9 -#elif (RTE_SDIO_D1_PORT_ID == 1) - #define RTE_SDIO_D1_PORT GPIOA - #define RTE_SDIO_D1_PIN GPIO_PIN_8 -#else - #error "Invalid SD_DAT1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 <1=>PA9 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) - #define RTE_SDIO_D2_PORT GPIOC - #define RTE_SDIO_D2_PIN GPIO_PIN_10 -#elif (RTE_SDIO_D2_PORT_ID == 1) - #define RTE_SDIO_D2_PORT GPIOA - #define RTE_SDIO_D2_PIN GPIO_PIN_9 -#else - #error "Invalid SD_DAT2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 <1=>PB5 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) - #define RTE_SDIO_D3_PORT GPIOC - #define RTE_SDIO_D3_PIN GPIO_PIN_11 -#elif (RTE_SDIO_D3_PORT_ID == 1) - #define RTE_SDIO_D3_PORT GPIOB - #define RTE_SDIO_D3_PIN GPIO_PIN_5 -#else - #error "Invalid SD_DAT3 Pin Configuration!" -#endif -// SDIO_D[1 .. 3] -// SDIO_D[4 .. 7] -#define RTE_SDIO_BUS_WIDTH_8 0 -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) - #define RTE_SDIO_D4_PORT GPIOB - #define RTE_SDIO_D4_PIN GPIO_PIN_8 -#else - #error "Invalid SD_DAT4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) - #define RTE_SDIO_D5_PORT GPIOB - #define RTE_SDIO_D5_PIN GPIO_PIN_9 -#else - #error "Invalid SD_DAT5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 <1=>PB14 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) - #define RTE_SDIO_D6_PORT GPIOC - #define RTE_SDIO_D6_PIN GPIO_PIN_6 -#elif (RTE_SDIO_D6_PORT_ID == 1) - #define RTE_SDIO_D6_PORT GPIOB - #define RTE_SDIO_D6_PIN GPIO_PIN_14 -#else - #error "Invalid SD_DAT6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 <1=>PB10 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) - #define RTE_SDIO_D7_PORT GPIOC - #define RTE_SDIO_D7_PIN GPIO_PIN_7 -#elif (RTE_SDIO_D7_PORT_ID == 1) - #define RTE_SDIO_D7_PORT GPIOB - #define RTE_SDIO_D7_PIN GPIO_PIN_10 -#else - #error "Invalid SD_DAT7 Pin Configuration!" -#endif -// SDIO_D[4 .. 7] -// SDIO Peripheral Bus - -// Card Detect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN_EN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_PIN 15 - -// Write Protect Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_EN 0 -#define RTE_SDIO_WP_ACTIVE 1 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_PIN 10 - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_RX_DMA 1 -#define RTE_SDIO_RX_DMA_NUMBER 2 -#define RTE_SDIO_RX_DMA_STREAM 3 -#define RTE_SDIO_RX_DMA_CHANNEL 4 -#define RTE_SDIO_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_TX_DMA 1 -#define RTE_SDIO_TX_DMA_NUMBER 2 -#define RTE_SDIO_TX_DMA_STREAM 6 -#define RTE_SDIO_TX_DMA_CHANNEL 4 -#define RTE_SDIO_TX_DMA_PRIORITY 0 - -// - - -// CAN1 (Controller Area Network 1) [Driver_CAN1] -// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN -#define RTE_CAN1 0 - -// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 <3=>PI9 <4=>PG0 -#define RTE_CAN1_RX_PORT_ID 0 -#if (RTE_CAN1_RX_PORT_ID == 0) -#define RTE_CAN1_RX_PORT GPIOA -#define RTE_CAN1_RX_BIT GPIO_PIN_11 -#elif (RTE_CAN1_RX_PORT_ID == 1) -#define RTE_CAN1_RX_PORT GPIOB -#define RTE_CAN1_RX_BIT GPIO_PIN_8 -#elif (RTE_CAN1_RX_PORT_ID == 2) -#define RTE_CAN1_RX_PORT GPIOD -#define RTE_CAN1_RX_BIT GPIO_PIN_0 -#elif (RTE_CAN1_RX_PORT_ID == 3) -#define RTE_CAN1_RX_PORT GPIOI -#define RTE_CAN1_RX_BIT GPIO_PIN_9 -#elif (RTE_CAN1_RX_PORT_ID == 4) -#define RTE_CAN1_RX_PORT GPIOG -#define RTE_CAN1_RX_BIT GPIO_PIN_0 -#else -#error "Invalid CAN1_RX Pin Configuration!" -#endif - -// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 <3=>PH13 <4=>PG1 -#define RTE_CAN1_TX_PORT_ID 0 -#if (RTE_CAN1_TX_PORT_ID == 0) -#define RTE_CAN1_TX_PORT GPIOA -#define RTE_CAN1_TX_BIT GPIO_PIN_12 -#elif (RTE_CAN1_TX_PORT_ID == 1) -#define RTE_CAN1_TX_PORT GPIOB -#define RTE_CAN1_TX_BIT GPIO_PIN_9 -#elif (RTE_CAN1_TX_PORT_ID == 2) -#define RTE_CAN1_TX_PORT GPIOD -#define RTE_CAN1_TX_BIT GPIO_PIN_1 -#elif (RTE_CAN1_TX_PORT_ID == 3) -#define RTE_CAN1_TX_PORT GPIOH -#define RTE_CAN1_TX_BIT GPIO_PIN_13 -#elif (RTE_CAN1_TX_PORT_ID == 4) -#define RTE_CAN1_TX_PORT GPIOG -#define RTE_CAN1_TX_BIT GPIO_PIN_1 -#else -#error "Invalid CAN1_TX Pin Configuration!" -#endif - -// - - -// CAN2 (Controller Area Network 2) [Driver_CAN2] -// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN -#define RTE_CAN2 0 - -// CAN2_RX Pin <0=>PB5 <1=>PB12 <2=>PG11 -#define RTE_CAN2_RX_PORT_ID 0 -#if (RTE_CAN2_RX_PORT_ID == 0) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT GPIO_PIN_5 -#elif (RTE_CAN2_RX_PORT_ID == 1) -#define RTE_CAN2_RX_PORT GPIOB -#define RTE_CAN2_RX_BIT GPIO_PIN_12 -#elif (RTE_CAN2_RX_PORT_ID == 2) -#define RTE_CAN2_RX_PORT GPIOG -#define RTE_CAN2_RX_BIT GPIO_PIN_11 -#else -#error "Invalid CAN2_RX Pin Configuration!" -#endif - -// CAN2_TX Pin <0=>PB6 <1=>PB13 <2=>PG12 -#define RTE_CAN2_TX_PORT_ID 0 -#if (RTE_CAN2_TX_PORT_ID == 0) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT GPIO_PIN_6 -#elif (RTE_CAN2_TX_PORT_ID == 1) -#define RTE_CAN2_TX_PORT GPIOB -#define RTE_CAN2_TX_BIT GPIO_PIN_13 -#elif (RTE_CAN2_TX_PORT_ID == 2) -#define RTE_CAN2_TX_PORT GPIOG -#define RTE_CAN2_TX_BIT GPIO_PIN_12 -#else -#error "Invalid CAN2_TX Pin Configuration!" -#endif - -// - - -// CAN3 (Controller Area Network 3) [Driver_CAN3] -// Configuration settings for Driver_CAN3 in component ::CMSIS Driver:CAN -// Available only on STM32F413xx and STM32F423xx device series -#define RTE_CAN3 0 - -// CAN3_RX Pin <0=>PA8 <1=>PB3 -#define RTE_CAN3_RX_PORT_ID 0 -#if (RTE_CAN3_RX_PORT_ID == 0) -#define RTE_CAN3_RX_PORT GPIOA -#define RTE_CAN3_RX_BIT GPIO_PIN_8 -#elif (RTE_CAN3_RX_PORT_ID == 1) -#define RTE_CAN3_RX_PORT GPIOB -#define RTE_CAN3_RX_BIT GPIO_PIN_3 -#else -#error "Invalid CAN3_RX Pin Configuration!" -#endif - -// CAN3_TX Pin <0=>PA15 <1=>PB4 -#define RTE_CAN3_TX_PORT_ID 0 -#if (RTE_CAN3_TX_PORT_ID == 0) -#define RTE_CAN3_TX_PORT GPIOA -#define RTE_CAN3_TX_BIT GPIO_PIN_15 -#elif (RTE_CAN3_TX_PORT_ID == 1) -#define RTE_CAN3_TX_PORT GPIOB -#define RTE_CAN3_TX_BIT GPIO_PIN_4 -#else -#error "Invalid CAN3_TX Pin Configuration!" -#endif - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC -#define RTE_ETH 0 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RX_ER_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 0 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 0 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 0 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 0 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::CMSIS Driver:USB Device - -#define RTE_USB_OTG_FS_DEVICE 1 - -// VBUS Sensing Pin -// Enable or disable VBUS sensing -#define RTE_OTG_FS_VBUS_SENSING_PIN 1 -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::CMSIS Driver:USB Host - -#define RTE_USB_OTG_FS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC3 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 3 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::CMSIS Driver:USB Device - -#define RTE_USB_OTG_HS_DEVICE 0 - -// VBUS Sensing Pin -// Enable or disable VBUS sensing -// Relevant only if PHY Interface On-chip full-speed PHY is selected -#define RTE_OTG_HS_VBUS_SENSING_PIN 0 -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::CMSIS Driver:USB Host -#define RTE_USB_OTG_HS_HOST 0 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// DMA -// Use dedicated DMA for transfers -// If DMA is used all USB transfer data buffers have to be 4-byte aligned. -#define RTE_OTG_HS_DMA 0 - -// - - -#endif /* __RTE_DEVICE_H */ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2018 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 9. April 2018 + * $Revision: V2.4.5 + * + * Project: RTE Device Configuration for ST STM32F4xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT0 GPIOA +#define GPIO_PORT1 GPIOB +#define GPIO_PORT2 GPIOC +#define GPIO_PORT3 GPIOD +#define GPIO_PORT4 GPIOE +#define GPIO_PORT5 GPIOF +#define GPIO_PORT6 GPIOG +#define GPIO_PORT7 GPIOH +#define GPIO_PORT8 GPIOI +#define GPIO_PORT9 GPIOJ +#define GPIO_PORT10 GPIOK + +#define GPIO_PORT(num) GPIO_PORT##num + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 <2=>PA15 <3=>PB6 +#define RTE_USART1_TX_ID 0 +#if (RTE_USART1_TX_ID == 0) +#define RTE_USART1_TX 0 +#elif (RTE_USART1_TX_ID == 1) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 9 +#elif (RTE_USART1_TX_ID == 2) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 15 +#elif (RTE_USART1_TX_ID == 3) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 <2=>PB3 <3=>PB7 +#define RTE_USART1_RX_ID 0 +#if (RTE_USART1_RX_ID == 0) +#define RTE_USART1_RX 0 +#elif (RTE_USART1_RX_ID == 1) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOA +#define RTE_USART1_RX_BIT 10 +#elif (RTE_USART1_RX_ID == 2) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 3 +#elif (RTE_USART1_RX_ID == 3) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_ID 0 +#if (RTE_USART1_CK_ID == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_ID == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT GPIOA +#define RTE_USART1_CK_BIT 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_ID 0 +#if (RTE_USART1_CTS_ID == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_ID == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT GPIOA +#define RTE_USART1_CTS_BIT 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_ID 0 +#if (RTE_USART1_RTS_ID == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_ID == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT GPIOA +#define RTE_USART1_RTS_BIT 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <5=>5 +// Selects DMA Stream (only Stream 2 or 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 2 +#define RTE_USART1_RX_DMA_STREAM 2 +#define RTE_USART1_RX_DMA_CHANNEL 4 +#define RTE_USART1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 2 +#define RTE_USART1_TX_DMA_STREAM 7 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 + +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 <2=>PD5 +#define RTE_USART2_TX_ID 0 +#if (RTE_USART2_TX_ID == 0) +#define RTE_USART2_TX 0 +#elif (RTE_USART2_TX_ID == 1) +#define RTE_USART2_TX 1 +#define RTE_USART2_TX_PORT GPIOA +#define RTE_USART2_TX_BIT 2 +#elif (RTE_USART2_TX_ID == 2) +#define RTE_USART2_TX 1 +#define RTE_USART2_TX_PORT GPIOD +#define RTE_USART2_TX_BIT 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 <2=>PD6 +#define RTE_USART2_RX_ID 0 +#if (RTE_USART2_RX_ID == 0) +#define RTE_USART2_RX 0 +#elif (RTE_USART2_RX_ID == 1) +#define RTE_USART2_RX 1 +#define RTE_USART2_RX_PORT GPIOA +#define RTE_USART2_RX_BIT 3 +#elif (RTE_USART2_RX_ID == 2) +#define RTE_USART2_RX 1 +#define RTE_USART2_RX_PORT GPIOD +#define RTE_USART2_RX_BIT 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 <2=>PD7 +#define RTE_USART2_CK_ID 0 +#if (RTE_USART2_CK_ID == 0) +#define RTE_USART2_CK 0 +#elif (RTE_USART2_CK_ID == 1) +#define RTE_USART2_CK 1 +#define RTE_USART2_CK_PORT GPIOA +#define RTE_USART2_CK_BIT 4 +#elif (RTE_USART2_CK_ID == 2) +#define RTE_USART2_CK 1 +#define RTE_USART2_CK_PORT GPIOD +#define RTE_USART2_CK_BIT 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 <2=>PD3 +#define RTE_USART2_CTS_ID 0 +#if (RTE_USART2_CTS_ID == 0) +#define RTE_USART2_CTS 0 +#elif (RTE_USART2_CTS_ID == 1) +#define RTE_USART2_CTS 1 +#define RTE_USART2_CTS_PORT GPIOA +#define RTE_USART2_CTS_BIT 0 +#elif (RTE_USART2_CTS_ID == 2) +#define RTE_USART2_CTS 1 +#define RTE_USART2_CTS_PORT GPIOD +#define RTE_USART2_CTS_BIT 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 <2=>PD4 +#define RTE_USART2_RTS_ID 0 +#if (RTE_USART2_RTS_ID == 0) +#define RTE_USART2_RTS 0 +#elif (RTE_USART2_RTS_ID == 1) +#define RTE_USART2_RTS 1 +#define RTE_USART2_RTS_PORT GPIOA +#define RTE_USART2_RTS_BIT 1 +#elif (RTE_USART2_RTS_ID == 2) +#define RTE_USART2_RTS 1 +#define RTE_USART2_RTS_PORT GPIOD +#define RTE_USART2_RTS_BIT 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <4=>4 <6=>6 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_STREAM 5 +#define RTE_USART2_RX_DMA_CHANNEL 4 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_STREAM 6 +#define RTE_USART2_TX_DMA_CHANNEL 4 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 <2=>PC10 <3=>PD8 +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) +#define RTE_USART3_TX 0 +#elif (RTE_USART3_TX_ID == 1) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOB +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 2) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOC +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 3) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOD +#define RTE_USART3_TX_BIT 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 <2=>PC11 <3=>PD9 <4=>PC5 +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) +#define RTE_USART3_RX 0 +#elif (RTE_USART3_RX_ID == 1) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOB +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 2) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 3) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOD +#define RTE_USART3_RX_BIT 9 +#elif (RTE_USART3_RX_ID == 4) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 5 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 <2=>PC12 <3=>PD10 +#define RTE_USART3_CK_ID 0 +#if (RTE_USART3_CK_ID == 0) +#define RTE_USART3_CK 0 +#elif (RTE_USART3_CK_ID == 1) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOB +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 2) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOC +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 3) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOD +#define RTE_USART3_CK_BIT 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 <2=>PD11 +#define RTE_USART3_CTS_ID 0 +#if (RTE_USART3_CTS_ID == 0) +#define RTE_USART3_CTS 0 +#elif (RTE_USART3_CTS_ID == 1) +#define RTE_USART3_CTS 1 +#define RTE_USART3_CTS_PORT GPIOB +#define RTE_USART3_CTS_BIT 13 +#elif (RTE_USART3_CTS_ID == 2) +#define RTE_USART3_CTS 1 +#define RTE_USART3_CTS_PORT GPIOD +#define RTE_USART3_CTS_BIT 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 <2=>PD12 +#define RTE_USART3_RTS_ID 0 +#if (RTE_USART3_RTS_ID == 0) +#define RTE_USART3_RTS 0 +#elif (RTE_USART3_RTS_ID == 1) +#define RTE_USART3_RTS 1 +#define RTE_USART3_RTS_PORT GPIOB +#define RTE_USART3_RTS_BIT 14 +#elif (RTE_USART3_RTS_ID == 2) +#define RTE_USART3_RTS 1 +#define RTE_USART3_RTS_PORT GPIOD +#define RTE_USART3_RTS_BIT 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <4=>4 +// Selects DMA Stream (only Stream 1 or 4 can be used) +// Channel <4=>4 <7=>7 +// Selects DMA Channel (only Channel 4 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_STREAM 1 +#define RTE_USART3_RX_DMA_CHANNEL 4 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 <4=>4 +// Selects DMA Stream (only Stream 3 or 4 can be used) +// Channel <4=>4 <7=>7 +// Selects DMA Channel (only Channel 4 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_STREAM 3 +#define RTE_USART3_TX_DMA_CHANNEL 4 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 + +// UART4_TX Pin <0=>Not Used <1=>PA0 <2=>PC10 <3=>PD10 <4=>PA12 <5=>PD1 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 0 +#elif (RTE_UART4_TX_ID == 2) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#elif (RTE_UART4_TX_ID == 3) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOD +#define RTE_UART4_TX_BIT 10 +#elif (RTE_UART4_TX_ID == 4) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 12 +#elif (RTE_UART4_TX_ID == 5) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOD +#define RTE_UART4_TX_BIT 1 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PA1 <2=>PC11 <3=>PA11 <4=>PD0 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 1 +#elif (RTE_UART4_RX_ID == 2) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#elif (RTE_UART4_RX_ID == 3) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 11 +#elif (RTE_UART4_RX_ID == 4) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOD +#define RTE_UART4_RX_BIT 0 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 1 +#define RTE_UART4_RX_DMA_STREAM 2 +#define RTE_UART4_RX_DMA_CHANNEL 4 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 1 +#define RTE_UART4_TX_DMA_STREAM 4 +#define RTE_UART4_TX_DMA_CHANNEL 4 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 + +// UART5_TX Pin <0=>Not Used <1=>PC12 <2=>PB6 <3=>PB9 <4=>PB13 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#elif (RTE_UART5_TX_ID == 2) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 6 +#elif (RTE_UART5_TX_ID == 3) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 9 +#elif (RTE_UART5_TX_ID == 4) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 13 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 <2=>PB5 <3=>PB8 <4=>PB12 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#elif (RTE_UART5_TX_ID == 2) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 5 +#elif (RTE_UART5_TX_ID == 3) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 8 +#elif (RTE_UART5_TX_ID == 4) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_RX_DMA 0 +#define RTE_UART5_RX_DMA_NUMBER 1 +#define RTE_UART5_RX_DMA_STREAM 0 +#define RTE_UART5_RX_DMA_CHANNEL 4 +#define RTE_UART5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 <8=>8 +// Selects DMA Channel (only Channel 4 or 8 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_TX_DMA 0 +#define RTE_UART5_TX_DMA_NUMBER 1 +#define RTE_UART5_TX_DMA_STREAM 7 +#define RTE_UART5_TX_DMA_CHANNEL 4 +#define RTE_UART5_TX_DMA_PRIORITY 0 + +// + + +// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::CMSIS Driver:USART +#define RTE_USART6 0 + +// USART6_TX Pin <0=>Not Used <1=>PA11 <2=>PC6 <3=>PG14 +#define RTE_USART6_TX_ID 0 +#if (RTE_USART6_TX_ID == 0) +#define RTE_USART6_TX 0 +#elif (RTE_USART6_TX_ID == 1) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOA +#define RTE_USART6_TX_BIT 11 +#elif (RTE_USART6_TX_ID == 2) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOC +#define RTE_USART6_TX_BIT 6 +#elif (RTE_USART6_TX_ID == 3) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOG +#define RTE_USART6_TX_BIT 14 +#else +#error "Invalid USART6_TX Pin Configuration!" +#endif + +// USART6_RX Pin <0=>Not Used <1=>PA12 <2=>PC7 <3=>PG9 +#define RTE_USART6_RX_ID 0 +#if (RTE_USART6_RX_ID == 0) +#define RTE_USART6_RX 0 +#elif (RTE_USART6_RX_ID == 1) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOA +#define RTE_USART6_RX_BIT 12 +#elif (RTE_USART6_RX_ID == 2) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOC +#define RTE_USART6_RX_BIT 7 +#elif (RTE_USART6_RX_ID == 3) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOG +#define RTE_USART6_RX_BIT 9 +#else +#error "Invalid USART6_RX Pin Configuration!" +#endif + +// USART6_CK Pin <0=>Not Used <1=>PC8 <2=>PG7 +#define RTE_USART6_CK_ID 0 +#if (RTE_USART6_CK_ID == 0) +#define RTE_USART6_CK 0 +#elif (RTE_USART6_CK_ID == 1) +#define RTE_USART6_CK 1 +#define RTE_USART6_CK_PORT GPIOC +#define RTE_USART6_CK_BIT 8 +#elif (RTE_USART6_CK_ID == 2) +#define RTE_USART6_CK 1 +#define RTE_USART6_CK_PORT GPIOG +#define RTE_USART6_CK_BIT 7 +#else +#error "Invalid USART6_CK Pin Configuration!" +#endif + +// USART6_CTS Pin <0=>Not Used <1=>PG13 <2=>PG15 +#define RTE_USART6_CTS_ID 0 +#if (RTE_USART6_CTS_ID == 0) +#define RTE_USART6_CTS 0 +#elif (RTE_USART6_CTS_ID == 1) +#define RTE_USART6_CTS 1 +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 13 +#elif (RTE_USART6_CTS_ID == 2) +#define RTE_USART6_CTS 1 +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 15 +#else +#error "Invalid USART6_CTS Pin Configuration!" +#endif + +// USART6_RTS Pin <0=>Not Used <1=>PG8 <2=>PG12 +#define RTE_USART6_RTS_ID 0 +#if (RTE_USART6_RTS_ID == 0) +#define RTE_USART6_RTS 0 +#elif (RTE_USART6_RTS_ID == 1) +#define RTE_USART6_RTS 1 +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 8 +#elif (RTE_USART6_RTS_ID == 2) +#define RTE_USART6_RTS 1 +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 12 +#else +#error "Invalid USART6_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_RX_DMA 0 +#define RTE_USART6_RX_DMA_NUMBER 2 +#define RTE_USART6_RX_DMA_STREAM 1 +#define RTE_USART6_RX_DMA_CHANNEL 5 +#define RTE_USART6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_TX_DMA 0 +#define RTE_USART6_TX_DMA_NUMBER 2 +#define RTE_USART6_TX_DMA_STREAM 6 +#define RTE_USART6_TX_DMA_CHANNEL 5 +#define RTE_USART6_TX_DMA_PRIORITY 0 + +// + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::CMSIS Driver:USART +#define RTE_UART7 0 + +// UART7_TX Pin <0=>Not Used <1=>PF7 <2=>PE8 <3=>PA15 <4=>PB4 +#define RTE_UART7_TX_ID 0 +#if (RTE_UART7_TX_ID == 0) +#define RTE_UART7_TX 0 +#elif (RTE_UART7_TX_ID == 1) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOF +#define RTE_UART7_TX_BIT 7 +#elif (RTE_UART7_TX_ID == 2) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOE +#define RTE_UART7_TX_BIT 8 +#elif (RTE_UART7_TX_ID == 3) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOA +#define RTE_UART7_TX_BIT 15 +#elif (RTE_UART7_TX_ID == 4) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOB +#define RTE_UART7_TX_BIT 4 +#else +#error "Invalid UART7_TX Pin Configuration!" +#endif + +// UART7_RX Pin <0=>Not Used <1=>PF6 <2=>PE7 <3=>PA8 <4=>PB3 +#define RTE_UART7_RX_ID 0 +#if (RTE_UART7_RX_ID == 0) +#define RTE_UART7_RX 0 +#elif (RTE_UART7_RX_ID == 1) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOF +#define RTE_UART7_RX_BIT 6 +#elif (RTE_UART7_RX_ID == 2) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOE +#define RTE_UART7_RX_BIT 7 +#elif (RTE_UART7_RX_ID == 3) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOA +#define RTE_UART7_RX_BIT 8 +#elif (RTE_UART7_RX_ID == 4) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOB +#define RTE_UART7_RX_BIT 3 +#else +#error "Invalid UART7_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART7_RX_DMA 0 +#define RTE_UART7_RX_DMA_NUMBER 1 +#define RTE_UART7_RX_DMA_STREAM 3 +#define RTE_UART7_RX_DMA_CHANNEL 5 +#define RTE_UART7_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART7_TX_DMA 0 +#define RTE_UART7_TX_DMA_NUMBER 1 +#define RTE_UART7_TX_DMA_STREAM 1 +#define RTE_UART7_TX_DMA_CHANNEL 5 +#define RTE_UART7_TX_DMA_PRIORITY 0 + +// + +// UART8 (Universal asynchronous receiver transmitter) [Driver_USART8] +// Configuration settings for Driver_USART8 in component ::CMSIS Driver:USART +#define RTE_UART8 0 + +// UART8_TX Pin <0=>Not Used <1=>PE1 <2=>PF9 +#define RTE_UART8_TX_ID 0 +#if (RTE_UART8_TX_ID == 0) +#define RTE_UART8_TX 0 +#elif (RTE_UART8_TX_ID == 1) +#define RTE_UART8_TX 1 +#define RTE_UART8_TX_PORT GPIOE +#define RTE_UART8_TX_BIT 1 +#elif (RTE_UART8_TX_ID == 2) +#define RTE_UART8_TX 1 +#define RTE_UART8_TX_PORT GPIOF +#define RTE_UART8_TX_BIT 9 +#else +#error "Invalid UART8_TX Pin Configuration!" +#endif + +// UART8_RX Pin <0=>Not Used <1=>PE0 <2=>PF8 +#define RTE_UART8_RX_ID 0 +#if (RTE_UART8_RX_ID == 0) +#define RTE_UART8_RX 0 +#elif (RTE_UART8_RX_ID == 1) +#define RTE_UART8_RX 1 +#define RTE_UART8_RX_PORT GPIOE +#define RTE_UART8_RX_BIT 0 +#elif (RTE_UART8_RX_ID == 2) +#define RTE_UART8_RX 1 +#define RTE_UART8_RX_PORT GPIOF +#define RTE_UART8_RX_BIT 8 +#else +#error "Invalid UART8_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART8_RX_DMA 0 +#define RTE_UART8_RX_DMA_NUMBER 1 +#define RTE_UART8_RX_DMA_STREAM 6 +#define RTE_UART8_RX_DMA_CHANNEL 5 +#define RTE_UART8_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART8_TX_DMA 0 +#define RTE_UART8_TX_DMA_NUMBER 1 +#define RTE_UART8_TX_DMA_STREAM 0 +#define RTE_UART8_TX_DMA_CHANNEL 5 +#define RTE_UART8_TX_DMA_PRIORITY 0 + +// + +// UART9 (Universal asynchronous receiver transmitter) [Driver_USART9] +// Configuration settings for Driver_USART9 in component ::CMSIS Driver:USART +#define RTE_UART9 0 + +// UART9_TX Pin <0=>Not Used <1=>PD15 <2=>PG1 +#define RTE_UART9_TX_ID 0 +#if (RTE_UART9_TX_ID == 0) +#define RTE_UART9_TX 0 +#elif (RTE_UART9_TX_ID == 1) +#define RTE_UART9_TX 1 +#define RTE_UART9_TX_PORT GPIOD +#define RTE_UART9_TX_BIT 15 +#elif (RTE_UART9_TX_ID == 2) +#define RTE_UART9_TX 1 +#define RTE_UART9_TX_PORT GPIOG +#define RTE_UART9_TX_BIT 1 +#else +#error "Invalid UART9_TX Pin Configuration!" +#endif + +// UART9_RX Pin <0=>Not Used <1=>PD14 <2=>PG0 +#define RTE_UART9_RX_ID 0 +#if (RTE_UART9_RX_ID == 0) +#define RTE_UART9_RX 0 +#elif (RTE_UART9_RX_ID == 1) +#define RTE_UART9_RX 1 +#define RTE_UART9_RX_PORT GPIOD +#define RTE_UART9_RX_BIT 14 +#elif (RTE_UART9_RX_ID == 2) +#define RTE_UART9_RX 1 +#define RTE_UART9_RX_PORT GPIOG +#define RTE_UART9_RX_BIT 0 +#else +#error "Invalid UART9_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART9_RX_DMA 0 +#define RTE_UART9_RX_DMA_NUMBER 1 +#define RTE_UART9_RX_DMA_STREAM 6 +#define RTE_UART9_RX_DMA_CHANNEL 5 +#define RTE_UART9_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART9_TX_DMA 0 +#define RTE_UART9_TX_DMA_NUMBER 1 +#define RTE_UART9_TX_DMA_STREAM 0 +#define RTE_UART9_TX_DMA_CHANNEL 5 +#define RTE_UART9_TX_DMA_PRIORITY 0 + +// + +// UART10 (Universal asynchronous receiver transmitter) [Driver_USART10] +// Configuration settings for Driver_USART10 in component ::CMSIS Driver:USART +#define RTE_UART10 0 + +// UART10_TX Pin <0=>Not Used <1=>PE3 <2=>PG12 +#define RTE_UART10_TX_ID 0 +#if (RTE_UART10_TX_ID == 0) +#define RTE_UART10_TX 0 +#elif (RTE_UART10_TX_ID == 1) +#define RTE_UART10_TX 1 +#define RTE_UART10_TX_PORT GPIOE +#define RTE_UART10_TX_BIT 3 +#elif (RTE_UART10_TX_ID == 2) +#define RTE_UART10_TX 1 +#define RTE_UART10_TX_PORT GPIOG +#define RTE_UART10_TX_BIT 12 +#else +#error "Invalid UART10_TX Pin Configuration!" +#endif + +// UART10_RX Pin <0=>Not Used <1=>PE2 <2=>PG11 +#define RTE_UART10_RX_ID 0 +#if (RTE_UART10_RX_ID == 0) +#define RTE_UART10_RX 0 +#elif (RTE_UART10_RX_ID == 1) +#define RTE_UART10_RX 1 +#define RTE_UART10_RX_PORT GPIOE +#define RTE_UART10_RX_BIT 2 +#elif (RTE_UART10_RX_ID == 2) +#define RTE_UART10_RX 1 +#define RTE_UART10_RX_PORT GPIOG +#define RTE_UART10_RX_BIT 11 +#else +#error "Invalid UART10_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <3=>3 +// Selects DMA Stream (only Stream 0 or 3 can be used) +// Channel <5=>5 <9=>9 +// Selects DMA Channel (only Channel 5 or 9 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART10_RX_DMA 0 +#define RTE_UART10_RX_DMA_NUMBER 1 +#define RTE_UART10_RX_DMA_STREAM 6 +#define RTE_UART10_RX_DMA_CHANNEL 5 +#define RTE_UART10_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 <3=>5 +// Selects DMA Stream (only Stream 7 or 5 can be used) +// Channel <6=>6 <9=>9 +// Selects DMA Channel (only Channel 6 or 9 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART10_TX_DMA 0 +#define RTE_UART10_TX_DMA_NUMBER 1 +#define RTE_UART10_TX_DMA_STREAM 0 +#define RTE_UART10_TX_DMA_CHANNEL 5 +#define RTE_UART10_TX_DMA_PRIORITY 0 + +// + + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 <1=>PB8 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 <1=>PB9 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 9 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_STREAM 0 +#define RTE_I2C1_RX_DMA_CHANNEL 1 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <6=>6 <7=>7 +// Selects DMA Stream (only Stream 1 or 6 or 7 can be used) +// Channel <0=>0 <1=>1 +// Selects DMA Channel (only Channel 0 or 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_STREAM 6 +#define RTE_I2C1_TX_DMA_CHANNEL 1 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 + +// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOF +#define RTE_I2C2_SCL_BIT 1 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT GPIOH +#define RTE_I2C2_SCL_BIT 4 +#elif (RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 <3=>PB3 <4=>PB9 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOF +#define RTE_I2C2_SDA_BIT 0 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT GPIOH +#define RTE_I2C2_SDA_BIT 5 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#elif (RTE_I2C2_SDA_PORT_ID == 3) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 3 +#elif (RTE_I2C2_SDA_PORT_ID == 4) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 9 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 <3=>3 +// Selects DMA Stream (only Stream 2 or 3 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 0 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_STREAM 2 +#define RTE_I2C2_RX_DMA_CHANNEL 7 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 0 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_STREAM 7 +#define RTE_I2C2_TX_DMA_CHANNEL 7 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::CMSIS Driver:I2C +#define RTE_I2C3 0 + +// I2C3_SCL Pin <0=>PH7 <1=>PA8 +#define RTE_I2C3_SCL_PORT_ID 0 +#if (RTE_I2C3_SCL_PORT_ID == 0) +#define RTE_I2C3_SCL_PORT GPIOH +#define RTE_I2C3_SCL_BIT 7 +#elif (RTE_I2C3_SCL_PORT_ID == 1) +#define RTE_I2C3_SCL_PORT GPIOA +#define RTE_I2C3_SCL_BIT 8 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// I2C3_SDA Pin <0=>PH8 <1=>PC9 <2=>PB4 <3=>PB8 +#define RTE_I2C3_SDA_PORT_ID 0 +#if (RTE_I2C3_SDA_PORT_ID == 0) +#define RTE_I2C3_SDA_PORT GPIOH +#define RTE_I2C3_SDA_BIT 8 +#elif (RTE_I2C3_SDA_PORT_ID == 1) +#define RTE_I2C3_SDA_PORT GPIOC +#define RTE_I2C3_SDA_BIT 9 +#elif (RTE_I2C3_SDA_PORT_ID == 2) +#define RTE_I2C3_SDA_PORT GPIOB +#define RTE_I2C3_SDA_BIT 4 +#elif (RTE_I2C3_SDA_PORT_ID == 3) +#define RTE_I2C3_SDA_PORT GPIOB +#define RTE_I2C3_SDA_BIT 8 +#else +#error "Invalid I2C3_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <1=>1 <3=>3 +// Selects DMA Channel (only Channel 1 or 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_RX_DMA 0 +#define RTE_I2C3_RX_DMA_NUMBER 1 +#define RTE_I2C3_RX_DMA_STREAM 2 +#define RTE_I2C3_RX_DMA_CHANNEL 3 +#define RTE_I2C3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 <5=>5 +// Selects DMA Stream (only Stream 4 or 5 can be used) +// Channel <3=>3 <6=>6 +// Selects DMA Channel (only Channel 3 or 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_TX_DMA 0 +#define RTE_I2C3_TX_DMA_NUMBER 1 +#define RTE_I2C3_TX_DMA_STREAM 4 +#define RTE_I2C3_TX_DMA_CHANNEL 3 +#define RTE_I2C3_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 <2=>PB4 +#define RTE_SPI1_MISO_PORT_ID 0 +#if (RTE_SPI1_MISO_PORT_ID == 0) +#define RTE_SPI1_MISO 0 +#elif (RTE_SPI1_MISO_PORT_ID == 1) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOA +#define RTE_SPI1_MISO_BIT 6 +#elif (RTE_SPI1_MISO_PORT_ID == 2) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOB +#define RTE_SPI1_MISO_BIT 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 <2=>PB5 +#define RTE_SPI1_MOSI_PORT_ID 0 +#if (RTE_SPI1_MOSI_PORT_ID == 0) +#define RTE_SPI1_MOSI 0 +#elif (RTE_SPI1_MOSI_PORT_ID == 1) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOA +#define RTE_SPI1_MOSI_BIT 7 +#elif (RTE_SPI1_MOSI_PORT_ID == 2) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOB +#define RTE_SPI1_MOSI_BIT 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// SPI1_SCK Pin <0=>PA5 <1=>PB3 +#define RTE_SPI1_SCL_PORT_ID 0 +#if (RTE_SPI1_SCL_PORT_ID == 0) +#define RTE_SPI1_SCL_PORT GPIOA +#define RTE_SPI1_SCL_BIT 5 +#elif (RTE_SPI1_SCL_PORT_ID == 1) +#define RTE_SPI1_SCL_PORT GPIOB +#define RTE_SPI1_SCL_BIT 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 +#define RTE_SPI1_NSS_PORT_ID 0 +#if (RTE_SPI1_NSS_PORT_ID == 0) +#define RTE_SPI1_NSS_PIN 0 +#elif (RTE_SPI1_NSS_PORT_ID == 1) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOA +#define RTE_SPI1_NSS_BIT 4 +#elif (RTE_SPI1_NSS_PORT_ID == 2) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOA +#define RTE_SPI1_NSS_BIT 15 +#else +#error "Invalid SPI1_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 2 +#define RTE_SPI1_RX_DMA_STREAM 0 +#define RTE_SPI1_RX_DMA_CHANNEL 3 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <3=>3 <5=>5 +// Selects DMA Stream (only Stream 2 or 3 or 5 can be used) +// Channel <2=>2 <3=>3 +// Selects DMA Channel (only Channel 2 or 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 2 +#define RTE_SPI1_TX_DMA_STREAM 5 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 <2=>PC2 <3=>PI2 <4=>PA12 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#elif (RTE_SPI2_MISO_PORT_ID == 2) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOC +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 3) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOI +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 4) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOA +#define RTE_SPI2_MISO_BIT 12 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 <2=>PC3 <3=>PI3 <4=>PA10 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#elif (RTE_SPI2_MOSI_PORT_ID == 2) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 3) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOI +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 4) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOA +#define RTE_SPI2_MOSI_BIT 10 +#else +#error "Invalid SPI2_MOSI Pin Configuration!" +#endif + +// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PC7 <3=>PD3 <4=>PI1 <5=>PA9 +#define RTE_SPI2_SCL_PORT_ID 0 +#if (RTE_SPI2_SCL_PORT_ID == 0) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 10 +#elif (RTE_SPI2_SCL_PORT_ID == 1) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 13 +#elif (RTE_SPI2_SCL_PORT_ID == 2) +#define RTE_SPI2_SCL_PORT GPIOC +#define RTE_SPI2_SCL_BIT 7 +#elif (RTE_SPI2_SCL_PORT_ID == 3) +#define RTE_SPI2_SCL_PORT GPIOD +#define RTE_SPI2_SCL_BIT 3 +#elif (RTE_SPI2_SCL_PORT_ID == 4) +#define RTE_SPI2_SCL_PORT GPIOI +#define RTE_SPI2_SCL_BIT 1 +#elif (RTE_SPI2_SCL_PORT_ID == 5) +#define RTE_SPI2_SCL_PORT GPIOA +#define RTE_SPI2_SCL_BIT 9 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_NSS Pin <0=>Not Used <1=>PB9 <2=>PB12 <3=>PI0 <4=>PA11 +#define RTE_SPI2_NSS_PORT_ID 0 +#if (RTE_SPI2_NSS_PORT_ID == 0) +#define RTE_SPI2_NSS_PIN 0 +#elif (RTE_SPI2_NSS_PORT_ID == 1) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 9 +#elif (RTE_SPI2_NSS_PORT_ID == 2) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 12 +#elif (RTE_SPI2_NSS_PORT_ID == 3) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOI +#define RTE_SPI2_NSS_BIT 0 +#elif (RTE_SPI2_NSS_PORT_ID == 4) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOA +#define RTE_SPI2_NSS_BIT 11 +#else +#error "Invalid SPI2_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_STREAM 3 +#define RTE_SPI2_RX_DMA_CHANNEL 0 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_STREAM 4 +#define RTE_SPI2_TX_DMA_CHANNEL 0 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 <2=>PC11 +#define RTE_SPI3_MISO_PORT_ID 0 +#if (RTE_SPI3_MISO_PORT_ID == 0) +#define RTE_SPI3_MISO 0 +#elif (RTE_SPI3_MISO_PORT_ID == 1) +#define RTE_SPI3_MISO 1 +#define RTE_SPI3_MISO_PORT GPIOB +#define RTE_SPI3_MISO_BIT 4 +#elif (RTE_SPI3_MISO_PORT_ID == 2) +#define RTE_SPI3_MISO 1 +#define RTE_SPI3_MISO_PORT GPIOC +#define RTE_SPI3_MISO_BIT 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI Pin <0=>Not Used <1=>PB5 <2=>PC12 <3=>PD6 +#define RTE_SPI3_MOSI_PORT_ID 0 +#if (RTE_SPI3_MOSI_PORT_ID == 0) +#define RTE_SPI3_MOSI 0 +#elif (RTE_SPI3_MOSI_PORT_ID == 1) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 5 +#elif (RTE_SPI3_MOSI_PORT_ID == 2) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOC +#define RTE_SPI3_MOSI_BIT 12 +#elif (RTE_SPI3_MOSI_PORT_ID == 3) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOD +#define RTE_SPI3_MOSI_BIT 6 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3_SCK Pin <0=>PB3 <1=>PB12 <2=>PC10 +#define RTE_SPI3_SCL_PORT_ID 0 +#if (RTE_SPI3_SCL_PORT_ID == 0) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 3 +#elif (RTE_SPI3_SCL_PORT_ID == 1) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 12 +#elif (RTE_SPI3_SCL_PORT_ID == 2) +#define RTE_SPI3_SCL_PORT GPIOC +#define RTE_SPI3_SCL_BIT 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 +#define RTE_SPI3_NSS_PORT_ID 0 +#if (RTE_SPI3_NSS_PORT_ID == 0) +#define RTE_SPI3_NSS_PIN 0 +#elif (RTE_SPI3_NSS_PORT_ID == 1) +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIOA +#define RTE_SPI3_NSS_BIT 4 +#elif (RTE_SPI3_NSS_PORT_ID == 2) +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIOA +#define RTE_SPI3_NSS_BIT 15 +#else +#error "Invalid SPI3_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 1 +#define RTE_SPI3_RX_DMA_STREAM 0 +#define RTE_SPI3_RX_DMA_CHANNEL 0 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 1 +#define RTE_SPI3_TX_DMA_STREAM 5 +#define RTE_SPI3_TX_DMA_CHANNEL 0 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] +// Configuration settings for Driver_SPI4 in component ::CMSIS Driver:SPI +#define RTE_SPI4 0 + +// SPI4_MISO Pin <0=>Not Used <1=>PA11 <2=>PE5 <3=>PE13 +#define RTE_SPI4_MISO_PORT_ID 0 +#if (RTE_SPI4_MISO_PORT_ID == 0) +#define RTE_SPI4_MISO 0 +#elif (RTE_SPI4_MISO_PORT_ID == 1) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOA +#define RTE_SPI4_MISO_BIT 11 +#elif (RTE_SPI4_MISO_PORT_ID == 2) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOE +#define RTE_SPI4_MISO_BIT 5 +#elif (RTE_SPI4_MISO_PORT_ID == 3) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOE +#define RTE_SPI4_MISO_BIT 13 +#else +#error "Invalid SPI4_MISO Pin Configuration!" +#endif + +// SPI4_MOSI Pin <0=>Not Used <1=>PA1 <2=>PE6 <3=>PE14 +#define RTE_SPI4_MOSI_PORT_ID 0 +#if (RTE_SPI4_MOSI_PORT_ID == 0) +#define RTE_SPI4_MOSI 0 +#elif (RTE_SPI4_MOSI_PORT_ID == 1) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOA +#define RTE_SPI4_MOSI_BIT 1 +#elif (RTE_SPI4_MOSI_PORT_ID == 2) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOE +#define RTE_SPI4_MOSI_BIT 6 +#elif (RTE_SPI4_MOSI_PORT_ID == 3) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOE +#define RTE_SPI4_MOSI_BIT 14 +#else +#error "Invalid SPI4_MOSI Pin Configuration!" +#endif + +// SPI4_SCK Pin <0=>PB13 <1=>PE2 <2=>PE12 +#define RTE_SPI4_SCL_PORT_ID 0 +#if (RTE_SPI4_SCL_PORT_ID == 0) +#define RTE_SPI4_SCL_PORT GPIOB +#define RTE_SPI4_SCL_BIT 13 +#elif (RTE_SPI4_SCL_PORT_ID == 1) +#define RTE_SPI4_SCL_PORT GPIOE +#define RTE_SPI4_SCL_BIT 2 +#elif (RTE_SPI4_SCL_PORT_ID == 2) +#define RTE_SPI4_SCL_PORT GPIOE +#define RTE_SPI4_SCL_BIT 12 +#else +#error "Invalid SPI4_SCK Pin Configuration!" +#endif + +// SPI4_NSS Pin <0=>Not Used <1=>PB12 <2=>PE4 <3=>PE11 +#define RTE_SPI4_NSS_PORT_ID 0 +#if (RTE_SPI4_NSS_PORT_ID == 0) +#define RTE_SPI4_NSS_PIN 0 +#elif (RTE_SPI4_NSS_PORT_ID == 1) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOB +#define RTE_SPI4_NSS_BIT 12 +#elif (RTE_SPI4_NSS_PORT_ID == 2) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOE +#define RTE_SPI4_NSS_BIT 4 +#elif (RTE_SPI4_NSS_PORT_ID == 3) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOE +#define RTE_SPI4_NSS_BIT 11 +#else +#error "Invalid SPI4_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <3=>3 <4=>4 +// Selects DMA Stream (only Stream 0 or 3 can be used) +// Channel <4=>4 <5=>5 +// Selects DMA Channel (only Channel 4 or 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI4_RX_DMA 0 +#define RTE_SPI4_RX_DMA_NUMBER 1 +#define RTE_SPI4_RX_DMA_STREAM 0 +#define RTE_SPI4_RX_DMA_CHANNEL 0 +#define RTE_SPI4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <4=>4 +// Selects DMA Stream (only Stream 1 or 4 can be used) +// Channel <4=>4 <5=>5 +// Selects DMA Channel (only Channel 4 or 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI4_TX_DMA 0 +#define RTE_SPI4_TX_DMA_NUMBER 1 +#define RTE_SPI4_TX_DMA_STREAM 5 +#define RTE_SPI4_TX_DMA_CHANNEL 0 +#define RTE_SPI4_TX_DMA_PRIORITY 0 + +// + + +// SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] +// Configuration settings for Driver_SPI5 in component ::CMSIS Driver:SPI +#define RTE_SPI5 0 + +// SPI5_MISO Pin <0=>Not Used <1=>PA12 <2=>PE5 <3=>PE13 <4=>PF8 <5=>PH7 +#define RTE_SPI5_MISO_PORT_ID 0 +#if (RTE_SPI5_MISO_PORT_ID == 0) +#define RTE_SPI5_MISO 0 +#elif (RTE_SPI5_MISO_PORT_ID == 1) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOA +#define RTE_SPI5_MISO_BIT 12 +#elif (RTE_SPI5_MISO_PORT_ID == 2) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOE +#define RTE_SPI5_MISO_BIT 5 +#elif (RTE_SPI5_MISO_PORT_ID == 3) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOE +#define RTE_SPI5_MISO_BIT 13 +#elif (RTE_SPI5_MISO_PORT_ID == 4) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOF +#define RTE_SPI5_MISO_BIT 8 +#elif (RTE_SPI5_MISO_PORT_ID == 5) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOH +#define RTE_SPI5_MISO_BIT 7 +#else +#error "Invalid SPI5_MISO Pin Configuration!" +#endif + +// SPI5_MOSI Pin <0=>Not Used <1=>PA10 <2=>PB8 <3=>PE6 <4=>PE14 <5=>PF9 <6=>PF11 +#define RTE_SPI5_MOSI_PORT_ID 0 +#if (RTE_SPI5_MOSI_PORT_ID == 0) +#define RTE_SPI5_MOSI 0 +#elif (RTE_SPI5_MOSI_PORT_ID == 1) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOA +#define RTE_SPI5_MOSI_BIT 10 +#elif (RTE_SPI5_MOSI_PORT_ID == 2) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOB +#define RTE_SPI5_MOSI_BIT 8 +#elif (RTE_SPI5_MOSI_PORT_ID == 3) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOE +#define RTE_SPI5_MOSI_BIT 6 +#elif (RTE_SPI5_MOSI_PORT_ID == 4) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOE +#define RTE_SPI5_MOSI_BIT 14 +#elif (RTE_SPI5_MOSI_PORT_ID == 5) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOF +#define RTE_SPI5_MOSI_BIT 9 +#elif (RTE_SPI5_MOSI_PORT_ID == 6) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOF +#define RTE_SPI5_MOSI_BIT 11 +#else +#error "Invalid SPI5_MOSI Pin Configuration!" +#endif + +// SPI5_SCK Pin <0=>PB0 <1=>PE2 <2=>PE12 <3=>PF7 <4=>PH6 +#define RTE_SPI5_SCL_PORT_ID 0 +#if (RTE_SPI5_SCL_PORT_ID == 0) +#define RTE_SPI5_SCL_PORT GPIOB +#define RTE_SPI5_SCL_BIT 0 +#elif (RTE_SPI5_SCL_PORT_ID == 1) +#define RTE_SPI5_SCL_PORT GPIOE +#define RTE_SPI5_SCL_BIT 2 +#elif (RTE_SPI5_SCL_PORT_ID == 2) +#define RTE_SPI5_SCL_PORT GPIOE +#define RTE_SPI5_SCL_BIT 12 +#elif (RTE_SPI5_SCL_PORT_ID == 3) +#define RTE_SPI5_SCL_PORT GPIOF +#define RTE_SPI5_SCL_BIT 7 +#elif (RTE_SPI5_SCL_PORT_ID == 4) +#define RTE_SPI5_SCL_PORT GPIOH +#define RTE_SPI5_SCL_BIT 6 +#else +#error "Invalid SPI5_SCK Pin Configuration!" +#endif + +// SPI5_NSS Pin <0=>Not Used <1=>PB1 <2=>PE4 <3=>PE11 <4=>PF6 <5=>PH5 +#define RTE_SPI5_NSS_PORT_ID 0 +#if (RTE_SPI5_NSS_PORT_ID == 0) +#define RTE_SPI5_NSS_PIN 0 +#elif (RTE_SPI5_NSS_PORT_ID == 1) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOB +#define RTE_SPI5_NSS_BIT 1 +#elif (RTE_SPI5_NSS_PORT_ID == 2) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOE +#define RTE_SPI5_NSS_BIT 4 +#elif (RTE_SPI5_NSS_PORT_ID == 3) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOE +#define RTE_SPI5_NSS_BIT 11 +#elif (RTE_SPI5_NSS_PORT_ID == 4) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOF +#define RTE_SPI5_NSS_BIT 6 +#elif (RTE_SPI5_NSS_PORT_ID == 5) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOH +#define RTE_SPI5_NSS_BIT 5 +#else +#error "Invalid SPI5_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <2=>2 <7=>7 +// Selects DMA Channel (only Channel 2 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI5_RX_DMA 0 +#define RTE_SPI5_RX_DMA_NUMBER 2 +#define RTE_SPI5_RX_DMA_STREAM 3 +#define RTE_SPI5_RX_DMA_CHANNEL 2 +#define RTE_SPI5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <4=>4 <5=>5 <6=>6 +// Selects DMA Stream (only Stream 4 or 6 can be used) +// Channel <2=>2 <5=>5 <7=>7 +// Selects DMA Channel (only Channel 2 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI5_TX_DMA 0 +#define RTE_SPI5_TX_DMA_NUMBER 2 +#define RTE_SPI5_TX_DMA_STREAM 4 +#define RTE_SPI5_TX_DMA_CHANNEL 2 +#define RTE_SPI5_TX_DMA_PRIORITY 0 + +// + + +// SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] +// Configuration settings for Driver_SPI6 in component ::CMSIS Driver:SPI +#define RTE_SPI6 0 + +// SPI6_MISO Pin <0=>Not Used <1=>PG12 +#define RTE_SPI6_MISO_PORT_ID 0 +#if (RTE_SPI6_MISO_PORT_ID == 0) +#define RTE_SPI6_MISO 0 +#elif (RTE_SPI6_MISO_PORT_ID == 1) +#define RTE_SPI6_MISO 1 +#define RTE_SPI6_MISO_PORT GPIOG +#define RTE_SPI6_MISO_BIT 12 +#else +#error "Invalid SPI6_MISO Pin Configuration!" +#endif + +// SPI6_MOSI Pin <0=>Not Used <1=>PG14 +#define RTE_SPI6_MOSI_PORT_ID 0 +#if (RTE_SPI6_MOSI_PORT_ID == 0) +#define RTE_SPI6_MOSI 0 +#elif (RTE_SPI6_MOSI_PORT_ID == 1) +#define RTE_SPI6_MOSI 1 +#define RTE_SPI6_MOSI_PORT GPIOG +#define RTE_SPI6_MOSI_BIT 14 +#else +#error "Invalid SPI6_MOSI Pin Configuration!" +#endif + +// SPI6_SCK Pin <0=>PG13 +#define RTE_SPI6_SCL_PORT_ID 0 +#if (RTE_SPI6_SCL_PORT_ID == 0) +#define RTE_SPI6_SCL_PORT GPIOG +#define RTE_SPI6_SCL_BIT 13 +#else +#error "Invalid SPI6_SCK Pin Configuration!" +#endif + +// SPI6_NSS Pin <0=>Not Used <1=>PG8 +#define RTE_SPI6_NSS_PORT_ID 0 +#if (RTE_SPI6_NSS_PORT_ID == 0) +#define RTE_SPI6_NSS_PIN 0 +#elif (RTE_SPI6_NSS_PORT_ID == 1) +#define RTE_SPI6_NSS_PIN 1 +#define RTE_SPI6_NSS_PORT GPIOG +#define RTE_SPI6_NSS_BIT 8 +#else +#error "Invalid SPI6_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI6_RX_DMA 0 +#define RTE_SPI6_RX_DMA_NUMBER 2 +#define RTE_SPI6_RX_DMA_STREAM 6 +#define RTE_SPI6_RX_DMA_CHANNEL 1 +#define RTE_SPI6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI6_TX_DMA 0 +#define RTE_SPI6_TX_DMA_NUMBER 2 +#define RTE_SPI6_TX_DMA_STREAM 5 +#define RTE_SPI6_TX_DMA_CHANNEL 1 +#define RTE_SPI6_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 <1=>PB15 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN GPIO_PIN_12 +#elif (RTE_SDIO_CK_PORT_ID == 1) + #define RTE_SDIO_CK_PORT GPIOB + #define RTE_SDIO_CK_PIN GPIO_PIN_15 +#else + #error "Invalid SD_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 <1=>PA6 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN GPIO_PIN_2 +#elif (RTE_SDIO_CMD_PORT_ID == 1) + #define RTE_SDIO_CMD_PORT GPIOA + #define RTE_SDIO_CMD_PIN GPIO_PIN_6 +#else + #error "Invalid SD_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 <1=>PB4 <2=>PB6 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN GPIO_PIN_8 +#elif (RTE_SDIO_D0_PORT_ID == 1) + #define RTE_SDIO_D0_PORT GPIOB + #define RTE_SDIO_D0_PIN GPIO_PIN_4 +#elif (RTE_SDIO_D0_PORT_ID == 2) + #define RTE_SDIO_D0_PORT GPIOB + #define RTE_SDIO_D0_PIN GPIO_PIN_6 +#else + #error "Invalid SD_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 <1=>PA8 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN GPIO_PIN_9 +#elif (RTE_SDIO_D1_PORT_ID == 1) + #define RTE_SDIO_D1_PORT GPIOA + #define RTE_SDIO_D1_PIN GPIO_PIN_8 +#else + #error "Invalid SD_DAT1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 <1=>PA9 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN GPIO_PIN_10 +#elif (RTE_SDIO_D2_PORT_ID == 1) + #define RTE_SDIO_D2_PORT GPIOA + #define RTE_SDIO_D2_PIN GPIO_PIN_9 +#else + #error "Invalid SD_DAT2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 <1=>PB5 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN GPIO_PIN_11 +#elif (RTE_SDIO_D3_PORT_ID == 1) + #define RTE_SDIO_D3_PORT GPIOB + #define RTE_SDIO_D3_PIN GPIO_PIN_5 +#else + #error "Invalid SD_DAT3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN GPIO_PIN_8 +#else + #error "Invalid SD_DAT4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN GPIO_PIN_9 +#else + #error "Invalid SD_DAT5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 <1=>PB14 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN GPIO_PIN_6 +#elif (RTE_SDIO_D6_PORT_ID == 1) + #define RTE_SDIO_D6_PORT GPIOB + #define RTE_SDIO_D6_PIN GPIO_PIN_14 +#else + #error "Invalid SD_DAT6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 <1=>PB10 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN GPIO_PIN_7 +#elif (RTE_SDIO_D7_PORT_ID == 1) + #define RTE_SDIO_D7_PORT GPIOB + #define RTE_SDIO_D7_PIN GPIO_PIN_10 +#else + #error "Invalid SD_DAT7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_PIN_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(7) +#define RTE_SDIO_CD_PIN 15 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(7) +#define RTE_SDIO_WP_PIN 10 + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_RX_DMA 1 +#define RTE_SDIO_RX_DMA_NUMBER 2 +#define RTE_SDIO_RX_DMA_STREAM 3 +#define RTE_SDIO_RX_DMA_CHANNEL 4 +#define RTE_SDIO_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_TX_DMA 1 +#define RTE_SDIO_TX_DMA_NUMBER 2 +#define RTE_SDIO_TX_DMA_STREAM 6 +#define RTE_SDIO_TX_DMA_CHANNEL 4 +#define RTE_SDIO_TX_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 <3=>PI9 <4=>PG0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT GPIO_PIN_11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT GPIO_PIN_8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT GPIO_PIN_0 +#elif (RTE_CAN1_RX_PORT_ID == 3) +#define RTE_CAN1_RX_PORT GPIOI +#define RTE_CAN1_RX_BIT GPIO_PIN_9 +#elif (RTE_CAN1_RX_PORT_ID == 4) +#define RTE_CAN1_RX_PORT GPIOG +#define RTE_CAN1_RX_BIT GPIO_PIN_0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 <3=>PH13 <4=>PG1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT GPIO_PIN_12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT GPIO_PIN_9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT GPIO_PIN_1 +#elif (RTE_CAN1_TX_PORT_ID == 3) +#define RTE_CAN1_TX_PORT GPIOH +#define RTE_CAN1_TX_BIT GPIO_PIN_13 +#elif (RTE_CAN1_TX_PORT_ID == 4) +#define RTE_CAN1_TX_PORT GPIOG +#define RTE_CAN1_TX_BIT GPIO_PIN_1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 <2=>PG11 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT GPIO_PIN_5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT GPIO_PIN_12 +#elif (RTE_CAN2_RX_PORT_ID == 2) +#define RTE_CAN2_RX_PORT GPIOG +#define RTE_CAN2_RX_BIT GPIO_PIN_11 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 <2=>PG12 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT GPIO_PIN_6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT GPIO_PIN_13 +#elif (RTE_CAN2_TX_PORT_ID == 2) +#define RTE_CAN2_TX_PORT GPIOG +#define RTE_CAN2_TX_BIT GPIO_PIN_12 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// CAN3 (Controller Area Network 3) [Driver_CAN3] +// Configuration settings for Driver_CAN3 in component ::CMSIS Driver:CAN +// Available only on STM32F413xx and STM32F423xx device series +#define RTE_CAN3 0 + +// CAN3_RX Pin <0=>PA8 <1=>PB3 +#define RTE_CAN3_RX_PORT_ID 0 +#if (RTE_CAN3_RX_PORT_ID == 0) +#define RTE_CAN3_RX_PORT GPIOA +#define RTE_CAN3_RX_BIT GPIO_PIN_8 +#elif (RTE_CAN3_RX_PORT_ID == 1) +#define RTE_CAN3_RX_PORT GPIOB +#define RTE_CAN3_RX_BIT GPIO_PIN_3 +#else +#error "Invalid CAN3_RX Pin Configuration!" +#endif + +// CAN3_TX Pin <0=>PA15 <1=>PB4 +#define RTE_CAN3_TX_PORT_ID 0 +#if (RTE_CAN3_TX_PORT_ID == 0) +#define RTE_CAN3_TX_PORT GPIOA +#define RTE_CAN3_TX_BIT GPIO_PIN_15 +#elif (RTE_CAN3_TX_PORT_ID == 1) +#define RTE_CAN3_TX_PORT GPIOB +#define RTE_CAN3_TX_BIT GPIO_PIN_4 +#else +#error "Invalid CAN3_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +#define RTE_ETH_MII 1 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) +#define RTE_ETH_MII_TXD0_PORT GPIOG +#define RTE_ETH_MII_TXD0_PIN 13 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) +#define RTE_ETH_MII_TXD1_PORT GPIOG +#define RTE_ETH_MII_TXD1_PIN 14 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) +#define RTE_ETH_MII_TXD3_PORT GPIOE +#define RTE_ETH_MII_TXD3_PIN 2 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) +#define RTE_ETH_MII_TX_EN_PORT GPIOG +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_PORT_ID 0 +#if (RTE_ETH_MII_RXD0_PORT_ID == 0) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_PORT_ID 0 +#if (RTE_ETH_MII_RXD1_PORT_ID == 0) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif +// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 +#define RTE_ETH_MII_RXD2_PORT_ID 0 +#if (RTE_ETH_MII_RXD2_PORT_ID == 0) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) +#define RTE_ETH_MII_RXD2_PORT GPIOH +#define RTE_ETH_MII_RXD2_PIN 6 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 +#define RTE_ETH_MII_RXD3_PORT_ID 0 +#if (RTE_ETH_MII_RXD3_PORT_ID == 0) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RXD3_PORT GPIOH +#define RTE_ETH_MII_RXD3_PIN 7 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_PORT_ID 0 +#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif +// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#elif (RTE_ETH_MII_RX_ER_PORT_ID == 1) +#define RTE_ETH_MII_RX_ER_PORT GPIOI +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#elif (RTE_ETH_MII_CRS_PORT_ID == 1) +#define RTE_ETH_MII_CRS_PORT GPIOH +#define RTE_ETH_MII_CRS_PIN 2 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 <1=>PH3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#elif (RTE_ETH_MII_COL_PORT_ID == 1) +#define RTE_ETH_MII_COL_PORT GPIOH +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) +#define RTE_ETH_RMII_TXD0_PORT GPIOG +#define RTE_ETH_RMII_TXD0_PIN 13 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) +#define RTE_ETH_RMII_TXD1_PORT GPIOG +#define RTE_ETH_RMII_TXD1_PIN 14 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) +#define RTE_ETH_RMII_TX_EN_PORT GPIOG +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_PORT_ID 0 +#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_PORT_ID 0 +#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 +#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::CMSIS Driver:USB Device + +#define RTE_USB_OTG_FS_DEVICE 1 + +// VBUS Sensing Pin +// Enable or disable VBUS sensing +#define RTE_OTG_FS_VBUS_SENSING_PIN 1 +// + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::CMSIS Driver:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) +#define RTE_OTG_FS_VBUS_BIT 5 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_FS_OC_BIT 11 +// + +// + + +// USB OTG High-speed +#define RTE_USB_OTG_HS 0 + +// PHY (Physical Layer) + +// PHY Interface +// <0=>On-chip full-speed PHY +// <1=>External ULPI high-speed PHY +#define RTE_USB_OTG_HS_PHY 1 + +// External ULPI Pins (UTMI+ Low Pin Interface) + +// OTG_HS_ULPI_CK Pin <0=>PA5 +#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" +#endif +// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 +#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 +#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 +#else +#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" +#endif +// OTG_HS_ULPI_STP Pin <0=>PC0 +#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" +#endif +// OTG_HS_ULPI_NXT Pin <0=>PC3 <1=>PH4 +#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 +#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 3 +#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 +#else +#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" +#endif +// OTG_HS_ULPI_D0 Pin <0=>PA3 +#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 +#else +#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" +#endif +// OTG_HS_ULPI_D1 Pin <0=>PB0 +#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" +#endif +// OTG_HS_ULPI_D2 Pin <0=>PB1 +#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 +#else +#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" +#endif +// OTG_HS_ULPI_D3 Pin <0=>PB10 +#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 +#else +#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" +#endif +// OTG_HS_ULPI_D4 Pin <0=>PB11 +#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 +#else +#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" +#endif +// OTG_HS_ULPI_D5 Pin <0=>PB12 +#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 +#else +#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" +#endif +// OTG_HS_ULPI_D6 Pin <0=>PB13 +#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 +#else +#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" +#endif +// OTG_HS_ULPI_D7 Pin <0=>PB5 +#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" +#endif + +// + +// + +// Device [Driver_USBD1] +// Configuration settings for Driver_USBD1 in component ::CMSIS Driver:USB Device + +#define RTE_USB_OTG_HS_DEVICE 0 + +// VBUS Sensing Pin +// Enable or disable VBUS sensing +// Relevant only if PHY Interface On-chip full-speed PHY is selected +#define RTE_OTG_HS_VBUS_SENSING_PIN 0 +// + +// Host [Driver_USBH1] +// Configuration settings for Driver_USBH1 in component ::CMSIS Driver:USB Host +#define RTE_USB_OTG_HS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_VBUS_PIN 1 +#define RTE_OTG_HS_VBUS_ACTIVE 0 +#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_HS_VBUS_BIT 2 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_OC_PIN 0 +#define RTE_OTG_HS_OC_ACTIVE 0 +#define RTE_OTG_HS_OC_PORT GPIO_PORT(2) +#define RTE_OTG_HS_OC_BIT 5 +// + +// DMA +// Use dedicated DMA for transfers +// If DMA is used all USB transfer data buffers have to be 4-byte aligned. +#define RTE_OTG_HS_DMA 0 + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/ac6_linker_script.sct.src b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/ac6_linker_script.sct.src new file mode 100644 index 0000000..e0318c9 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/ac6_linker_script.sct.src @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Stack and Heap are configured in startup file */ +#define __STACK_SIZE 0 +#define __HEAP_SIZE 0 + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + +#if __STACK_SIZE > 0 + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +#endif + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/regions_STM32F429I-Discovery.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/regions_STM32F429I-Discovery.h new file mode 100644 index 0000000..67eafdd --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/regions_STM32F429I-Discovery.h @@ -0,0 +1,98 @@ +#ifndef REGIONS_STM32F429I_DISCOVERY_H +#define REGIONS_STM32F429I_DISCOVERY_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Auto-generated using information from packs +// Device Family Pack (DFP): Keil::STM32F4xx_DFP@2.16.0 +// Board Support Pack (BSP): Keil::STM32F4xx_DFP@2.16.0 + +// ROM Configuration +// ======================= +// __ROM0 (is rx memory: IROM1 from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x08000000 +// Contains Startup and Vector Table +#define __ROM0_BASE 0x08000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00200000 +#define __ROM0_SIZE 0x00200000 +// + +// __ROM1 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __ROM1_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM1_SIZE 0x0 +// + +// __ROM2 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __ROM2_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM2_SIZE 0x0 +// + +// __ROM3 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __ROM3_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM3_SIZE 0x0 +// + +// + +// RAM Configuration +// ======================= +// __RAM0 (is rwx memory: IRAM1 from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x20000000 +// Contains uninitialized RAM, Stack, and Heap +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00030000 +#define __RAM0_SIZE 0x00030000 +// + +// __RAM1 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __RAM1_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __RAM1_SIZE 0x0 +// + +// __RAM2 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __RAM2_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __RAM2_SIZE 0x0 +// + +// __RAM3 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __RAM3_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __RAM3_SIZE 0x0 +// + +// + +// Resources that are not allocated to linker regions +// rwx RAM: IRAM2 from DFP: BASE: 0x10000000 SIZE: 0x00010000 + + +#endif /* REGIONS_STM32F429I_DISCOVERY_H */ diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s similarity index 100% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/startup_stm32f407xx.s b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s.base@2.6.2 similarity index 92% rename from Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/startup_stm32f407xx.s rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s.base@2.6.2 index da25df5..d3a0a94 100644 --- a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/startup_stm32f407xx.s +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s.base@2.6.2 @@ -1,7 +1,7 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32f407xx.s +;******************************************************************************* +;* File Name : startup_stm32f429xx.s ;* Author : MCD Application Team -;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. +;* Description : STM32F429x devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler @@ -10,40 +10,27 @@ ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. +;******************************************************************************** +;* @attention +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause ;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000800 +Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size @@ -54,7 +41,7 @@ __initial_sp ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00002800 +Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base @@ -168,10 +155,18 @@ __Vectors DCD __initial_sp ; Top of Stack DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD 0 ; Reserved DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU - + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D __Vectors_End @@ -318,7 +313,16 @@ Default_Handler PROC EXPORT DCMI_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] - + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler @@ -400,7 +404,15 @@ OTG_HS_IRQHandler DCMI_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler - +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler B . ENDP diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h similarity index 99% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h index 195d544..46ac6d3 100644 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration file - * - * @note modified by ARM - * The modifications allow to use this file as User Code Template - * within the Device Family Pack. + * @brief HAL configuration file + * + * @note modified by ARM + * The modifications allow to use this file as User Code Template + * within the Device Family Pack. ****************************************************************************** * @attention * @@ -25,10 +25,10 @@ #ifndef __STM32F4xx_HAL_CONF_H #define __STM32F4xx_HAL_CONF_H -#ifdef _RTE_ -#include "RTE_Components.h" /* Component selection */ -#endif - +#ifdef _RTE_ +#include "RTE_Components.h" /* Component selection */ +#endif + #ifdef __cplusplus extern "C" { #endif @@ -40,151 +40,151 @@ /** * @brief This is the list of modules to be used in the HAL driver */ -#ifdef RTE_DEVICE_HAL_COMMON -#define HAL_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_ADC -#define HAL_ADC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CAN +#ifdef RTE_DEVICE_HAL_COMMON +#define HAL_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_ADC +#define HAL_ADC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CAN #define HAL_CAN_MODULE_ENABLED -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -#endif -#ifdef RTE_DEVICE_HAL_CRC -#define HAL_CRC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CEC +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +#endif +#ifdef RTE_DEVICE_HAL_CRC +#define HAL_CRC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CEC #define HAL_CEC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CRYP -#define HAL_CRYP_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DAC -#define HAL_DAC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DCMI -#define HAL_DCMI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DMA +#endif +#ifdef RTE_DEVICE_HAL_CRYP +#define HAL_CRYP_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DAC +#define HAL_DAC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DCMI +#define HAL_DCMI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DMA #define HAL_DMA_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DMA2D -#define HAL_DMA2D_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_ETH -#define HAL_ETH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_EXTI +#endif +#ifdef RTE_DEVICE_HAL_DMA2D +#define HAL_DMA2D_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_ETH +#define HAL_ETH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_EXTI #define HAL_EXTI_MODULE_ENABLED -#endif -#if defined (RTE_DEVICE_HAL_FLASH) || defined (RTE_DEVICE_HAL_COMMON) -#define HAL_FLASH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_NAND +#endif +#if defined (RTE_DEVICE_HAL_FLASH) || defined (RTE_DEVICE_HAL_COMMON) +#define HAL_FLASH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_NAND #define HAL_NAND_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_NOR +#endif +#ifdef RTE_DEVICE_HAL_NOR #define HAL_NOR_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PCCARD +#endif +#ifdef RTE_DEVICE_HAL_PCCARD #define HAL_PCCARD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SRAM +#endif +#ifdef RTE_DEVICE_HAL_SRAM #define HAL_SRAM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SDRAM +#endif +#ifdef RTE_DEVICE_HAL_SDRAM #define HAL_SDRAM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_HASH -#define HAL_HASH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_GPIO +#endif +#ifdef RTE_DEVICE_HAL_HASH +#define HAL_HASH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_GPIO #define HAL_GPIO_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_I2C +#endif +#ifdef RTE_DEVICE_HAL_I2C #define HAL_I2C_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SMBUS -#define HAL_SMBUS_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_I2S -#define HAL_I2S_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_IWDG -#define HAL_IWDG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_LTDC -#define HAL_LTDC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DSI +#endif +#ifdef RTE_DEVICE_HAL_SMBUS +#define HAL_SMBUS_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_I2S +#define HAL_I2S_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_IWDG +#define HAL_IWDG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_LTDC +#define HAL_LTDC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DSI #define HAL_DSI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PWR +#endif +#ifdef RTE_DEVICE_HAL_PWR #define HAL_PWR_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_QSPI -#define HAL_QSPI_MODULE_ENABLED -#endif -#if defined (RTE_DEVICE_HAL_RCC) || defined (RTE_DEVICE_HAL_COMMON) -#define HAL_RCC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_RNG -#define HAL_RNG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_RTC +#endif +#ifdef RTE_DEVICE_HAL_QSPI +#define HAL_QSPI_MODULE_ENABLED +#endif +#if defined (RTE_DEVICE_HAL_RCC) || defined (RTE_DEVICE_HAL_COMMON) +#define HAL_RCC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_RNG +#define HAL_RNG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_RTC #define HAL_RTC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SAI -#define HAL_SAI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SD -#define HAL_SD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SPI -#define HAL_SPI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_TIM -#define HAL_TIM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_UART -#define HAL_UART_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_USART -#define HAL_USART_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_IRDA -#define HAL_IRDA_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SMARTCARD -#define HAL_SMARTCARD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_WWDG -#define HAL_WWDG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CORTEX +#endif +#ifdef RTE_DEVICE_HAL_SAI +#define HAL_SAI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SD +#define HAL_SD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SPI +#define HAL_SPI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_TIM +#define HAL_TIM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_UART +#define HAL_UART_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_USART +#define HAL_USART_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_IRDA +#define HAL_IRDA_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SMARTCARD +#define HAL_SMARTCARD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_WWDG +#define HAL_WWDG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CORTEX #define HAL_CORTEX_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PCD +#endif +#ifdef RTE_DEVICE_HAL_PCD #define HAL_PCD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_HCD +#endif +#ifdef RTE_DEVICE_HAL_HCD #define HAL_HCD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_FMPI2C +#endif +#ifdef RTE_DEVICE_HAL_FMPI2C #define HAL_FMPI2C_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SPDIFRX +#endif +#ifdef RTE_DEVICE_HAL_SPDIFRX #define HAL_SPDIFRX_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DFSDM -#define HAL_DFSDM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_LPTIM -#define HAL_LPTIM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_MMC -#define HAL_MMC_MODULE_ENABLED -#endif +#endif +#ifdef RTE_DEVICE_HAL_DFSDM +#define HAL_DFSDM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_LPTIM +#define HAL_LPTIM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_MMC +#define HAL_MMC_MODULE_ENABLED +#endif /* ########################## HSE/HSI Values adaptation ##################### */ @@ -247,10 +247,10 @@ */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U +#define USE_RTOS 0U #define PREFETCH_ENABLE 0U /* The prefetch will be enabled in SystemClock_Config(), depending on the used - STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */ -#define INSTRUCTION_CACHE_ENABLE 1U + STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */ +#define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ @@ -362,8 +362,8 @@ #define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ #define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ /* ################## SPI peripheral configuration ########################## */ @@ -416,7 +416,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -438,7 +438,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -453,11 +453,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -467,10 +467,10 @@ #include "stm32f4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + #ifdef HAL_I2S_MODULE_ENABLED #include "stm32f4xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ @@ -538,7 +538,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -558,19 +558,19 @@ #ifdef HAL_SPDIFRX_MODULE_ENABLED #include "stm32f4xx_hal_spdifrx.h" #endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/stm32f4xx_hal_conf.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h.base@1.7.13 similarity index 99% rename from Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/stm32f4xx_hal_conf.h rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h.base@1.7.13 index 64f4258..31af5bd 100644 --- a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/stm32f4xx_hal_conf.h +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/stm32f4xx_hal_conf.h.base@1.7.13 @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration file - * - * @note modified by ARM - * The modifications allow to use this file as User Code Template - * within the Device Family Pack. + * @brief HAL configuration file + * + * @note modified by ARM + * The modifications allow to use this file as User Code Template + * within the Device Family Pack. ****************************************************************************** * @attention * @@ -19,16 +19,16 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H #define __STM32F4xx_HAL_CONF_H -#ifdef _RTE_ -#include "RTE_Components.h" /* Component selection */ -#endif - +#ifdef _RTE_ +#include "RTE_Components.h" /* Component selection */ +#endif + #ifdef __cplusplus extern "C" { #endif @@ -40,151 +40,151 @@ /** * @brief This is the list of modules to be used in the HAL driver */ -#ifdef RTE_DEVICE_HAL_COMMON -#define HAL_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_ADC -#define HAL_ADC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CAN +#ifdef RTE_DEVICE_HAL_COMMON +#define HAL_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_ADC +#define HAL_ADC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CAN #define HAL_CAN_MODULE_ENABLED -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -#endif -#ifdef RTE_DEVICE_HAL_CRC -#define HAL_CRC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CEC +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +#endif +#ifdef RTE_DEVICE_HAL_CRC +#define HAL_CRC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CEC #define HAL_CEC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CRYP -#define HAL_CRYP_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DAC -#define HAL_DAC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DCMI -#define HAL_DCMI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DMA +#endif +#ifdef RTE_DEVICE_HAL_CRYP +#define HAL_CRYP_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DAC +#define HAL_DAC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DCMI +#define HAL_DCMI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DMA #define HAL_DMA_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DMA2D -#define HAL_DMA2D_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_ETH -#define HAL_ETH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_EXTI +#endif +#ifdef RTE_DEVICE_HAL_DMA2D +#define HAL_DMA2D_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_ETH +#define HAL_ETH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_EXTI #define HAL_EXTI_MODULE_ENABLED -#endif -#if defined (RTE_DEVICE_HAL_FLASH) || defined (RTE_DEVICE_HAL_COMMON) -#define HAL_FLASH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_NAND +#endif +#if defined (RTE_DEVICE_HAL_FLASH) || defined (RTE_DEVICE_HAL_COMMON) +#define HAL_FLASH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_NAND #define HAL_NAND_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_NOR +#endif +#ifdef RTE_DEVICE_HAL_NOR #define HAL_NOR_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PCCARD +#endif +#ifdef RTE_DEVICE_HAL_PCCARD #define HAL_PCCARD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SRAM +#endif +#ifdef RTE_DEVICE_HAL_SRAM #define HAL_SRAM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SDRAM +#endif +#ifdef RTE_DEVICE_HAL_SDRAM #define HAL_SDRAM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_HASH -#define HAL_HASH_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_GPIO +#endif +#ifdef RTE_DEVICE_HAL_HASH +#define HAL_HASH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_GPIO #define HAL_GPIO_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_I2C +#endif +#ifdef RTE_DEVICE_HAL_I2C #define HAL_I2C_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SMBUS -#define HAL_SMBUS_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_I2S -#define HAL_I2S_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_IWDG -#define HAL_IWDG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_LTDC -#define HAL_LTDC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DSI +#endif +#ifdef RTE_DEVICE_HAL_SMBUS +#define HAL_SMBUS_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_I2S +#define HAL_I2S_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_IWDG +#define HAL_IWDG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_LTDC +#define HAL_LTDC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DSI #define HAL_DSI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PWR +#endif +#ifdef RTE_DEVICE_HAL_PWR #define HAL_PWR_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_QSPI -#define HAL_QSPI_MODULE_ENABLED -#endif -#if defined (RTE_DEVICE_HAL_RCC) || defined (RTE_DEVICE_HAL_COMMON) -#define HAL_RCC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_RNG -#define HAL_RNG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_RTC +#endif +#ifdef RTE_DEVICE_HAL_QSPI +#define HAL_QSPI_MODULE_ENABLED +#endif +#if defined (RTE_DEVICE_HAL_RCC) || defined (RTE_DEVICE_HAL_COMMON) +#define HAL_RCC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_RNG +#define HAL_RNG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_RTC #define HAL_RTC_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SAI -#define HAL_SAI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SD -#define HAL_SD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SPI -#define HAL_SPI_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_TIM -#define HAL_TIM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_UART -#define HAL_UART_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_USART -#define HAL_USART_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_IRDA -#define HAL_IRDA_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SMARTCARD -#define HAL_SMARTCARD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_WWDG -#define HAL_WWDG_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_CORTEX +#endif +#ifdef RTE_DEVICE_HAL_SAI +#define HAL_SAI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SD +#define HAL_SD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SPI +#define HAL_SPI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_TIM +#define HAL_TIM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_UART +#define HAL_UART_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_USART +#define HAL_USART_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_IRDA +#define HAL_IRDA_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SMARTCARD +#define HAL_SMARTCARD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_WWDG +#define HAL_WWDG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CORTEX #define HAL_CORTEX_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_PCD +#endif +#ifdef RTE_DEVICE_HAL_PCD #define HAL_PCD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_HCD +#endif +#ifdef RTE_DEVICE_HAL_HCD #define HAL_HCD_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_FMPI2C +#endif +#ifdef RTE_DEVICE_HAL_FMPI2C #define HAL_FMPI2C_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_SPDIFRX +#endif +#ifdef RTE_DEVICE_HAL_SPDIFRX #define HAL_SPDIFRX_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_DFSDM -#define HAL_DFSDM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_LPTIM -#define HAL_LPTIM_MODULE_ENABLED -#endif -#ifdef RTE_DEVICE_HAL_MMC -#define HAL_MMC_MODULE_ENABLED -#endif +#endif +#ifdef RTE_DEVICE_HAL_DFSDM +#define HAL_DFSDM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_LPTIM +#define HAL_LPTIM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_MMC +#define HAL_MMC_MODULE_ENABLED +#endif /* ########################## HSE/HSI Values adaptation ##################### */ @@ -247,10 +247,10 @@ */ #define VDD_VALUE (3300U) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U /* The prefetch will be enabled in SystemClock_Config(), depending on the used - STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */ -#define INSTRUCTION_CACHE_ENABLE 1U +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U /* The prefetch will be enabled in SystemClock_Config(), depending on the used + STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */ +#define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ @@ -362,8 +362,8 @@ #define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ #define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ /* ################## SPI peripheral configuration ########################## */ @@ -416,7 +416,7 @@ #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -438,7 +438,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -453,11 +453,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -467,10 +467,10 @@ #include "stm32f4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + #ifdef HAL_I2S_MODULE_ENABLED #include "stm32f4xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ @@ -538,7 +538,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -558,19 +558,19 @@ #ifdef HAL_SPDIFRX_MODULE_ENABLED #include "stm32f4xx_hal_spdifrx.h" #endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/system_stm32f4xx.c b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/system_stm32f4xx.c similarity index 100% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/system_stm32f4xx.c rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/system_stm32f4xx.c diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/system_stm32f4xx.c b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/system_stm32f4xx.c.base@2.6.3 similarity index 100% rename from Tools/SPI_Server/Board/MCBSTM32F400/RTE/Device/STM32F407IGHx/system_stm32f4xx.c rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/RTE/Device/STM32F429ZITx/system_stm32f4xx.c.base@2.6.3 diff --git a/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/STM32F429I-DISC1.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/STM32F429I-DISC1.h new file mode 100644 index 0000000..0cef802 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/STM32F429I-DISC1.h @@ -0,0 +1,42 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#ifndef STM32F429I_DISC1_H_ +#define STM32F429I_DISC1_H_ + +#include "Driver_SPI.h" +#include "Driver_USART.h" + +// CMSIS Driver instances of Board peripherals +#define CMSIS_DRIVER_SPI 1 // Driver_SPI1 +#define CMSIS_DRIVER_USART 1 // Driver_USART1 + +// CMSIS Driver instance for STDIO retarget +#define RETARGET_STDIO_UART 2 + +// CMSIS Drivers +extern ARM_DRIVER_SPI ARM_Driver_SPI_(CMSIS_DRIVER_SPI); // SPI1 +extern ARM_DRIVER_USART ARM_Driver_USART_(CMSIS_DRIVER_USART); // USART1 +extern ARM_DRIVER_USART ARM_Driver_USART_(RETARGET_STDIO_UART); // STDIO retargeted USART2 + +#ifdef CMSIS_shield_header +#include CMSIS_shield_header +#endif + +#endif // STM32F429I_DISC1_H_ diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/main.c b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/main.c similarity index 94% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/main.c rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/main.c index c534139..92b14ab 100644 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/main.c +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/main.c @@ -36,11 +36,14 @@ #include #include -#include "SPI_Server_Config.h" -#include "SPI_Server.h" +#include "app_main.h" #include "stm32f4xx_hal.h" +#include "cmsis_vio.h" + +extern int stdio_init (void); + // Private function prototypes static void Error_Handler(void); static void SystemClock_Config(void); @@ -56,12 +59,13 @@ int32_t main (void) { SystemClock_Config(); SystemCoreClockUpdate(); - // Initialize kernel, create threads and start kernel - (void)osKernelInitialize(); - (void)SPI_Server_Start(); - (void)osKernelStart(); + stdio_init(); /* Initialize STDIO */ + + vioInit(); /* Initialize Virtual I/O */ + + app_main(); /* Execute Application main */ - for (;;) {} + return 0; } diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/main.h b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/main.h similarity index 100% rename from Tools/SPI_Server/Board/MCBSTM32F400/main.h rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/main.h diff --git a/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/retarget_stdio.c b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/retarget_stdio.c new file mode 100644 index 0000000..5e15595 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/retarget_stdio.c @@ -0,0 +1,139 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2024 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: retarget_stdio.c + * Purpose: Retarget stdio to CMSIS UART + * + *---------------------------------------------------------------------------*/ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#include "Driver_USART.h" +#endif + +#ifndef RETARGET_STDIO_UART +#error "RETARGET_STDIO_UART not defined!" +#endif + +// Compile-time configuration +#define UART_BAUDRATE 115200 + +// Exported functions +extern int stdio_init (void); +extern int stderr_putchar (int ch); +extern int stdout_putchar (int ch); +extern int stdin_getchar (void); + +#ifndef CMSIS_target_header +extern ARM_DRIVER_USART ARM_Driver_USART_(RETARGET_STDIO_UART); +#endif + +#define ptrUSART (&ARM_Driver_USART_(RETARGET_STDIO_UART)) + +/** + Initialize stdio + + \return 0 on success, or -1 on error. +*/ +int stdio_init (void) { + + if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_DATA_BITS_8 | + ARM_USART_PARITY_NONE | + ARM_USART_STOP_BITS_1 | + ARM_USART_FLOW_CONTROL_NONE, + UART_BAUDRATE) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { + return -1; + } + + if (ptrUSART->Control(ARM_USART_CONTROL_TX, 1U) != ARM_DRIVER_OK) { + return -1; + } + + return 0; +} + +/** + Put a character to the stderr + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stderr_putchar (int ch) { + uint8_t buf[1]; + + buf[0] = (uint8_t)ch; + + if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { + return -1; + } + + while (ptrUSART->GetStatus().tx_busy != 0U); + + return ch; +} + +/** + Put a character to the stdout + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stdout_putchar (int ch) { + uint8_t buf[1]; + + buf[0] = (uint8_t)ch; + + if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { + return -1; + } + + while (ptrUSART->GetStatus().tx_busy != 0U); + + return ch; +} + +/** + Get a character from the stdio + + \return The next character from the input, or -1 on read error. +*/ +int stdin_getchar (void) { + uint8_t buf[1]; + + if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { + return -1; + } + + while (ptrUSART->GetStatus().rx_busy != 0U); + + return (int)buf[0]; +} diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/vio_STM32F429I.c b/Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/vio_STM32F429I.c similarity index 100% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/vio_STM32F429I.c rename to Tools/SPI_Server/STM32F429I-DISC1/Board/STM32F429I-DISC1/vio_STM32F429I.c diff --git a/Tools/SPI_Server/Config/SPI_Server_Config.h b/Tools/SPI_Server/STM32F429I-DISC1/Config/SPI_Server_Config.h similarity index 90% rename from Tools/SPI_Server/Config/SPI_Server_Config.h rename to Tools/SPI_Server/STM32F429I-DISC1/Config/SPI_Server_Config.h index b1ae479..5e51b11 100644 --- a/Tools/SPI_Server/Config/SPI_Server_Config.h +++ b/Tools/SPI_Server/STM32F429I-DISC1/Config/SPI_Server_Config.h @@ -26,6 +26,12 @@ #ifndef SPI_SERVER_CONFIG_H_ #define SPI_SERVER_CONFIG_H_ +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define ARDUINO_UNO_SPI 0 +#endif + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- //------ With VS Code: Open Preview for Configuration Wizard ------------------- @@ -36,12 +42,12 @@ // Clock / Frame Format: Clock Polarity 0, Clock Phase 0 // Data Bits: 8 // Bit Order: MSB to LSB -// Driver_SPI# <0-255> +// Driver_SPI# // Choose the Driver_SPI# instance. // For example to use Driver_SPI0 select 0. // -#define SPI_SERVER_DRV_NUM 0 +#define SPI_SERVER_DRV_NUM 1 #define SPI_SERVER_BUF_SIZE 4096 #define SPI_SERVER_CMD_TIMEOUT 100 diff --git a/Tools/SPI_Server/Include/SPI_Server.h b/Tools/SPI_Server/STM32F429I-DISC1/Include/SPI_Server.h similarity index 100% rename from Tools/SPI_Server/Include/SPI_Server.h rename to Tools/SPI_Server/STM32F429I-DISC1/Include/SPI_Server.h diff --git a/Tools/SPI_Server/STM32F429I-DISC1/README.md b/Tools/SPI_Server/STM32F429I-DISC1/README.md new file mode 100644 index 0000000..247814c --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/README.md @@ -0,0 +1,133 @@ +# SPI Server Application for STM32F429I-DISC1 + +This application serves as an **SPI Server** running on the STMicroelectronics **STM32F429I-DISC1 (32F429IDISCOVERY)** development board. +It provides a physical test environment for validating SPI driver compliance to the **CMSIS SPI driver specification v2.0.0 and above**. + +--- + +## Overview + +The SPI Server operates in **Slave mode**, awaiting commands over the SPI interface from an external SPI Client (Driver Validation). +Upon receiving a command, it executes the corresponding operation and returns to the waiting state. +Commands may either execute to completion or terminate upon timeout. + +All commands (except `XFER`) utilize a fixed SPI configuration and timeout as defined in the **`SPI_Server_Config.h`** file. +The `XFER` command temporarily applies custom SPI settings defined by the most recent `SET COM` command. + +--- + +## Default SPI Configuration + +| Parameter | Value +|-------------|------ +| Mode | Slave (hardware-monitored Slave Select) +| Clock/Frame | Polarity 0, Phase 0 +| Data Bits | 8 +| Bit Order | MSB first + +--- + +## Hardware Connections + +Peripheral used: **SPI1** + +| Function | Pin | Description +|----------|------|------------ +| SCLK | PA5 | SPI clock +| MOSI | PA7 | Master Out, Slave In +| MISO | PB4 | Master In, Slave Out +| SS | PA15 | Requires external pull-up to Vcc (3.3V) +| GND | GND | Any board ground + +--- + +## Command Protocol + +Each command is **32 bytes long**, padded with zeros if shorter. Optional parameters are enclosed in `[]`. + +### Supported Commands + +| Command (32 bytes zero padded) | Data Phase Direction | Description +|-----------------------------------------------------------|----------------------|------------ +| `GET VER` | OUT (16 bytes) | Returns firmware version in `major.minor.patch` format. +| `GET CAP` | OUT (32 bytes) | Returns supported mode/format/bit masks and speed limits. +| `SET BUF RX/TX,len[,pattern]` | IN (`1en` bytes) | Sets RX/TX buffer; optionally pre-fills with pattern. +| `GET BUF RX/TX,len` | OUT (`len` bytes) | Reads `len` bytes from RX/TX buffer. +| `SET COM mode,format,bit_num,bit_order,ss_mode,bus_speed` | | Sets custom SPI communication parameters for next `XFER`. +| `XFER num[,delay_c][,delay_t][,timeout]` | IN/OUT (`num` items) | Performs full-duplex SPI data transfer. +| `GET CNT` | OUT (16 bytes) | Returns count in decimal notation. + +## Command Parameters + +| Parameter | Description +|-------------|------------ +| `RX/TX` | RX = SPI Server receive buffer, TX = SPI Server transmit buffer +| `len` | Data length for data phase +| `pattern` | Hex value used to pre-fill buffer +| `mode` | 0 = Master, 1 = Slave +| `format` | 0 = Clock Polarity 0, Clock Phase 0 +| | 1 = Clock Polarity 0, Clock Phase 1 +| | 2 = Clock Polarity 1, Clock Phase 0 +| | 3 = Clock Polarity 1, Clock Phase 1 +| | 4 = Texas Instruments Frame Format +| | 5 = National Semiconductor Microwire Frame Format +| `bit_num` | Bits per frame (132) +| `bit_order` | 0 = MSB first, 1 = LSB first +| `ss_mode` | 0 = unused, 1 = Master-driven/Slave-monitored +| `bus_speed` | SPI clock rate (bps) +| `num` | Number of items (according CMSIS SPI driver specification) +| `delay_c` | Delay before Control function is called (ms) +| `delay_t` | Delay after Control function is called but before Transfer function is called (ms) +| `timeout` | Total transfer timeout including delay_c and delay_t delays, including delay_c and delay_t (ms) + +## Response Formats + +| Command | Response +|-------------|--------- +| `GET VER` | 16 bytes, "major.minor.patch" +| `GET CAP` | 32 bytes, "mode_mask,format_mask,data_bit_mask,bit_order_mask,min_bus_speed_in_kbps,max_bus_speed_in_kbps" +| | mode_mask (2 digits hex): specifies mask of supported modes +| | - bit 0.: Master +| | - bit 1.: Slave +| | format_mask (2 digits hex): specifies mask of supported clock/frame formats +| | - bit 0.: Clock Polarity 0, Clock Phase 0 +| | - bit 1.: Clock Polarity 0, Clock Phase 1 +| | - bit 2.: Clock Polarity 1, Clock Phase 0 +| | - bit 3.: Clock Polarity 1, Clock Phase 1 +| | - bit 4.: Texas Instruments Frame Format +| | - bit 5.: National Semiconductor Microwire Frame Format +| | data_bit_mask (8 digits hex): specifies mask of supported data bits +| | - bit 0.: Data Bits 1 +| | ... +| | - bit 31.: Data Bits 32 +| | bit_order_mask (2 digits hex): specifies mask of supported bit orders +| | - bit 0.: MSB first +| | - bit 1.: LSB first +| | min_bus_speed_in_kbps (dec): minimum supported bus speed (in kbps) +| | max_bus_speed_in_kbps (dec): maximum supported bus speed (in kbps) +| `GET BUF` | `len` bytes from respective buffer +| `GET CNT` | 16 bytes (dec) + +--- + +## Communication Example + +```text +-> GET VER <- "1.1.0" +-> GET CAP <- "03,1F,00008080,03,1000,10000" +-> SET BUF TX,0,53 (Fill TX with 'S') +-> SET BUF RX,0,3F (Fill RX with '?') +-> GET BUF RX,16 <- "????????????????" +-> SET COM 1,0,8,0,1,2000000 (Slave mode, CPOL=0, CPHA=0, 8-bit, MSB, 2 Mbps) +-> XFER 16,10,0,100 <-> 16-byte transfer +-> GET CNT <- "16" +``` + +--- + +## Build Targets + +| Target | Description +|-------------|------------ +| **Debug** | Low optimization build with GLCD interface (for debugging). +| **Release** | Optimized binary without UI (for production testing). diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.c b/Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.c similarity index 100% rename from Tools/SPI_Server/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.c rename to Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.c diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.c b/Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.c.base@5.1.1 similarity index 100% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.c rename to Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.c.base@5.1.1 diff --git a/Tools/SPI_Server/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.h b/Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h similarity index 100% rename from Tools/SPI_Server/Board/MCBSTM32F400/RTE/CMSIS/RTX_Config.h rename to Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h diff --git a/Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h.base@5.5.2 b/Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h.base@5.5.2 new file mode 100644 index 0000000..4d2f501 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h.base@5.5.2 @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Debug_STM32F429ZITx/Pre_Include_Global.h b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Debug_STM32F429ZITx/Pre_Include_Global.h new file mode 100644 index 0000000..3b2d5f8 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Debug_STM32F429ZITx/Pre_Include_Global.h @@ -0,0 +1,16 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.11.0 + * + * Project: 'SPI_Server.Debug+STM32F429ZITx' + * Target: 'Debug+STM32F429ZITx' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common@1.7.13 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Debug_STM32F429ZITx/RTE_Components.h b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Debug_STM32F429ZITx/RTE_Components.h new file mode 100644 index 0000000..8548f63 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Debug_STM32F429ZITx/RTE_Components.h @@ -0,0 +1,81 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.11.0 + * + * Project: 'SPI_Server.Debug+STM32F429ZITx' + * Target: 'Debug+STM32F429ZITx' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f4xx.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ +#define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ +#define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ +#define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ +#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ +#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:SPI@2.16 */ +#define RTE_Drivers_SPI1 /* Driver SPI1 */ +#define RTE_Drivers_SPI2 /* Driver SPI2 */ +#define RTE_Drivers_SPI3 /* Driver SPI3 */ +#define RTE_Drivers_SPI4 /* Driver SPI4 */ +#define RTE_Drivers_SPI5 /* Driver SPI5 */ +#define RTE_Drivers_SPI6 /* Driver SPI6 */ +/* Keil::CMSIS Driver:USART@2.14 */ +#define RTE_Drivers_USART1 /* Driver USART1 */ +#define RTE_Drivers_USART2 /* Driver USART2 */ +#define RTE_Drivers_USART3 /* Driver USART3 */ +#define RTE_Drivers_USART4 /* Driver USART4 */ +#define RTE_Drivers_USART5 /* Driver USART5 */ +#define RTE_Drivers_USART6 /* Driver USART6 */ +#define RTE_Drivers_USART7 /* Driver USART7 */ +#define RTE_Drivers_USART8 /* Driver USART8 */ +#define RTE_Drivers_USART9 /* Driver USART9 */ +#define RTE_Drivers_USART10 /* Driver USART10 */ +/* Keil::Device:STM32Cube Framework:Classic@1.7.13 */ +#define RTE_DEVICE_FRAMEWORK_CLASSIC +/* Keil::Device:STM32Cube HAL:Common@1.7.13 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex@1.7.13 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA2D@1.7.13 */ +#define RTE_DEVICE_HAL_DMA2D +/* Keil::Device:STM32Cube HAL:DMA@1.7.13 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:GPIO@1.7.13 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:I2C@1.7.13 */ +#define RTE_DEVICE_HAL_I2C +/* Keil::Device:STM32Cube HAL:LTDC@1.7.13 */ +#define RTE_DEVICE_HAL_LTDC +/* Keil::Device:STM32Cube HAL:PWR@1.7.13 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC@1.7.13 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:SDRAM@1.7.13 */ +#define RTE_DEVICE_HAL_SDRAM +/* Keil::Device:STM32Cube HAL:SPI@1.7.13 */ +#define RTE_DEVICE_HAL_SPI +/* Keil::Device:STM32Cube HAL:UART@1.7.13 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:STM32Cube HAL:USART@1.7.13 */ +#define RTE_DEVICE_HAL_USART +/* Keil::Device:Startup@2.6.3 */ +#define RTE_DEVICE_STARTUP_STM32F4XX /* Device Startup for STM32F4 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Release_STM32F429ZITx/Pre_Include_Global.h b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Release_STM32F429ZITx/Pre_Include_Global.h new file mode 100644 index 0000000..dbe02ab --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Release_STM32F429ZITx/Pre_Include_Global.h @@ -0,0 +1,16 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.11.0 + * + * Project: 'SPI_Server.Release+STM32F429ZITx' + * Target: 'Release+STM32F429ZITx' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common@1.7.13 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Release_STM32F429ZITx/RTE_Components.h b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Release_STM32F429ZITx/RTE_Components.h new file mode 100644 index 0000000..294d6e7 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/RTE/_Release_STM32F429ZITx/RTE_Components.h @@ -0,0 +1,81 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.11.0 + * + * Project: 'SPI_Server.Release+STM32F429ZITx' + * Target: 'Release+STM32F429ZITx' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f4xx.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ +#define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ +#define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ +#define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.5.4 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ +#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ +#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:SPI@2.16 */ +#define RTE_Drivers_SPI1 /* Driver SPI1 */ +#define RTE_Drivers_SPI2 /* Driver SPI2 */ +#define RTE_Drivers_SPI3 /* Driver SPI3 */ +#define RTE_Drivers_SPI4 /* Driver SPI4 */ +#define RTE_Drivers_SPI5 /* Driver SPI5 */ +#define RTE_Drivers_SPI6 /* Driver SPI6 */ +/* Keil::CMSIS Driver:USART@2.14 */ +#define RTE_Drivers_USART1 /* Driver USART1 */ +#define RTE_Drivers_USART2 /* Driver USART2 */ +#define RTE_Drivers_USART3 /* Driver USART3 */ +#define RTE_Drivers_USART4 /* Driver USART4 */ +#define RTE_Drivers_USART5 /* Driver USART5 */ +#define RTE_Drivers_USART6 /* Driver USART6 */ +#define RTE_Drivers_USART7 /* Driver USART7 */ +#define RTE_Drivers_USART8 /* Driver USART8 */ +#define RTE_Drivers_USART9 /* Driver USART9 */ +#define RTE_Drivers_USART10 /* Driver USART10 */ +/* Keil::Device:STM32Cube Framework:Classic@1.7.13 */ +#define RTE_DEVICE_FRAMEWORK_CLASSIC +/* Keil::Device:STM32Cube HAL:Common@1.7.13 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex@1.7.13 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA2D@1.7.13 */ +#define RTE_DEVICE_HAL_DMA2D +/* Keil::Device:STM32Cube HAL:DMA@1.7.13 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:GPIO@1.7.13 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:I2C@1.7.13 */ +#define RTE_DEVICE_HAL_I2C +/* Keil::Device:STM32Cube HAL:LTDC@1.7.13 */ +#define RTE_DEVICE_HAL_LTDC +/* Keil::Device:STM32Cube HAL:PWR@1.7.13 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC@1.7.13 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:SDRAM@1.7.13 */ +#define RTE_DEVICE_HAL_SDRAM +/* Keil::Device:STM32Cube HAL:SPI@1.7.13 */ +#define RTE_DEVICE_HAL_SPI +/* Keil::Device:STM32Cube HAL:UART@1.7.13 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:STM32Cube HAL:USART@1.7.13 */ +#define RTE_DEVICE_HAL_USART +/* Keil::Device:Startup@2.6.3 */ +#define RTE_DEVICE_STARTUP_STM32F4XX /* Device Startup for STM32F4 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Tools/SPI_Server/STM32F429I-DISC1/SPI_Server.cproject.yml b/Tools/SPI_Server/STM32F429I-DISC1/SPI_Server.cproject.yml new file mode 100644 index 0000000..1ddec91 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/SPI_Server.cproject.yml @@ -0,0 +1,49 @@ +project: + description: CMSIS Driver Validation SPI Server for STM32F429I-DISC1 board + + # List of packs used in the project. + packs: + - pack: ARM::CMSIS@5.9.0 + + # List of connections required or provided by the project. + connections: + - connect: SPI Server + provides: + - CMSIS-RTOS2 + consumes: + - CMSIS_VIO + - STDOUT + + # List of include paths passed via the command line to the build tool + add-path: + - ./ + + # List of source groups and files. + groups: + - group: Documentation + files: + - file: README.md + - group: Source Files + files: + - file: app_main.c + - group: SPI Server Files + files: + - file: Config/SPI_Server_Config.h + - file: Include/SPI_Server.h + - file: Source/SPI_Server.c + + # List of components used by the application. + components: + - component: CMSIS:RTOS2:Keil RTX5&Source + + # List of layers used by the application. + layers: + - layer: $Board-Layer$ + type: Board + + # List of executable file formats to be generated. + output: + type: + - elf + - hex + - map diff --git a/Tools/SPI_Server/STM32F429I-DISC1/SPI_Server.csolution.yml b/Tools/SPI_Server/STM32F429I-DISC1/SPI_Server.csolution.yml new file mode 100644 index 0000000..c07e5cc --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/SPI_Server.csolution.yml @@ -0,0 +1,42 @@ +solution: + description: CMSIS Driver Validation SPI Server for STM32F429I-DISC1 board + created-for: CMSIS-Toolbox@2.11.0 + cdefault: + + # List of tested compilers that can be selected + select-compiler: + - compiler: AC6 + + compiler: AC6 # select compiler for solution + + # List of miscellaneous tool-specific controls + misc: + - for-compiler: AC6 # GDB requires DWARF 5, remove when using uVision Debugger + C-CPP: + - -gdwarf-5 + ASM: + - -gdwarf-5 + + # List different hardware targets that are used to deploy the solution. + target-types: + - type: STM32F429ZITx + device: STM32F429ZITx + board: STM32F429I-Discovery:Rev.B + variables: + - Board-Layer: $SolutionDir()$/Board/STM32F429I-DISC1/Board.clayer.yml + + # List of different build configurations. + build-types: + - type: Debug + debug: on + optimize: debug + define: + - DEBUG: 1 + + - type: Release + debug: off + optimize: balanced + + # List related projects. + projects: + - project: SPI_Server.cproject.yml diff --git a/Tools/SPI_Server/Source/SPI_Server.c b/Tools/SPI_Server/STM32F429I-DISC1/Source/SPI_Server.c similarity index 99% rename from Tools/SPI_Server/Source/SPI_Server.c rename to Tools/SPI_Server/STM32F429I-DISC1/Source/SPI_Server.c index 67f21a2..11b1029 100644 --- a/Tools/SPI_Server/Source/SPI_Server.c +++ b/Tools/SPI_Server/STM32F429I-DISC1/Source/SPI_Server.c @@ -158,8 +158,9 @@ static void *ptr_spi_xfer_buf_tx_alloc = NULL; int32_t SPI_Server_Start (void) { int32_t ret; - vioInit(); - (void)vioPrint(vioLevelHeading, "SPI Server v%s", SPI_SERVER_VER); +#ifdef DEBUG + vioPrint(vioLevelHeading, "SPI Server v%s", SPI_SERVER_VER); +#endif // Initialize local variables spi_server_state = SPI_SERVER_STATE_RECEPTION; @@ -220,9 +221,11 @@ int32_t SPI_Server_Start (void) { } } +#ifdef DEBUG if (ret != EXIT_SUCCESS) { vioPrint(vioLevelError, "Server Start failed!"); } +#endif return ret; } @@ -271,9 +274,11 @@ int32_t SPI_Server_Stop (void) { ptr_spi_xfer_buf_tx_alloc = NULL; } +#ifdef DEBUG if (ret != EXIT_SUCCESS) { vioPrint(vioLevelError, "Server Stop failed! "); } +#endif return ret; } @@ -313,13 +318,17 @@ static void SPI_Server_Thread (void *argument) { break; } } +#ifdef DEBUG vioPrint(vioLevelMessage, "%.20s ", spi_cmd_buf_rx); +#endif spi_server_state = SPI_SERVER_STATE_RECEPTION; break; case SPI_SERVER_STATE_TERMINATE: // Self-terminate the thread default: // Should never happen, processed as terminate request +#ifdef DEBUG vioPrint(vioLevelError, "Server stopped! "); +#endif (void)SPI_Com_Abort(); (void)osThreadTerminate(osThreadGetId()); break; diff --git a/Tools/SPI_Server/STM32F429I-DISC1/app_main.c b/Tools/SPI_Server/STM32F429I-DISC1/app_main.c new file mode 100644 index 0000000..369d2eb --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/app_main.c @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#include "app_main.h" + +#include "cmsis_os2.h" + +#include "SPI_Server.h" + +// Main stack size must be multiple of 8 Bytes +#define APP_MAIN_STK_SZ (4096U) +static uint64_t app_main_stk[APP_MAIN_STK_SZ / 8]; +static const osThreadAttr_t app_main_attr = { + .stack_mem = &app_main_stk[0], + .stack_size = sizeof(app_main_stk) +}; + +/*--------------------------------------------------------------------------- + * Application main thread + *---------------------------------------------------------------------------*/ +void app_main_thread (void *argument) { + (void)argument; + + SPI_Server_Start(); // Start SPI Server + + osThreadExit(); +} + +/*--------------------------------------------------------------------------- + * Application main function + *---------------------------------------------------------------------------*/ +int32_t app_main (void) { + osKernelInitialize(); + osThreadNew(app_main_thread, NULL, &app_main_attr); + osKernelStart(); + return 0; +} diff --git a/Tools/SPI_Server/STM32F429I-DISC1/app_main.h b/Tools/SPI_Server/STM32F429I-DISC1/app_main.h new file mode 100644 index 0000000..c2f29b3 --- /dev/null +++ b/Tools/SPI_Server/STM32F429I-DISC1/app_main.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_MAIN_H_ +#define APP_MAIN_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +extern int32_t app_main (void); + +#ifdef __cplusplus +} +#endif + +#endif // APP_MAIN_H_ diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/Config/SPI_Server_Config.h b/Tools/SPI_Server/Template/Config/SPI_Server_Config.h similarity index 81% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/Config/SPI_Server_Config.h rename to Tools/SPI_Server/Template/Config/SPI_Server_Config.h index a20cf7c..068c0ce 100644 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/Config/SPI_Server_Config.h +++ b/Tools/SPI_Server/Template/Config/SPI_Server_Config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020-2025 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,14 @@ #ifndef SPI_SERVER_CONFIG_H_ #define SPI_SERVER_CONFIG_H_ +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define ARDUINO_UNO_SPI 0 +#endif + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- // SPI Server // SPI Server configuration. @@ -35,12 +42,12 @@ // Clock / Frame Format: Clock Polarity 0, Clock Phase 0 // Data Bits: 8 // Bit Order: MSB to LSB -// Driver_SPI# <0-255> +// Driver_SPI# // Choose the Driver_SPI# instance. // For example to use Driver_SPI0 select 0. // -#define SPI_SERVER_DRV_NUM 1 +#define SPI_SERVER_DRV_NUM ARDUINO_UNO_SPI #define SPI_SERVER_BUF_SIZE 4096 #define SPI_SERVER_CMD_TIMEOUT 100 diff --git a/Tools/SPI_Server/Template/Include/SPI_Server.h b/Tools/SPI_Server/Template/Include/SPI_Server.h new file mode 100644 index 0000000..e279a6c --- /dev/null +++ b/Tools/SPI_Server/Template/Include/SPI_Server.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: SPI Server + * Title: SPI Server header file + * + * ----------------------------------------------------------------------------- + */ + +#ifndef SPI_SERVER_H_ +#define SPI_SERVER_H_ + +#include + +#define SPI_SERVER_VER "1.1.2" + +#define SPI_SERVER_STATE_RECEPTION 0 +#define SPI_SERVER_STATE_EXECUTION 1 +#define SPI_SERVER_STATE_TERMINATE 255 + + +// Global functions +extern int32_t SPI_Server_Start (void); +extern int32_t SPI_Server_Stop (void); + +#endif diff --git a/Tools/SPI_Server/Template/README.md b/Tools/SPI_Server/Template/README.md new file mode 100644 index 0000000..b49922d --- /dev/null +++ b/Tools/SPI_Server/Template/README.md @@ -0,0 +1,135 @@ +# SPI Server Template Application + +This application serves as an **SPI Server** running on any development board with CMSIS compliant **SPI driver** and compatible **Board Layer**. +It provides a physical test environment for validating SPI driver compliance to the **CMSIS SPI driver specification v2.0.0 and above**. + +For more information about **Board Layer** check the [**Reference Applications documentation**](https://open-cmsis-pack.github.io/cmsis-toolbox/ReferenceApplications/). + +--- + +## Overview + +The SPI Server operates in **Slave mode**, awaiting commands over the SPI interface from an external SPI Client (Driver Validation). +Upon receiving a command, it executes the corresponding operation and returns to the waiting state. +Commands may either execute to completion or terminate upon timeout. + +All commands (except `XFER`) utilize a fixed SPI configuration and timeout as defined in the **`SPI_Server_Config.h`** file. +The `XFER` command temporarily applies custom SPI settings defined by the most recent `SET COM` command. + +--- + +## Default SPI Configuration + +| Parameter | Value +|-------------|------ +| Mode | Slave (hardware-monitored Slave Select) +| Clock/Frame | Polarity 0, Phase 0 +| Data Bits | 8 +| Bit Order | MSB first + +--- + +## Hardware Connections + +Insure that proper **Driver_SPI#** is selected in the **`SPI_Server_Config.h`** file with define `SPI_SERVER_DRV_NUM`. + +> **Note:** By default, if defined by the board layer, the `ARDUINO_UNO_SPI` will be used as selected **Driver_SPI#**. + +Respective pins depend on the selected board, check the board description for pins used for the SPI interface. + +> **Note:** Also ground pin must be connected to the DUT. + +> **Note:** If the SPI driver is not fully CMSIS compliant then SPI Server most likely will not work properly and reliably. + +--- + +## Command Protocol + +Each command is **32 bytes long**, padded with zeros if shorter. Optional parameters are enclosed in `[]`. + +### Supported Commands + +| Command (32 bytes zero padded) | Data Phase Direction | Description +|-----------------------------------------------------------|----------------------|------------ +| `GET VER` | OUT (16 bytes) | Returns firmware version in `major.minor.patch` format. +| `GET CAP` | OUT (32 bytes) | Returns supported mode/format/bit masks and speed limits. +| `SET BUF RX/TX,len[,pattern]` | IN (`1en` bytes) | Sets RX/TX buffer; optionally pre-fills with pattern. +| `GET BUF RX/TX,len` | OUT (`len` bytes) | Reads `len` bytes from RX/TX buffer. +| `SET COM mode,format,bit_num,bit_order,ss_mode,bus_speed` | | Sets custom SPI communication parameters for next `XFER`. +| `XFER num[,delay_c][,delay_t][,timeout]` | IN/OUT (`num` items) | Performs full-duplex SPI data transfer. +| `GET CNT` | OUT (16 bytes) | Returns count in decimal notation. + +## Command Parameters + +| Parameter | Description +|-------------|------------ +| `RX/TX` | RX = SPI Server receive buffer, TX = SPI Server transmit buffer +| `len` | Data length for data phase +| `pattern` | Hex value used to pre-fill buffer +| `mode` | 0 = Master, 1 = Slave +| `format` | 0 = Clock Polarity 0, Clock Phase 0 +| | 1 = Clock Polarity 0, Clock Phase 1 +| | 2 = Clock Polarity 1, Clock Phase 0 +| | 3 = Clock Polarity 1, Clock Phase 1 +| | 4 = Texas Instruments Frame Format +| | 5 = National Semiconductor Microwire Frame Format +| `bit_num` | Bits per frame (132) +| `bit_order` | 0 = MSB first, 1 = LSB first +| `ss_mode` | 0 = unused, 1 = Master-driven/Slave-monitored +| `bus_speed` | SPI clock rate (bps) +| `num` | Number of items (according CMSIS SPI driver specification) +| `delay_c` | Delay before Control function is called (ms) +| `delay_t` | Delay after Control function is called but before Transfer function is called (ms) +| `timeout` | Total transfer timeout including delay_c and delay_t delays, including delay_c and delay_t (ms) + +## Response Formats + +| Command | Response +|-------------|--------- +| `GET VER` | 16 bytes, "major.minor.patch" +| `GET CAP` | 32 bytes, "mode_mask,format_mask,data_bit_mask,bit_order_mask,min_bus_speed_in_kbps,max_bus_speed_in_kbps" +| | mode_mask (2 digits hex): specifies mask of supported modes +| | - bit 0.: Master +| | - bit 1.: Slave +| | format_mask (2 digits hex): specifies mask of supported clock/frame formats +| | - bit 0.: Clock Polarity 0, Clock Phase 0 +| | - bit 1.: Clock Polarity 0, Clock Phase 1 +| | - bit 2.: Clock Polarity 1, Clock Phase 0 +| | - bit 3.: Clock Polarity 1, Clock Phase 1 +| | - bit 4.: Texas Instruments Frame Format +| | - bit 5.: National Semiconductor Microwire Frame Format +| | data_bit_mask (8 digits hex): specifies mask of supported data bits +| | - bit 0.: Data Bits 1 +| | ... +| | - bit 31.: Data Bits 32 +| | bit_order_mask (2 digits hex): specifies mask of supported bit orders +| | - bit 0.: MSB first +| | - bit 1.: LSB first +| | min_bus_speed_in_kbps (dec): minimum supported bus speed (in kbps) +| | max_bus_speed_in_kbps (dec): maximum supported bus speed (in kbps) +| `GET BUF` | `len` bytes from respective buffer +| `GET CNT` | 16 bytes (dec) + +--- + +## Communication Example + +```text +-> GET VER <- "1.1.0" +-> GET CAP <- "03,1F,00008080,03,1000,10000" +-> SET BUF TX,0,53 (Fill TX with 'S') +-> SET BUF RX,0,3F (Fill RX with '?') +-> GET BUF RX,16 <- "????????????????" +-> SET COM 1,0,8,0,1,2000000 (Slave mode, CPOL=0, CPHA=0, 8-bit, MSB, 2 Mbps) +-> XFER 16,10,0,100 <-> 16-byte transfer +-> GET CNT <- "16" +``` + +--- + +## Build Targets + +| Target | Description +|-------------|------------ +| **Debug** | Low optimization build with STDOUT interface (for debugging). +| **Release** | Optimized binary without UI (for production testing). diff --git a/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.c b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.c.base@5.2.0 b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.c.base@5.2.0 new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.c.base@5.2.0 @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.h similarity index 85% rename from Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h rename to Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.h index 088d5c6..17b7a57 100644 --- a/Tools/SPI_Server/Board/STM32F429I-DISC1/RTE/CMSIS/RTX_Config.h +++ b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ * * ----------------------------------------------------------------------------- * - * $Revision: V5.5.2 + * $Revision: V5.6.0 * * Project: CMSIS-RTOS RTX * Title: RTX Configuration definitions @@ -69,6 +69,61 @@ // +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + // ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries @@ -142,11 +197,25 @@ #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + // Stack overrun checking // Enables stack overrun check at thread switch (requires RTX source variant). // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK -#define OS_STACK_CHECK 0 +#define OS_STACK_CHECK 1 #endif // Stack usage watermark @@ -156,10 +225,10 @@ #define OS_STACK_WATERMARK 0 #endif -// Processor mode for Thread execution +// Default Processor mode for Thread execution // <0=> Unprivileged mode // <1=> Privileged mode -// Default: Privileged mode +// Default: Unprivileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif @@ -211,6 +280,20 @@ #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + // Timer Callback Queue entries <0-256> // Number of concurrent active timer callback functions. // May be set to 0 when timers are not used. diff --git a/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.h.base@5.6.0 b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.h.base@5.6.0 new file mode 100644 index 0000000..fe0c57b --- /dev/null +++ b/Tools/SPI_Server/Template/RTE/CMSIS/RTX_Config.h.base@5.6.0 @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Unprivileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 0 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/Tools/SPI_Server/Template/SPI_Server.cproject.yml b/Tools/SPI_Server/Template/SPI_Server.cproject.yml new file mode 100644 index 0000000..9db227e --- /dev/null +++ b/Tools/SPI_Server/Template/SPI_Server.cproject.yml @@ -0,0 +1,51 @@ +project: + description: CMSIS Driver Validation SPI Server + + # List of packs used in the project. + packs: + - pack: ARM::CMSIS@^6.2.0 + - pack: ARM::CMSIS-RTX@^5.9.0 + + # List of connections required or provided by the project. + connections: + - connect: SPI Server + provides: + - CMSIS-RTOS2 + consumes: + - CMSIS_VIO + - STDOUT + + # List of include paths passed via the command line to the build tool + add-path: + - ./ + + # List of source groups and files. + groups: + - group: Documentation + files: + - file: README.md + - group: Source Files + files: + - file: app_main.c + - group: SPI Server Files + files: + - file: Config/SPI_Server_Config.h + - file: Include/SPI_Server.h + - file: Source/SPI_Server.c + + # List of components used by the application. + components: + - component: CMSIS:OS Tick:SysTick + - component: CMSIS:RTOS2:Keil RTX5&Source + + # List of layers used by the application. + layers: + - layer: $Board-Layer$ + type: Board + + # List of executable file formats to be generated. + output: + type: + - elf + - hex + - map diff --git a/Tools/SPI_Server/Template/SPI_Server.csolution.yml b/Tools/SPI_Server/Template/SPI_Server.csolution.yml new file mode 100644 index 0000000..a319d67 --- /dev/null +++ b/Tools/SPI_Server/Template/SPI_Server.csolution.yml @@ -0,0 +1,41 @@ +solution: + description: CMSIS Driver Validation SPI Server + created-for: CMSIS-Toolbox@2.11.0 + cdefault: + + # List of tested compilers that can be selected + select-compiler: + - compiler: AC6 + + compiler: AC6 # select compiler for solution + + # List of miscellaneous tool-specific controls + misc: + - for-compiler: AC6 # GDB requires DWARF 5, remove when using uVision Debugger + C-CPP: + - -gdwarf-5 + ASM: + - -gdwarf-5 + + # List different hardware targets that are used to deploy the solution. + target-types: + # - type: + # board: + # variables: + # - Board-Layer: .clayer.yml + + # List of different build configurations. + build-types: + - type: Debug + debug: on + optimize: debug + define: + - DEBUG: 1 + + - type: Release + debug: off + optimize: balanced + + # List related projects. + projects: + - project: SPI_Server.cproject.yml diff --git a/Tools/SPI_Server/Template/Source/SPI_Server.c b/Tools/SPI_Server/Template/Source/SPI_Server.c new file mode 100644 index 0000000..ea5c063 --- /dev/null +++ b/Tools/SPI_Server/Template/Source/SPI_Server.c @@ -0,0 +1,1419 @@ +/* + * Copyright (c) 2020-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: SPI Server + * Title: SPI Server application + * + * ----------------------------------------------------------------------------- + */ + + +#include +#include +#include +#include + +#include "SPI_Server_Config.h" +#include "SPI_Server.h" + +#include "cmsis_os2.h" +#include "cmsis_compiler.h" +#include "cmsis_vio.h" + +#include "Driver_SPI.h" // ::CMSIS Driver:SPI + +#ifndef SPI_SERVER_DEBUG +#define SPI_SERVER_DEBUG 0 +#endif + +// Fixed SPI Server settings (not available through SPI_Server_Config.h) +#define SPI_SERVER_SS_MODE 2 // Slave Select Hardware monitored +#define SPI_SERVER_FORMAT 0 // Clock Polarity 0 / Clock Phase 0 +#define SPI_SERVER_DATA_BITS 8 // 8 data bits +#define SPI_SERVER_BIT_ORDER 0 // MSB to LSB bit order + +#define SPI_EVENTS_MASK (ARM_SPI_EVENT_TRANSFER_COMPLETE | \ + ARM_SPI_EVENT_DATA_LOST | \ + ARM_SPI_EVENT_MODE_FAULT) + +#define DATA_BITS_TO_BYTES(data_bits) (((data_bits) > 16) ? (4U) : (((data_bits) > 8) ? (2U) : (1U))) +#define BYTES_TO_ITEMS(bytes,data_bits) ((bytes + DATA_BITS_TO_BYTES(data_bits) - 1U) / DATA_BITS_TO_BYTES(data_bits)) + +/* Access to Driver_SPI# */ +#define SPI_Driver_Aux(n) Driver_SPI##n +#define SPI_Driver_Name(n) SPI_Driver_Aux(n) +extern ARM_DRIVER_SPI SPI_Driver_Name(SPI_SERVER_DRV_NUM); +#define drvSPI (&SPI_Driver_Name(SPI_SERVER_DRV_NUM)) + +typedef struct { // SPI Interface settings structure + uint32_t mode; + uint32_t format; + uint32_t bit_num; + uint32_t bit_order; + uint32_t ss_mode; + uint32_t bus_speed; +} SPI_COM_CONFIG_t; + +// Structure containing command string and pointer to command handling function +typedef struct { + const char *command; + int32_t (*Command_Func) (const char *command); +} SPI_CMD_DESC_t; + +// Local functions + +// Main thread (reception and execution of command) +__NO_RETURN \ +static void SPI_Server_Thread (void *argument); + +// SPI Interface communication functions +static void SPI_Com_Event (uint32_t event); +static int32_t SPI_Com_Initialize (void); +static int32_t SPI_Com_Uninitialize (void); +static int32_t SPI_Com_PowerOn (void); +static int32_t SPI_Com_PowerOff (void); +static int32_t SPI_Com_Configure (const SPI_COM_CONFIG_t *config); +static uint32_t SPI_Com_SS (uint32_t active); +static int32_t SPI_Com_Receive ( void *data_in, uint32_t num, uint32_t timeout); +static int32_t SPI_Com_Send (const void *data_out, uint32_t num, uint32_t timeout); +static int32_t SPI_Com_Transfer (const void *data_out, void *data_in, uint32_t num, uint32_t timeout); +static int32_t SPI_Com_Abort (void); +static uint32_t SPI_Com_GetCnt (void); + +// Command handling functions +static int32_t SPI_Cmd_GetVer (const char *cmd); +static int32_t SPI_Cmd_GetCap (const char *cmd); +static int32_t SPI_Cmd_SetBuf (const char *cmd); +static int32_t SPI_Cmd_GetBuf (const char *cmd); +static int32_t SPI_Cmd_SetCom (const char *cmd); +static int32_t SPI_Cmd_Xfer (const char *cmd); +static int32_t SPI_Cmd_GetCnt (const char *cmd); + +// Local variables + +// Command specification (command string, command handling function) +static const SPI_CMD_DESC_t spi_cmd_desc[] = { + { "GET VER" , SPI_Cmd_GetVer }, + { "GET CAP" , SPI_Cmd_GetCap }, + { "SET BUF" , SPI_Cmd_SetBuf }, + { "GET BUF" , SPI_Cmd_GetBuf }, + { "SET COM" , SPI_Cmd_SetCom }, + { "XFER" , SPI_Cmd_Xfer }, + { "GET CNT" , SPI_Cmd_GetCnt } +}; + +static osThreadId_t spi_server_thread_id = NULL; +static osThreadAttr_t thread_attr = { + .name = "SPI_Server_Thread", + .stack_size = 512U +}; + +static uint8_t spi_server_state = SPI_SERVER_STATE_RECEPTION; +static uint32_t spi_cmd_timeout = SPI_SERVER_CMD_TIMEOUT; +static uint32_t spi_xfer_timeout = SPI_SERVER_CMD_TIMEOUT; +static uint32_t spi_xfer_cnt = 0U; +static uint32_t spi_xfer_buf_size = SPI_SERVER_BUF_SIZE; +static const SPI_COM_CONFIG_t spi_com_config_default = { ARM_SPI_MODE_SLAVE, + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk), + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk), + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk), + ARM_SPI_SS_SLAVE_HW, + 0U // Bus speed for Slave mode is unused + }; +static const SPI_COM_CONFIG_t spi_com_config_inactive= { ARM_SPI_MODE_INACTIVE, 0U, 0U, 0U, 0U, 0U }; +static SPI_COM_CONFIG_t spi_com_config_xfer; +static uint8_t spi_bytes_per_item = 1U; +static uint8_t spi_cmd_buf_rx[32] __ALIGNED(4); +static uint8_t spi_cmd_buf_tx[32] __ALIGNED(4); +static uint8_t *ptr_spi_xfer_buf_rx = NULL; +static uint8_t *ptr_spi_xfer_buf_tx = NULL; +static void *ptr_spi_xfer_buf_rx_alloc = NULL; +static void *ptr_spi_xfer_buf_tx_alloc = NULL; + +// Global functions + +/** + \fn int32_t SPI_Server_Start (void) + \brief Initialize, power up, configure SPI interface and start SPI Server thread. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +int32_t SPI_Server_Start (void) { + int32_t ret; + +#ifdef DEBUG + printf("SPI Server v%s\r\n", SPI_SERVER_VER); +#endif + + // Initialize local variables + spi_server_state = SPI_SERVER_STATE_RECEPTION; + spi_cmd_timeout = SPI_SERVER_CMD_TIMEOUT; + spi_xfer_timeout = SPI_SERVER_CMD_TIMEOUT; + spi_xfer_cnt = 0U; + spi_xfer_buf_size = SPI_SERVER_BUF_SIZE; + spi_bytes_per_item = DATA_BITS_TO_BYTES(SPI_SERVER_DATA_BITS); + memset(spi_cmd_buf_rx, 0, sizeof(spi_cmd_buf_rx)); + memset(spi_cmd_buf_tx, 0, sizeof(spi_cmd_buf_tx)); + memcpy(&spi_com_config_xfer, &spi_com_config_default, sizeof(SPI_COM_CONFIG_t)); + + // Allocate buffers for data transmission and reception + // (maximum size is incremented by 4 bytes to ensure that buffer can be aligned to 4 bytes) + + ptr_spi_xfer_buf_rx_alloc = malloc(SPI_SERVER_BUF_SIZE + 4U); + if (((uint32_t)ptr_spi_xfer_buf_rx_alloc & 3U) != 0U) { + // If allocated memory is not 4 byte aligned, use next 4 byte aligned address for ptr_tx_buf + ptr_spi_xfer_buf_rx = (uint8_t *)((((uint32_t)ptr_spi_xfer_buf_rx_alloc) + 3U) & (~3U)); + } else { + // If allocated memory is 4 byte aligned, use it directly + ptr_spi_xfer_buf_rx = (uint8_t *)ptr_spi_xfer_buf_rx_alloc; + } + ptr_spi_xfer_buf_tx_alloc = malloc(SPI_SERVER_BUF_SIZE + 4U); + if (((uint32_t)ptr_spi_xfer_buf_tx_alloc & 3U) != 0U) { + // If allocated memory is not 4 byte aligned, use next 4 byte aligned address for ptr_tx_buf + ptr_spi_xfer_buf_tx = (uint8_t *)((((uint32_t)ptr_spi_xfer_buf_tx_alloc) + 3U) & (~3U)); + } else { + // If allocated memory is 4 byte aligned, use it directly + ptr_spi_xfer_buf_tx = (uint8_t *)ptr_spi_xfer_buf_tx_alloc; + } + + if ((ptr_spi_xfer_buf_rx != NULL) || (ptr_spi_xfer_buf_tx != NULL)) { + memset(ptr_spi_xfer_buf_rx, 0, SPI_SERVER_BUF_SIZE); + memset(ptr_spi_xfer_buf_rx, 0, SPI_SERVER_BUF_SIZE); + ret = EXIT_SUCCESS; + } else { + ret = EXIT_FAILURE; + } + + if (ret == EXIT_SUCCESS) { + ret = SPI_Com_Initialize(); + } + + if (ret == EXIT_SUCCESS) { + ret = SPI_Com_PowerOn(); + } + + if (ret == EXIT_SUCCESS) { + ret = SPI_Com_Configure(&spi_com_config_default); + } + + if ((ret == EXIT_SUCCESS) && (spi_server_thread_id == NULL)) { + // Create SPI_Server_Thread thread + spi_server_thread_id = osThreadNew(SPI_Server_Thread, NULL, &thread_attr); + if (spi_server_thread_id == NULL) { + ret = EXIT_FAILURE; + } + } + +#ifdef DEBUG + if (ret != EXIT_SUCCESS) { + printf("Server Start failed!\r\n"); + } +#endif + + return ret; +} + +/** + \fn int32_t SPI_Server_Stop (void) + \brief Terminate SPI Server thread, power down and uninitialize SPI interface. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +int32_t SPI_Server_Stop (void) { + int32_t ret; + uint32_t i; + + ret = EXIT_FAILURE; + + if (spi_server_thread_id != NULL) { + spi_server_state = SPI_SERVER_STATE_TERMINATE; + for (i = 0U; i < 10U; i++) { + if (osThreadGetState(spi_server_thread_id) == osThreadTerminated) { + spi_server_thread_id = NULL; + ret = EXIT_SUCCESS; + break; + } + (void)osDelay(100U); + } + } + + if (ret == EXIT_SUCCESS) { + ret = SPI_Com_PowerOff(); + } + + if (ret == EXIT_SUCCESS) { + ret = SPI_Com_Uninitialize(); + } + + if (ptr_spi_xfer_buf_rx_alloc != NULL) { + free(ptr_spi_xfer_buf_rx_alloc); + ptr_spi_xfer_buf_rx = NULL; + ptr_spi_xfer_buf_rx_alloc = NULL; + } + if (ptr_spi_xfer_buf_tx_alloc != NULL) { + free(ptr_spi_xfer_buf_tx_alloc); + ptr_spi_xfer_buf_tx = NULL; + ptr_spi_xfer_buf_tx_alloc = NULL; + } + +#ifdef DEBUG + if (ret != EXIT_SUCCESS) { + printf("Server Stop failed!\r\n"); + } +#endif + + return ret; +} + + +// Local functions + +/** + \fn static void SPI_Server_Thread (void *argument) + \brief SPI Server thread function. + \detail This is a thread function that waits to receive a command from SPI Client + (Driver Validation suite), and after command is received it is executed + and the process starts again by waiting to receive next command. + \param[in] argument Not used + \return none +*/ +static void SPI_Server_Thread (void *argument) { + uint8_t i; + + (void)argument; + + for (;;) { + switch (spi_server_state) { + + case SPI_SERVER_STATE_RECEPTION: // Receive a command + if (SPI_Com_Receive(spi_cmd_buf_rx, BYTES_TO_ITEMS(sizeof(spi_cmd_buf_rx),SPI_SERVER_DATA_BITS), osWaitForever) == EXIT_SUCCESS) { + spi_server_state = SPI_SERVER_STATE_EXECUTION; + } + // If 32 byte command was not received restart the reception of 32 byte command + break; + + case SPI_SERVER_STATE_EXECUTION: // Execute a command + // Find the command and call handling function + for (i = 0U; i < (sizeof(spi_cmd_desc) / sizeof(SPI_CMD_DESC_t)); i++) { + if (memcmp(spi_cmd_buf_rx, spi_cmd_desc[i].command, strlen(spi_cmd_desc[i].command)) == 0) { + (void)spi_cmd_desc[i].Command_Func((const char *)spi_cmd_buf_rx); + break; + } + } +#ifdef DEBUG + printf("%.20s\r\n", spi_cmd_buf_rx); +#endif + spi_server_state = SPI_SERVER_STATE_RECEPTION; + break; + + case SPI_SERVER_STATE_TERMINATE: // Self-terminate the thread + default: // Should never happen, processed as terminate request +#ifdef DEBUG + printf("Server stopped!\r\n"); +#endif + (void)SPI_Com_Abort(); + (void)osThreadTerminate(osThreadGetId()); + break; + } + } +} + +/** + \fn static void SPI_Com_Event (uint32_t event) + \brief SPI communication event callback (called from SPI driver from IRQ context). + \detail This function dispatches event (flag) to SPI Server thread. + \param[in] event SPI event + - ARM_SPI_EVENT_TRANSFER_COMPLETE: Data Transfer completed + - ARM_SPI_EVENT_DATA_LOST: Data lost: Receive overflow / Transmit underflow + - ARM_SPI_EVENT_MODE_FAULT: Master Mode Fault (SS deactivated when Master) + \return none +*/ +static void SPI_Com_Event (uint32_t event) { + + if (spi_server_thread_id != NULL) { + (void)osThreadFlagsSet(spi_server_thread_id, event); + } +} + +/** + \fn static int32_t SPI_Com_Initialize (void) + \brief Initialize SPI interface. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Initialize (void) { + int32_t ret; + + ret = EXIT_FAILURE; + + if (drvSPI->Initialize(SPI_Com_Event) == ARM_DRIVER_OK) { + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_Uninitialize (void) + \brief Uninitialize SPI interface. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Uninitialize (void) { + int32_t ret; + + ret = EXIT_FAILURE; + + if (drvSPI->Uninitialize() == ARM_DRIVER_OK) { + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_PowerOn (void) + \brief Power-up SPI interface. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_PowerOn (void) { + int32_t ret; + + ret = EXIT_FAILURE; + + if (drvSPI->PowerControl(ARM_POWER_FULL) == ARM_DRIVER_OK) { + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_PowerOff (void) + \brief Power-down SPI interface. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_PowerOff (void) { + int32_t ret; + + ret = EXIT_FAILURE; + + if (drvSPI->PowerControl(ARM_POWER_OFF) == ARM_DRIVER_OK) { + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_Configure (const SPI_COM_CONFIG_t *config) + \brief Configure SPI interface. + \param[in] config Pointer to structure containing SPI interface configuration settings + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Configure (const SPI_COM_CONFIG_t *config) { + int32_t ret; + + ret = EXIT_FAILURE; + + if (drvSPI->Control(config->mode | + config->format | + config->bit_num | + config->bit_order | + config->ss_mode , + config->bus_speed ) == ARM_DRIVER_OK) { + spi_bytes_per_item = DATA_BITS_TO_BYTES((config->bit_num & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static uint32_t SPI_Com_SS (void) + \brief Drive Slave Select line with Control function. + \return number of data items transferred +*/ +static uint32_t SPI_Com_SS (uint32_t active) { + int32_t ret; + uint32_t arg; + + ret = EXIT_FAILURE; + + if (active != 0U) { + arg = ARM_SPI_SS_ACTIVE; + } else { + arg = ARM_SPI_SS_INACTIVE; + } + + if (drvSPI->Control(ARM_SPI_CONTROL_SS, arg) == ARM_DRIVER_OK) { + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_Receive (void *data_in, uint32_t num, uint32_t timeout) + \brief Receive data (command) over SPI interface. + \param[out] data_in Pointer to memory where data will be received + \param[in] num Number of data items to be received + \param[in] timeout Timeout for reception (in ms) + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Receive (void *data_in, uint32_t num, uint32_t timeout) { + int32_t ret; + uint32_t flags, tmo, time, cnt; + + ret = EXIT_FAILURE; + + if (spi_server_thread_id != NULL) { + memset(data_in, (int32_t)'?', spi_bytes_per_item * num); + vioSetSignal (vioLED0, vioLEDon); + cnt = 0; + time = timeout; + if (drvSPI->Receive(data_in, num) == ARM_DRIVER_OK) { + while (time != 0U) { + if (time > 100U) { + tmo = 100U; + } else { + tmo = time; + } + flags = osThreadFlagsWait(SPI_EVENTS_MASK, osFlagsWaitAny, tmo); + if (flags == osFlagsErrorTimeout) { // If timeout + if (time != osWaitForever) { + time -= tmo; + } + if (drvSPI->GetDataCount() != 0U) { + while (cnt != drvSPI->GetDataCount()) { // While count is changing + cnt = drvSPI->GetDataCount(); + flags = osThreadFlagsWait(SPI_EVENTS_MASK, osFlagsWaitAny, 10U); + if (flags == osFlagsErrorTimeout) { // If timeout + if (time != osWaitForever) { + if (time > tmo) { + time -= tmo; + } else { + time = 0U; + break; + } + } + } else if ((flags & (0x80000000U | ARM_SPI_EVENT_TRANSFER_COMPLETE)) == ARM_SPI_EVENT_TRANSFER_COMPLETE) { + // If completed event was signaled + ret = EXIT_SUCCESS; + break; + } else { + // In all other cases exit with failed status + break; + } + } + if (cnt != 0U) { + // If something was received but not of expected size then terminate the reception + break; + } + } + } else if ((flags & (0x80000000U | ARM_SPI_EVENT_TRANSFER_COMPLETE)) == ARM_SPI_EVENT_TRANSFER_COMPLETE) { + // If completed event was signaled + ret = EXIT_SUCCESS; + break; + } else { + // In all other cases exit with failed status + break; + } + } + if (ret != EXIT_SUCCESS) { + // If receive was activated but failed to receive expected data then abort the transfer + (void)drvSPI->Control(ARM_SPI_ABORT_TRANSFER, 0U); + } + vioSetSignal (vioLED0, vioLEDoff); + } + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_Send (const void *data_out, uint32_t num, uint32_t timeout) + \brief Send data (response) over SPI interface. + \param[out] data_out Pointer to memory containing data to be sent + \param[in] num Number of data items to be sent + \param[in] timeout Timeout for send (in ms) + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Send (const void *data_out, uint32_t num, uint32_t timeout) { + uint32_t flags; + int32_t ret; + + ret = EXIT_FAILURE; + + if (spi_server_thread_id != NULL) { + vioSetSignal (vioLED1, vioLEDon); + if (drvSPI->Send(data_out, num) == ARM_DRIVER_OK) { + flags = osThreadFlagsWait(SPI_EVENTS_MASK, osFlagsWaitAny, timeout); + if ((flags & (0x80000000U | ARM_SPI_EVENT_TRANSFER_COMPLETE)) == ARM_SPI_EVENT_TRANSFER_COMPLETE) { + // If completed event was signaled + ret = EXIT_SUCCESS; + } + if (ret != EXIT_SUCCESS) { + // If send was activated but failed to send all of the expected data then abort the transfer + (void)drvSPI->Control(ARM_SPI_ABORT_TRANSFER, 0U); + } + vioSetSignal (vioLED1, vioLEDoff); + } + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_Transfer (const void *data_out, void *data_in, uint32_t num, uint32_t timeout) + \brief Transfer (send/receive) data over SPI interface. + \param[in] data_out Pointer to memory containing data to be sent + \param[out] data_in Pointer to memory where data will be received + \param[in] num Number of data items to be transferred + \param[in] timeout Timeout for transfer (in ms) + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Transfer (const void *data_out, void *data_in, uint32_t num, uint32_t timeout) { + uint32_t flags; + int32_t ret; + + ret = EXIT_FAILURE; + + if (spi_server_thread_id != NULL) { + vioSetSignal (vioLED2, vioLEDon); + if (drvSPI->Transfer(data_out, data_in, num) == ARM_DRIVER_OK) { + flags = osThreadFlagsWait(SPI_EVENTS_MASK, osFlagsWaitAny, timeout); + spi_xfer_cnt = drvSPI->GetDataCount(); + if ((flags & (0x80000000U | ARM_SPI_EVENT_TRANSFER_COMPLETE)) == ARM_SPI_EVENT_TRANSFER_COMPLETE) { + // If completed event was signaled + ret = EXIT_SUCCESS; + } else { + // If error or timeout + (void)drvSPI->Control(ARM_SPI_ABORT_TRANSFER, 0U); + } + vioSetSignal (vioLED2, vioLEDoff); + } + } + + return ret; +} + +/** + \fn static int32_t SPI_Com_Abort (void) + \brief Abort current transfer on SPI interface. + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Com_Abort (void) { + int32_t ret; + + ret = EXIT_FAILURE; + + if (drvSPI->Control(ARM_SPI_ABORT_TRANSFER, 0U) == ARM_DRIVER_OK) { + ret = EXIT_SUCCESS; + } + + return ret; +} + +/** + \fn static uint32_t SPI_Com_GetCnt (void) + \brief Get number of data items transferred over SPI interface in last transfer. + \return number of data items transferred +*/ +static uint32_t SPI_Com_GetCnt (void) { + return spi_xfer_cnt; +} + + +// Command handling functions + +/** + \fn static int32_t SPI_Cmd_GetVer (const char *cmd) + \brief Handle command "GET VER". + \detail Return SPI Server version over SPI interface (16 bytes). + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_GetVer (const char *cmd) { + + (void)cmd; + + memset(spi_cmd_buf_tx, 0, 16); + memcpy(spi_cmd_buf_tx, SPI_SERVER_VER, sizeof(SPI_SERVER_VER)); + + return (SPI_Com_Send(spi_cmd_buf_tx, BYTES_TO_ITEMS(16U, SPI_SERVER_DATA_BITS), spi_cmd_timeout)); +} + +/** + \fn static int32_t SPI_Cmd_GetCap (const char *cmd) + \brief Handle command "GET CAP". + \detail Return SPI Server capabilities over SPI interface (32 bytes). + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_GetCap (const char *cmd) { + int32_t ret; + uint32_t mode_mask, format_mask, data_bits_mask, bit_order_mask, bus_speed_min, bus_speed_max; + uint32_t bs; + uint8_t i; + + (void)cmd; + + ret = EXIT_FAILURE; + + // Determine supported minimum bus speed + // Find minimum speed setting at which Control function succeeds + bs = 1000U; + do { + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs ) == ARM_DRIVER_OK) { + break; + } + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs * 2U) == ARM_DRIVER_OK) { + bs *= 2U; + break; + } + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs * 5U) == ARM_DRIVER_OK) { + bs *= 5U; + break; + } + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs * 10U) == ARM_DRIVER_OK) { + bs *= 10U; + break; + } + bs *= 10U; + } while (bs < 1000000U); + bus_speed_min = bs; + + // Determine supported maximum bus speed + // Find maximum speed setting at which Control function succeeds + bs = 100000000U; + do { + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs ) == ARM_DRIVER_OK) { + break; + } + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs / 2U) == ARM_DRIVER_OK) { + bs /= 2U; + break; + } + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs / 5U) == ARM_DRIVER_OK) { + bs /= 5U; + break; + } + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bs / 10U) == ARM_DRIVER_OK) { + bs /= 10U; + break; + } + bs /= 10U; + } while (bs > 1000000U); + bus_speed_max = bs; + + // Determine supported modes + mode_mask = 0U; + if (drvSPI->Control(ARM_SPI_MODE_MASTER | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_MASTER_HW_OUTPUT , + bus_speed_min ) == ARM_DRIVER_OK) { + mode_mask |= 1U; + } + + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + mode_mask |= 1U << 1; + } + + // Determine supported clock / frame format + format_mask = 0U; + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ARM_SPI_CPOL0_CPHA0 | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + format_mask |= 1U; + } + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ARM_SPI_CPOL0_CPHA1 | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + format_mask |= 1U << 1; + } + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ARM_SPI_CPOL1_CPHA0 | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + format_mask |= 1U << 2; + } + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ARM_SPI_CPOL1_CPHA1 | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + format_mask |= 1U << 3; + } + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ARM_SPI_TI_SSI | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + format_mask |= 1U << 4; + } + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ARM_SPI_MICROWIRE | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + format_mask |= 1U << 5; + } + + // Determine supported data bits + data_bits_mask = 0U; + for (i = 1U; i <= 32U; i++) { + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((i << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ((SPI_SERVER_BIT_ORDER << ARM_SPI_BIT_ORDER_Pos) & ARM_SPI_BIT_ORDER_Msk) | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + data_bits_mask |= 1UL << (i - 1U); + } + } + + // Determine bit order + bit_order_mask = 0U; + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ARM_SPI_MSB_LSB | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + bit_order_mask |= 1U; + } + if (drvSPI->Control(ARM_SPI_MODE_SLAVE | + ((SPI_SERVER_FORMAT << ARM_SPI_FRAME_FORMAT_Pos) & ARM_SPI_FRAME_FORMAT_Msk) | + ((SPI_SERVER_DATA_BITS << ARM_SPI_DATA_BITS_Pos) & ARM_SPI_DATA_BITS_Msk) | + ARM_SPI_LSB_MSB | + ARM_SPI_SS_SLAVE_HW , + 0U ) == ARM_DRIVER_OK) { + bit_order_mask |= 1U << 1; + } + + // Revert communication settings to default because they were changed during auto-detection of capabilities + (void)SPI_Com_Configure(&spi_com_config_default); + + memset(spi_cmd_buf_tx, 0, 32); + if (snprintf((char *)spi_cmd_buf_tx, 32, "%02X,%02X,%08X,%02X,%i,%i", + mode_mask, + format_mask, + data_bits_mask, + bit_order_mask, + (bus_speed_min / 1000U), + (bus_speed_max / 1000U)) <= 32) { + ret = SPI_Com_Send(spi_cmd_buf_tx, BYTES_TO_ITEMS(32U, SPI_SERVER_DATA_BITS), spi_cmd_timeout); + } + + return ret; +} + +/** + \fn static int32_t SPI_Cmd_SetBuf (const char *cmd) + \brief Handle command "SET BUF RX/TX,len[,pattern]". + \detail Initialize content of the buffer in the following way: + - fill whole buffer with 'pattern' value if it is specified, and 'len' is 0 + - fill whole buffer with 0 if 'pattern' is not provided and 'len' is 0 + - load 'len' bytes from start of the buffer with content + received in IN data phase + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_SetBuf (const char *cmd) { + const char *ptr_str; + uint8_t *ptr_buf; + uint32_t val, len; + uint8_t pattern; + int32_t ret; + + ret = EXIT_SUCCESS; + ptr_str = NULL; + ptr_buf = NULL; + val = 0U; + len = 0U; + pattern = 0U; + + // Parse 'RX' or 'TX' selection + if (strstr(cmd, "RX") != NULL) { + ptr_buf = ptr_spi_xfer_buf_rx; + } else if (strstr(cmd, "TX") != NULL) { + ptr_buf = ptr_spi_xfer_buf_tx; + } else { + ret = EXIT_FAILURE; + } + + if (ret == EXIT_SUCCESS) { + // Parse 'len' + ptr_str = strstr(cmd, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if (val <= spi_xfer_buf_size) { + len = val; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse optional 'pattern' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%x", &val) == 1) { + pattern = (uint8_t)val; + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_buf != NULL)) { + // Fill the whole buffer with 'pattern', if 'pattern' was not specified + // in the command then the whole buffer will be filled with 0 + memset(ptr_buf, (int32_t)pattern, spi_xfer_buf_size); + } + + if ((ret == EXIT_SUCCESS) && (ptr_buf != NULL) && (len != 0U)) { + // Load 'len' bytes from start of buffer with content received in IN data phase + ret = SPI_Com_Receive(ptr_buf, BYTES_TO_ITEMS(len, SPI_SERVER_DATA_BITS), spi_cmd_timeout); + } + + return ret; +} + +/** + \fn static int32_t SPI_Cmd_GetBuf (const char *cmd) + \brief Handle command "GET BUF RX/TX,len". + \detail Send content of buffer over SPI interface. + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_GetBuf (const char *cmd) { + const char *ptr_str; + const uint8_t *ptr_buf; + uint32_t val, len; + int32_t ret; + + ret = EXIT_SUCCESS; + ptr_str = NULL; + ptr_buf = NULL; + val = 0U; + len = 0U; + + // Parse 'RX' or 'TX' selection + if (strstr(cmd, "RX") != NULL) { + ptr_buf = ptr_spi_xfer_buf_rx; + } else if (strstr(cmd, "TX") != NULL) { + ptr_buf = ptr_spi_xfer_buf_tx; + } else { + ret = EXIT_FAILURE; + } + + if (ret == EXIT_SUCCESS) { + // Parse 'len' + ptr_str = strstr(cmd, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if ((val > 0U) && (val <= spi_xfer_buf_size)) { + len = val; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_buf != NULL) && (len != 0U)) { + ret = SPI_Com_Send(ptr_buf, BYTES_TO_ITEMS(len, SPI_SERVER_DATA_BITS), spi_cmd_timeout); + } + + return ret; +} + +/** + \fn static int32_t SPI_Cmd_SetCom (const char *cmd) + \brief Handle command "SET COM mode,format,bit_num,bit_order,ss_mode,bus_speed". + \detail Set communication configuration settings used for transfers (XFER commands). + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_SetCom (const char *cmd) { + const char *ptr_str; + uint32_t val; + int32_t ret; + + ret = EXIT_SUCCESS; + val = 0U; + + ptr_str = &cmd[7]; // Skip "SET COM" + while (*ptr_str == ' ') { // Skip whitespaces + ptr_str++; + } + + // Parse 'mode' + if (sscanf(ptr_str, "%u", &val) == 1) { + switch (val) { + case 0U: // Master mode + spi_com_config_xfer.mode = ARM_SPI_MODE_MASTER; + break; + case 1U: // Slave mode + spi_com_config_xfer.mode = ARM_SPI_MODE_SLAVE; + break; + default: + ret = EXIT_FAILURE; + break; + } + } else { + ret = EXIT_FAILURE; + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse 'format' (clock polarity/phase or frame format) + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + switch (val) { + case 0: // Clock polarity 0, clock phase 0 + spi_com_config_xfer.format = ARM_SPI_CPOL0_CPHA0; + break; + case 1: // Clock polarity 0, clock phase 1 + spi_com_config_xfer.format = ARM_SPI_CPOL0_CPHA1; + break; + case 2: // Clock polarity 1, clock phase 0 + spi_com_config_xfer.format = ARM_SPI_CPOL1_CPHA0; + break; + case 3: // Clock polarity 1, clock phase 1 + spi_com_config_xfer.format = ARM_SPI_CPOL1_CPHA1; + break; + case 4: // Texas Instruments Frame Format + spi_com_config_xfer.format = ARM_SPI_TI_SSI; + break; + case 5: // National Microwire Frame Format + spi_com_config_xfer.format = ARM_SPI_MICROWIRE; + break; + default: + ret = EXIT_FAILURE; + break; + } + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse 'bit_num' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if ((val > 0U) && (val <= 32U)) { + spi_com_config_xfer.bit_num = ARM_SPI_DATA_BITS(val); + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse 'bit_order' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if (val == 0U) { + spi_com_config_xfer.bit_order = ARM_SPI_MSB_LSB; + } else if (val == 1U) { + spi_com_config_xfer.bit_order = ARM_SPI_LSB_MSB; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse 'ss_mode' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if (spi_com_config_xfer.mode == ARM_SPI_MODE_MASTER) { + // Slave Select modes for Master mode + switch (val) { + case 0: + spi_com_config_xfer.ss_mode = ARM_SPI_SS_MASTER_UNUSED; + break; + case 1: + spi_com_config_xfer.ss_mode = ARM_SPI_SS_MASTER_SW; + break; + default: + ret = EXIT_FAILURE; + break; + } + } else { + // Slave Select modes for Slave mode + switch (val) { + case 0: + spi_com_config_xfer.ss_mode = ARM_SPI_SS_SLAVE_SW; + break; + case 1: + spi_com_config_xfer.ss_mode = ARM_SPI_SS_SLAVE_HW; + break; + default: + ret = EXIT_FAILURE; + break; + } + } + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse 'bus_speed' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + spi_com_config_xfer.bus_speed = val; + } else { + ret = EXIT_FAILURE; + } + } + } + + return ret; +} + +/** + \fn static int32_t SPI_Cmd_Xfer (const char *cmd) + \brief Handle command "XFER num[,delay_c][,delay_t][,timeout]". + \detail Send data from SPI TX buffer and receive data to SPI RX buffer + (buffers must be set with "SET BUF" command before this command). + Control function is delayed by optional parameter 'delay_c' in milliseconds. + Transfer function is delayed by optional parameter 'delay_t' in milliseconds, + starting after delay specified with 'delay_c' parameter. + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_Xfer (const char *cmd) { + const char *ptr_str; + uint32_t val, num, delay_c, delay_t, start_tick, curr_tick; + int32_t ret; + + ret = EXIT_SUCCESS; + val = 0U; + num = 0U; + delay_c = 0U; + delay_t = 0U; + + ptr_str = &cmd[4]; // Skip "XFER" + while (*ptr_str == ' ') { // Skip whitespaces + ptr_str++; + } + + // Parse 'num' + if (sscanf(ptr_str, "%u", &val) == 1) { + if ((val > 0U) && (val <= spi_xfer_buf_size)) { + num = val; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse optional 'delay_c' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if (val != osWaitForever) { + delay_c = val; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse optional 'delay_t' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if (val != osWaitForever) { + delay_t = val; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + } + + if ((ret == EXIT_SUCCESS) && (ptr_str != NULL)) { + // Parse optional 'timeout' + ptr_str = strstr(ptr_str, ","); // Find ',' + if (ptr_str != NULL) { // If ',' was found + ptr_str++; // Skip ',' + while (*ptr_str == ' ') { // Skip whitespaces after ',' + ptr_str++; + } + if (sscanf(ptr_str, "%u", &val) == 1) { + if (val != osWaitForever) { + spi_xfer_timeout = val; + } else { + ret = EXIT_FAILURE; + } + } else { + ret = EXIT_FAILURE; + } + } + } + + start_tick = osKernelGetTickCount(); + + if (ret == EXIT_SUCCESS) { + // Deactivate SPI + ret = SPI_Com_Configure(&spi_com_config_inactive); + } + + if ((ret == EXIT_SUCCESS) && (delay_c != 0U)) { + // Delay before Control function is called + (void)osDelay(delay_c); + } + + if (ret == EXIT_SUCCESS) { + // Configure communication settings before transfer + ret = SPI_Com_Configure(&spi_com_config_xfer); + } + + if ((ret == EXIT_SUCCESS) && (delay_t != 0U)) { + // Delay before Transfer function is called + (void)osDelay(delay_t); + } + + if ((ret == EXIT_SUCCESS) && + ((spi_com_config_xfer.mode == ARM_SPI_MODE_SLAVE) && + (spi_com_config_xfer.ss_mode == ARM_SPI_SS_SLAVE_SW)) || + ((spi_com_config_xfer.mode == ARM_SPI_MODE_MASTER) && + (spi_com_config_xfer.ss_mode == ARM_SPI_SS_MASTER_SW))) { + ret = SPI_Com_SS(1U); + } + + if (ret == EXIT_SUCCESS) { + // Transfer data + ret = SPI_Com_Transfer(ptr_spi_xfer_buf_tx, ptr_spi_xfer_buf_rx, num, spi_xfer_timeout); + } + + if ((ret == EXIT_SUCCESS) && + ((spi_com_config_xfer.mode == ARM_SPI_MODE_SLAVE) && + (spi_com_config_xfer.ss_mode == ARM_SPI_SS_SLAVE_SW)) || + ((spi_com_config_xfer.mode == ARM_SPI_MODE_MASTER) && + (spi_com_config_xfer.ss_mode == ARM_SPI_SS_MASTER_SW))) { + ret = SPI_Com_SS(0U); + } + + // Deactivate SPI + (void)SPI_Com_Configure(&spi_com_config_inactive); + + // Wait until timeout expires + curr_tick = osKernelGetTickCount(); + if ((curr_tick - start_tick) < spi_xfer_timeout) { + (void)osDelay(spi_xfer_timeout - (curr_tick - start_tick)); + } + + // Wait additional 10 ms to insure that Client has deactivated + (void)osDelay(10U); + + // Revert communication settings to default + (void)SPI_Com_Configure(&spi_com_config_default); + + return ret; +} + +/** + \fn static int32_t SPI_Cmd_GetCnt (const char *cmd) + \brief Handle command "GET CNT". + \detail Return number of items transferred (sent/received) in last transfer + (requested by last XFER command). + \param[in] cmd Pointer to null-terminated command string + \return execution status + - EXIT_SUCCESS: Operation successful + - EXIT_FAILURE: Operation failed +*/ +static int32_t SPI_Cmd_GetCnt (const char *cmd) { + int32_t ret; + + (void)cmd; + + ret = EXIT_FAILURE; + + memset(spi_cmd_buf_tx, 0, 16); + if (snprintf((char *)spi_cmd_buf_tx, 16, "%u", SPI_Com_GetCnt()) < 16) { + ret = SPI_Com_Send(spi_cmd_buf_tx, BYTES_TO_ITEMS(16U, SPI_SERVER_DATA_BITS), spi_cmd_timeout); + } + + return ret; +} diff --git a/Tools/SPI_Server/Template/app_main.c b/Tools/SPI_Server/Template/app_main.c new file mode 100644 index 0000000..369d2eb --- /dev/null +++ b/Tools/SPI_Server/Template/app_main.c @@ -0,0 +1,53 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#include "app_main.h" + +#include "cmsis_os2.h" + +#include "SPI_Server.h" + +// Main stack size must be multiple of 8 Bytes +#define APP_MAIN_STK_SZ (4096U) +static uint64_t app_main_stk[APP_MAIN_STK_SZ / 8]; +static const osThreadAttr_t app_main_attr = { + .stack_mem = &app_main_stk[0], + .stack_size = sizeof(app_main_stk) +}; + +/*--------------------------------------------------------------------------- + * Application main thread + *---------------------------------------------------------------------------*/ +void app_main_thread (void *argument) { + (void)argument; + + SPI_Server_Start(); // Start SPI Server + + osThreadExit(); +} + +/*--------------------------------------------------------------------------- + * Application main function + *---------------------------------------------------------------------------*/ +int32_t app_main (void) { + osKernelInitialize(); + osThreadNew(app_main_thread, NULL, &app_main_attr); + osKernelStart(); + return 0; +} diff --git a/Tools/SPI_Server/Template/app_main.h b/Tools/SPI_Server/Template/app_main.h new file mode 100644 index 0000000..c2f29b3 --- /dev/null +++ b/Tools/SPI_Server/Template/app_main.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2025 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_MAIN_H_ +#define APP_MAIN_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +extern int32_t app_main (void); + +#ifdef __cplusplus +} +#endif + +#endif // APP_MAIN_H_