diff --git a/IQviewer.tcl b/IQviewer.tcl deleted file mode 100644 index 69180ce..0000000 --- a/IQviewer.tcl +++ /dev/null @@ -1,81 +0,0 @@ -#See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53021.pdf -#and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii52003.pdf - -# run with ~/NAS/primary_a/Projects/fpga/prime/quartus/bin/quartus_stp_tcl -# not quartus_sh - -# ~/NAS/primary_a/Projects/fpga/prime/quartus/bin/quartus_stp_tcl -t IQviewer.tcl - -proc pause {{message "Hit Enter to continue ==> "}} { - puts -nonewline $message - flush stdout - gets stdin -} - -proc hex_to_signed {value} { - set sign [expr {($value & 0b10000000000000000000000000000000)}] - set mag [expr {($value & 0b01111111111111111111111111111111)}] - if {$sign==0} { - set exp 0 - } else { - set exp [expr -2**31] - } - set value [expr {$exp + $mag}] - return $value -} -#thanks Quantum0xE7 on SO! - - - - -set usb [lindex [get_hardware_names] 0] -set device_name [lindex [get_device_names -hardware_name $usb] 0] - -start_insystem_source_probe -device_name $device_name -hardware_name $usb - -set output_filename "../eppenwolf/runs/phage_experiment_6/fluorescence_slide_1.csv" - -array set waveform {} - - -while {1} { - - set previous_count_binary [read_probe_data -instance_index 0]; - set I_count_binary [read_probe_data -instance_index 0]; - - while {$I_count_binary == $previous_count_binary} { - puts "Integrating..." - after 1000; - set I_count_binary [read_probe_data -instance_index 0]; - set Q_count_binary [read_probe_data -instance_index 1]; - - } - - binary scan [binary format B64 [format "%064s" $I_count_binary]] W I_count_binary_scanned - binary scan [binary format B64 [format "%064s" $Q_count_binary]] W Q_count_binary_scanned - - set I_count [hex_to_signed $I_count_binary_scanned]; - set Q_count [hex_to_signed $Q_count_binary_scanned]; - - puts $I_count; - puts $Q_count; - - puts [expr { sqrt((double($I_count)*double($I_count)) + (double($Q_count)*double($Q_count))) } ]; - puts [expr { atan( $Q_count / double($I_count)) }]; - - #set addc_bin [read_probe_data -instance_index 1]; - #binary scan [binary format B64 [format "%064s" $addc_bin]] W addc - - pause; - - - -} - - -#set value "11111111111111111111111111111111"; - - - - -#end_interactive_probe; diff --git a/clocks.sdc b/clocks.sdc deleted file mode 100644 index dbeaf3c..0000000 --- a/clocks.sdc +++ /dev/null @@ -1,9 +0,0 @@ -create_clock -name "clock_50_mhz" -period 20.0ns [get_ports {clock_50_mhz}] -create_clock -name "main_clock" -period 5.0ns [get_ports {main_clock}] - -create_clock -name "PMT_in" -period 5.0ns [get_ports {PMT_in}] -create_clock -name "light_source_pin" -period 300ns [get_ports {light_source_pin}] - - -derive_pll_clocks -derive_clock_uncertainty \ No newline at end of file diff --git a/fluorescence_FPGA.qsf b/fluorescence_FPGA.qsf deleted file mode 100644 index d106f4d..0000000 --- a/fluorescence_FPGA.qsf +++ /dev/null @@ -1,76 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition -# Date created = 00:35:40 November 05, 2020 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# fluorescence_FPGA_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name DEVICE EP4CE22F17C6 -set_global_assignment -name TOP_LEVEL_ENTITY fluorescence_FPGA -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:35:40 NOVEMBER 05, 2020" -set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_location_assignment PIN_D3 -to light_source_pin -set_location_assignment PIN_R8 -to clock_50_mhz -set_location_assignment PIN_C3 -to PMT_in -set_location_assignment PIN_A3 -to pulse_out_pin -set_location_assignment PIN_A15 -to LEDs[0] -set_location_assignment PIN_A13 -to LEDs[1] -set_location_assignment PIN_B13 -to LEDs[2] -set_location_assignment PIN_A11 -to LEDs[3] -set_location_assignment PIN_D1 -to LEDs[4] -set_location_assignment PIN_F3 -to LEDs[5] -set_location_assignment PIN_B1 -to LEDs[6] -set_location_assignment PIN_L3 -to LEDs[7] -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name QIP_FILE altsource_probe/synthesis/altsource_probe.qip -set_global_assignment -name VERILOG_FILE fluorescence_FPGA.v -set_global_assignment -name SDC_FILE clocks.sdc -set_global_assignment -name SOURCE_FILE source.spf -set_global_assignment -name VERILOG_FILE readout.v -set_global_assignment -name QIP_FILE clkgen.qip -set_global_assignment -name QIP_FILE ram.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fluorescence_FPGA.v b/fluorescence_FPGA.v deleted file mode 100644 index 41cea7c..0000000 --- a/fluorescence_FPGA.v +++ /dev/null @@ -1,362 +0,0 @@ - - -module fluorescence_FPGA(PMT_in, light_source_pin, clock_50_mhz, pulse_out_pin, LEDs); - - - reg [63:0] integration_timer= 0; - -// - reg [31:0] in_phase_add_count = 0; - reg [31:0] in_phase_subtract_count = 0; - - reg [31:0] quadrature_add_count = 0; - reg [31:0] quadrature_subtract_count = 0; - - reg [31:0] pulse_out_accumulator= 0; - - reg signed [31:0] in_phase_subtracted_signed_value= 0; - reg signed [31:0] quadrature_subtracted_signed_value= 0; - - reg [31:0] in_phase_count = 0; - reg [31:0] quadrature_count = 0; - - output [7:0] LEDs; - - - localparam [31:0] num_waveform_samples = 40; - - reg [7:0] waveform [(num_waveform_samples-1):0]; - reg [31:0] readout_waveform_index; - wire [31:0] current_waveform_value; - - assign current_waveform_value = waveform[readout_waveform_index]; - - - - wire main_clock; -// wire locked; - assign main_clock = clock_50_mhz; -// -// clkgen clock_generator(clock_50_mhz, main_clock); - - reg [31:0] blank2 = 0; - reg [31:0] blank = 0; - reg s_ena = 0; - reg s_clk = 0; - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (0), - .instance_id ("inpc"), - .probe_width (32), - .source_width (32), - .source_initial_value ("0"), - .enable_metastability ("YES") - ) in_system_sources_probes_0 ( - .source (blank2), // sources.source - .source_ena (s_clk), // .source_ena - .source_clk (s_ena), // source_clk.clk - .probe (in_phase_subtracted_signed_value) // probes.probe - ); - - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (1), - .instance_id ("qadc"), - .probe_width (32), - .source_width (32), - .source_initial_value ("0"), - .enable_metastability ("YES") - ) in_system_sources_probes_1 ( - .source (blank2), // sources.source - .source_ena (s_clk), // .source_ena - .source_clk (s_ena), // source_clk.clk - .probe (quadrature_subtracted_signed_value) // probes.probe - ); - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (2), - .instance_id ("ipcn"), - .probe_width (32), - .source_width (32), - .source_initial_value ("0"), - .enable_metastability ("YES") - ) in_system_sources_probes_2 ( - .source (blank2), // sources.source - .source_ena (s_clk), // .source_ena - .source_clk (s_ena), // source_clk.clk - .probe (in_phase_count) // probes.probe - ); - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (3), - .instance_id ("qacn"), - .probe_width (32), - .source_width (32), - .source_initial_value ("0"), - .enable_metastability ("YES") - ) in_system_sources_probes_3 ( - .source (blank2), // sources.source - .source_ena (s_clk), // .source_ena - .source_clk (s_ena), // source_clk.clk - .probe (quadrature_count) // probes.probe - ); - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (4), - .instance_id ("wfvl"), - .probe_width (32), - .source_width (32), - .source_initial_value ("0"), - .enable_metastability ("YES") - ) in_system_sources_probes_4 ( - .source (blank2), // sources.source - .source_ena (s_clk), // .source_ena - .source_clk (s_ena), // source_clk.clk - .probe (current_waveform_value) // probes.probe - ); - altsource_probe_top #( - .sld_auto_instance_index ("YES"), - .sld_instance_index (5), - .instance_id ("wfix"), - .probe_width (32), - .source_width (32), - .source_initial_value ("0"), - .enable_metastability ("YES") - ) in_system_sources_probes_5 ( - .source (blank2), // sources.source - .source_ena (s_clk), // .source_ena - .source_clk (s_ena), // source_clk.clk - .probe (readout_waveform_index) // probes.probe - ); - - - - - - - - input PMT_in; //GPIO_01 PIN_C3 - input clock_50_mhz; //CLOCK_50 PIN_R8 - output light_source_pin; //GPIO_00 PIN_D3 - output pulse_out_pin; - - reg pulse_out = 0; - - localparam [63:0] main_clock_frequency = 32'd50000000; - - localparam [63:0] integration_time = main_clock_frequency * 10; - - localparam [31:0] light_frequency = 100000; - localparam [31:0] light_modulation_period = ((main_clock_frequency)/(light_frequency)); // * 4 -// assign LEDs = add_count; - assign LEDs = 0; - - - assign pulse_out_pin = pulse_out; - - reg previous_clear_flag = 0; - - reg pulse_captured = 0; - reg prev_pulse_captured = 0; - reg [31:0] light_timer_flag = 0; - - - - always @(posedge PMT_in) - begin - if(PMT_in) - begin - pulse_captured <= !pulse_captured; - in_phase_flag <= in_phase; - quadrature_flag <= quadrature; - light_timer_flag <= light_timer; - - temp <= waveform[pulse_timer_flag_idx] + 1; - - end - - end - - wire [31:0] pulse_timer_flag_idx ; - - assign pulse_timer_flag_idx = light_timer_flag - gate_begin; - - reg in_phase = 0; - reg quadrature = 0; - - reg in_phase_flag = 0; - reg quadrature_flag = 0; - -// assign LEDs[0] = in_phase; -// assign LEDs[1] = quadrature; - - reg double_light_clock = 0; - reg [31:0] double_light_timer = 0; - reg [31:0] light_timer = 0; - - always @(posedge main_clock) - begin - - - double_light_timer <= double_light_timer + 32'd1; - light_timer <= light_timer + 32'd1; - - if(double_light_timer >= (light_modulation_period/2)-1) - //div 2 because the I/Q divides - begin - double_light_timer <= 32'd0; - double_light_clock <= !double_light_clock; - end - - if(light_timer >= (light_modulation_period*2)-1) - begin - light_timer <= 32'd0; - end - - end - - always @(posedge double_light_clock) - begin - in_phase <= !in_phase; - end - - always @(negedge double_light_clock) - begin - quadrature <= !quadrature; - end - - - assign light_source_pin = in_phase; - - - localparam [31:0] gate_begin = light_modulation_period+(light_modulation_period/2); - localparam [31:0] gate_end = (light_modulation_period+(light_modulation_period/2)+num_waveform_samples)-1; - - reg [31:0] temp = 0; - - - always @(posedge main_clock) - begin - - pulse_out <= (light_timer >= gate_begin) && (light_timer < gate_end); - - - integration_timer <= integration_timer + 64'd1; - - if(integration_timer >= integration_time-1) - begin - integration_timer <= 64'd0; - in_phase_subtracted_signed_value <= $signed(in_phase_add_count) - $signed(in_phase_subtract_count); - quadrature_subtracted_signed_value <= $signed(quadrature_add_count) - $signed(quadrature_subtract_count); - - in_phase_count <= in_phase_add_count; - quadrature_count <= quadrature_add_count; - - - in_phase_add_count <= 0; - in_phase_subtract_count <= 0; - quadrature_add_count <= 0; - quadrature_subtract_count <= 0; - - begin_readout_flag <= !begin_readout_flag; - - end - else - begin - /* might drop a pulse or mis-phase once per integration time. not a huge deal I don't think. */ - if(pulse_captured != prev_pulse_captured) - begin - prev_pulse_captured <= pulse_captured; - - if(in_phase_flag) - begin - if(in_phase_add_count < {32{1'b1}}) - begin - in_phase_add_count <= in_phase_add_count + 1; - end - end - else - begin - if(in_phase_subtract_count < {32{1'b1}}) - begin - in_phase_subtract_count <= in_phase_subtract_count + 1; - end - end - - - if(quadrature_flag) - begin - if(quadrature_add_count < {32{1'b1}}) - begin - quadrature_add_count <= quadrature_add_count + 1; - end - end - else - begin - if(quadrature_subtract_count < {32{1'b1}}) - begin - quadrature_subtract_count <= quadrature_subtract_count + 1; - end - end - - - - - if((light_timer_flag >= gate_begin) && (light_timer_flag < gate_end) && !reading_out) - begin - //waveform is captured in the second quadrant. - waveform[pulse_timer_flag_idx] <= temp; - end - - - end - end - - if(reading_out && readout_waveform_index > 0) - begin - waveform[readout_waveform_index - 1] = 32'd0; - end - - end - - - - localparam [31:0] readout_frequency = 100; - localparam [31:0] readout_clock_period = ((main_clock_frequency)/(readout_frequency)); // * 4 - reg [31:0] readout_timer = 0; - - reg begin_readout_flag = 0; - - reg prev_readout_flag = 0; - - reg reading_out = 0; - - always @(posedge main_clock) - begin - - - readout_timer <= readout_timer + 32'd1; - - if(readout_timer >= (readout_clock_period)-1 && readout_waveform_index < num_waveform_samples-2) - begin - readout_timer <= 32'd0; - readout_waveform_index <= readout_waveform_index + 1; - end - - reading_out <= (readout_waveform_index < num_waveform_samples-2); - - if(prev_readout_flag != begin_readout_flag) //reset, begin counting again. - begin - readout_waveform_index <= 0; - prev_readout_flag <= begin_readout_flag; - end - - end - - - -endmodule - - - - diff --git a/monitor.py b/monitor.py deleted file mode 100644 index efc3851..0000000 --- a/monitor.py +++ /dev/null @@ -1,3 +0,0 @@ -ftdi://ftdi:ft232h/1 - -open_from_url() diff --git a/probe_dump.tcl b/probe_dump.tcl deleted file mode 100644 index ff9806b..0000000 --- a/probe_dump.tcl +++ /dev/null @@ -1,114 +0,0 @@ -#See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53021.pdf -#and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii52003.pdf - -# run with ~/NAS/primary_a/Projects/fpga/prime/quartus/bin/quartus_stp_tcl -t probe_dump.tcl -# not quartus_sh - -proc pause {{message "Hit Enter to continue ==> "}} { - puts -nonewline $message - flush stdout - gets stdin -} - -proc hex_to_signed {value} { - set sign [expr {($value & 0b10000000000000000000000000000000)}] - set mag [expr {($value & 0b01111111111111111111111111111111)}] - if {$sign==0} { - set exp 0 - } else { - set exp [expr -2**31] - } - set value [expr {$exp + $mag}] - return $value -} -#thanks Quantum0xE7 on SO! - - - - -set usb [lindex [get_hardware_names] 0] -set device_name [lindex [get_device_names -hardware_name $usb] 0] - -start_insystem_source_probe -device_name $device_name -hardware_name $usb - -set output_filename "../eppenwolf/runs/phage_experiment_7/fluorescence_slide_1.csv" - - -set cuvette 0 - -while {$cuvette < 8} { - pause "move to cuvette $cuvette and hit enter"; - - set previous_count_binary [read_probe_data -instance_index 0]; - set count_binary [read_probe_data -instance_index 0]; - - while {$count_binary == $previous_count_binary} { - #wait for a fresh integration time - after 1000; - set count_binary [read_probe_data -instance_index 0]; - } - - set iter 0; - while {$iter < 5} { - - - set previous_count_binary [read_probe_data -instance_index 0]; - while {$count_binary == $previous_count_binary} { - puts "Integrating..." - after 1000; - set count_binary [read_probe_data -instance_index 0]; - } - - set I_count_binary [read_probe_data -instance_index 0]; - set Q_count_binary [read_probe_data -instance_index 1]; - set ipcn_binary [read_probe_data -instance_index 2]; - set qacn_binary [read_probe_data -instance_index 3]; - - binary scan [binary format B64 [format "%064s" $I_count_binary]] W I_count_binary_scanned - binary scan [binary format B64 [format "%064s" $Q_count_binary]] W Q_count_binary_scanned - binary scan [binary format B64 [format "%064s" $ipcn_binary]] W ipcn - binary scan [binary format B64 [format "%064s" $qacn_binary]] W qacn - - set I_count [hex_to_signed $I_count_binary_scanned]; - set Q_count [hex_to_signed $Q_count_binary_scanned]; - - set mag [expr { sqrt((double($I_count)*double($I_count)) + (double($Q_count)*double($Q_count))) } ]; - set phase [expr { atan( $Q_count / double($I_count)) }]; - - - set outfile [open $output_filename a] - - puts -nonewline $outfile $cuvette; - puts -nonewline $outfile ","; - puts -nonewline $outfile $I_count; - puts -nonewline $outfile ","; - puts -nonewline $outfile $Q_count; - puts -nonewline $outfile ","; - puts -nonewline $outfile $ipcn; - puts -nonewline $outfile ","; - puts -nonewline $outfile $qacn; - puts -nonewline $outfile ","; - puts -nonewline $outfile $mag; - #puts -nonewline $outfile ","; - #puts -nonewline $outfile $phase; - puts -nonewline $outfile "\n"; - - close $outfile; # no buffering - - puts $I_count; - - incr iter; - - } - - - incr cuvette; -} - - -#set value "11111111111111111111111111111111"; - - - - -#end_interactive_probe; diff --git a/waveformviewer.tcl b/waveformviewer.tcl deleted file mode 100644 index 66cdf21..0000000 --- a/waveformviewer.tcl +++ /dev/null @@ -1,90 +0,0 @@ -#See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53021.pdf -#and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii52003.pdf - -# run with ~/NAS/primary_a/Projects/fpga/prime/quartus/bin/quartus_stp_tcl -# not quartus_sh - -proc no-op {args} {} -proc pause {{message "Hit Enter to continue ==> "}} { - puts -nonewline $message - flush stdout - gets stdin -} - -proc hex_to_signed {value} { - set sign [expr {($value & 0b10000000000000000000000000000000)}] - set mag [expr {($value & 0b01111111111111111111111111111111)}] - if {$sign==0} { - set exp 0 - } else { - set exp [expr -2**31] - } - set value [expr {$exp + $mag}] - return $value -} -#thanks Quantum0xE7 on SO! - - - - -set usb [lindex [get_hardware_names] 0] -set device_name [lindex [get_device_names -hardware_name $usb] 0] - -start_insystem_source_probe -device_name $device_name -hardware_name $usb - -set output_filename "../eppenwolf/runs/phage_experiment_7/fluorescence_slide_1.csv" - - -set num_waveform_samples 38 - - - -while {1} { - - set waveform [list ] - - set binary_index [read_probe_data -instance_index 5]; - set binary_waveform_count [read_probe_data -instance_index 4]; - binary scan [binary format B64 [format "%064s" $binary_index]] W waveform_index - binary scan [binary format B64 [format "%064s" $binary_waveform_count]] W waveform_count - - while {$waveform_index >= $num_waveform_samples-1} { - set binary_index [read_probe_data -instance_index 5]; - binary scan [binary format B64 [format "%064s" $binary_index]] W waveform_index - } - set prev_index 0; - while {$waveform_index < $num_waveform_samples-1} { - # unsigned - - if { $waveform_index != $prev_index } { - set prev_index $waveform_index; - lappend waveform $waveform_count; - puts $waveform_index; - } - - #lset waveform $waveform_index $waveform_count */ - set binary_index [read_probe_data -instance_index 5]; - after 1; - set binary_waveform_count [read_probe_data -instance_index 4]; - binary scan [binary format B64 [format "%064s" $binary_index]] W waveform_index - binary scan [binary format B64 [format "%064s" $binary_waveform_count]] W waveform_count - } - - puts $waveform; -} - - -#set value "11111111111111111111111111111111"; -while {1} { - set binary_index [read_probe_data -instance_index 5]; - set binary_waveform_count [read_probe_data -instance_index 4]; - binary scan [binary format B64 [format "%064s" $binary_index]] W waveform_index - binary scan [binary format B64 [format "%064s" $binary_waveform_count]] W waveform_count - puts $waveform_index; - puts $waveform_count; -} - - - - -#end_interactive_probe;