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instructions.c
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/**
* Copyright 2022 University of Adelaide
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*declares all supported x86_64 assembly instructions*/
#include "instructions.h"
#include "common.h"
#include "enums.h"
// clang-format off
const struct opd_format_table OPD_FORMAT_TABLE[] = {
// first operand does not exist or is an immediate
{n, {'\0'}}, {n, "i"},
// first operand is a memory reference
{m, "m"}, {mi, "mi"}, {mr, "mr"},
{mri, "mri"}, {mrr, "mrr"}, {mv, "mv"},
{my, "my"},
// first operand is a register
{r, "r"}, {ri, "ri"}, {rm, "rm"},
{rmi, "rmi"}, {rmr, "rmr"}, {rr, "rr"},
{rri, "rri"}, {rrm, "rrm"}, {rrr, "rrr"},
{rv, "rv"},
// first operand is a xmm register
{vi, "vi"}, {vr, "vr"}, {vm, "vm"},
{vv, "vv"}, {vvm, "vvm"}, {vvmi,"vvmi"},
{vvv, "vvv"}, {vvvi,"vvvi"},
// first operand is a ymm register
{ym, "ym"}, {yy, "yy"}, {yym, "yym"},
{yymi,"yymi"}, {yyy, "yyy"}, {yyyi,"yyyi"},
// operand format not found
{opd_error, "error"}};
const struct instr_table INSTR_TABLE[] = {
{{'\0'}, EOI, {NA, NA}, NA, OTHER, NA, NA, 0, {0}},
{{'\0'}, LABEL, {NA, NA}, NA, OTHER, NA, NA, 0, {0}},
{{'\0'}, SKIP, {NA, NA}, NA, OTHER, NA, NA, 0, {0}},
{"adc", adc, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x10, REG}},
{{'\0'}, adc, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x12, REG}},
{{'\0'}, adc, {mi, ri}, M, OPERATION, 1, 2, 3, {REX, 0x80, REG}},
{{'\0'}, adc, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x14}},
{"adcx", adcx, {rr, rm}, RM, OTHER, NA, NA, 6, {0x66, REX, 0x0f, 0x38, 0xf6, REG}},
{"add", add, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x00, REG}},
{{'\0'}, add, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x02, REG}},
{{'\0'}, add, {mi, ri}, M, OPERATION, 1, 0, 3, {REX, 0x80, REG}},
{{'\0'}, add, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x04}},
{"adox", adox, {rr, rm}, RM, OTHER, NA, NA, 6, {0xf3, REX, 0x0f, 0x38, 0xf6, REG}},
{"and", and, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x20, REG}},
{{'\0'}, and, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x22, REG}},
{{'\0'}, and, {mi, ri}, M, OPERATION, 1, 4, 3, {REX, 0x80, REG}},
{{'\0'}, and, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x24}},
{"bextr", bextr, {rrr, rmr}, RMV, VECTOR_EXT, NA, NA, 3, {VEX(NDS,LZ,NONE,X0F38,W0_W1), 0xf7, REG}},
{"bzhi", bzhi, {rrr, rmr}, RMV, VECTOR_EXT, NA, NA, 3, {VEX(NDS,LZ,NONE,X0F38,W0_W1), 0xf5, REG}},
{"call", call, {n, n}, D, CONTROL_FLOW, NA, NA, 1, {0xe8}},
{{'\0'}, call, {r, m}, O, CONTROL_FLOW, NA, 2, 3, {REX, 0xff, REG}},
{{'\0'}, call, {NA, NA}, D, CONTROL_FLOW, NA, NA, 3, {0xff, 0x14, 0x25}},
{"clc", clc, {n, n}, NA, OTHER, NA, NA, 1, {0xf8}},
{"cpuid", cpuid, {n, n}, NA, OTHER, NA, NA, 2, {0x0f, 0xa2}},
{"clflush", clflush, {r, m}, M, BYTE_OPD, NA, 7, 4, {REX, 0x0f, 0xae, REG}},
{"cmova", cmova, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x47, REG}},
{"cmovae", cmovae, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x43, REG}},
{"cmovb", cmovb, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x42, REG}},
{"cmovbe", cmovbe, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x46, REG}},
{"cmovc", cmovc, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x42, REG}},
{"cmove", cmove, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x44, REG}},
{"cmovg", cmovg, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4f, REG}},
{"cmovge", cmovge, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4d, REG}},
{"cmovl", cmovl, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4c, REG}},
{"cmovle", cmovle, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4e, REG}},
{"cmovna", cmovna, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x46, REG}},
{"cmovnae", cmovnae, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x42, REG}},
{"cmovnb", cmovnb, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x43, REG}},
{"cmovnbe", cmovnbe, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x47, REG}},
{"cmovnc", cmovnc, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x43, REG}},
{"cmovne", cmovne, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x45, REG}},
{"cmovng", cmovng, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4e, REG}},
{"cmovnge", cmovnge, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4c, REG}},
{"cmovnl", cmovnl, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4d, REG}},
{"cmovnle", cmovnle, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4f, REG}},
{"cmovno", cmovno, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x41, REG}},
{"cmovnp", cmovnp, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4b, REG}},
{"cmovns", cmovns, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x49, REG}},
{"cmovnz", cmovnz, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x45, REG}},
{"cmovo", cmovo, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x40, REG}},
{"cmovp", cmovp, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4a, REG}},
{"cmovpe", cmovpe, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4a, REG}},
{"cmovpo", cmovpo, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x4b, REG}},
{"cmovs", cmovs, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x48, REG}},
{"cmovz", cmovz, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0x44, REG}},
{"cmp", cmp, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x38, REG}},
{{'\0'}, cmp, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x3a, REG}},
{{'\0'}, cmp, {mi, ri}, M, OPERATION, 1, 7, 3, {REX, 0x80, REG}},
{{'\0'}, cmp, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x3c}},
{"cvtdq2pd", cvtdq2pd, {NA, vv}, RM, VECTOR, NA, NA, 5, {0xf3, REX, 0x0f, 0xe6, REG}},
{"cvtpd2dq", cvtpd2dq, {NA, vv}, RM, VECTOR, NA, NA, 5, {0xf2, REX, 0x0f, 0xe6, REG}},
{"dec", dec, {r, m}, M, OTHER, 1, 1, 3, {REX, 0xfe, REG}},
{"divpd", divpd, {NA, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x5e, REG}},
{"imul", imul, {rri, rmi}, RM, OTHER, 1, NA, 3, {REX, 0x68, REG}},
{{'\0'}, imul, {rr, rm}, RM, OTHER, NA, NA, 4, {REX, 0x0f, 0xaf, REG}},
{{'\0'}, imul, {NA, r}, M, OTHER, 1, 5, 3, {REX, 0xf6, REG}},
{"inc", inc, {r, m}, M, OTHER, 1, 0, 3, {REX, 0xfe, REG}},
{"ja", ja, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x87}},
{{'\0'}, ja, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x77, ib}},
{"jae", jae, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x83}},
{{'\0'}, jae, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x73, ib}},
{"jb", jb, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x82}},
{{'\0'}, jb, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x72, ib}},
{"je", je, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x84}},
{{'\0'}, je, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x74, ib}},
{"jg", jg, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x8f}},
{{'\0'}, jg, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x7f, ib}},
{"jge", jge, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x8d}},
{{'\0'}, jge, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x7d, ib}},
{{'\0'}, jbe, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x86}},
{{'\0'}, jbe, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x76, ib}},
{"jl", jl, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x8c}},
{{'\0'}, jl, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x7c, ib}},
{"jle", jle, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x8e}},
{{'\0'}, jle, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x7e, ib}},
{"jmp", jmp, {n, n}, D, CONTROL_FLOW, NA, NA, 1, {0xe9}},
{{'\0'}, jmp, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0xeb, ib}},
{{'\0'}, jmp, {r, m}, O, CONTROL_FLOW, NA, 4, 3, {REX, 0xff, REG}},
{"jne", jne, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x85}},
{{'\0'}, jne, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x75, ib}},
{"jno", jno, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x81}},
{{'\0'}, jno, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x71, ib}},
{"jnp", jnp, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x8b}},
{{'\0'}, jnp, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x7b, ib}},
{"jns", jns, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x89}},
{{'\0'}, jns, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x79, ib}},
{"jo", jo, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x80}},
{{'\0'}, jo, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x70, ib}},
{"jp", jp, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x8a}},
{{'\0'}, jp, {n, n}, S, CONTROL_FLOW, NA, NA, 2, {0x7a, ib}},
{"jrcxz", jrcxz, {n, n}, S, CONTROL_FLOW, NA, NA, 2, {0xe3, ib}},
{{'\0'}, jrcxz, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0xe3, ib}},
{"js", js, {n, n}, D, CONTROL_FLOW, NA, NA, 2, {0x0f, 0x88}},
{{'\0'}, js, {NA, NA}, S, CONTROL_FLOW, NA, NA, 2, {0x78, ib}},
{"lea", lea, {NA, rm}, RM, OTHER, NA, NA, 3, {REX, 0x8d, REG}},
{"lfence", lfence, {n, n}, NA, OTHER, NA, NA, 3, {0x0f, 0xae, 0xe8}},
{"mfence", mfence, {n, n}, NA, OTHER, NA, NA, 3, {0x0f, 0xae, 0xf0}},
{"mov", mov, {rr, mr}, MR, DATA_TRANSFER, 1, NA, 3, {REX, 0x88, REG}},
{{'\0'}, mov, {NA, rm}, RM, DATA_TRANSFER, 1, NA, 3, {REX, 0x8a, REG}},
{{'\0'}, mov, {mi, ri}, I, DATA_TRANSFER, 1, NA, 2, {REX, 0xb0+rd}},
{{'\0'}, mov, {NA, NA}, M, DATA_TRANSFER, 1, 0, 3, {REX, 0xc6, REG}},
{"movd", movd, {vm, vr}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x6e, REG}},
{{'\0'}, movd, {mv, rv}, MR, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x7e, REG}},
{"movntdqa", movntdqa, {NA, vm}, RM, VECTOR, NA, NA, 6, {0x66, REX, 0x0f, 0x38, 0x2a, REG}},
{"movntq", movntq, {NA, mr}, MR, VECTOR, NA, NA, 4, {REX, 0x0f, 0xe7, REG}},
{"movq", movq, {NA, vr}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x6e, REG}},
{{'\0'}, movq, {NA, mv}, MR, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xd6, REG}},
{{'\0'}, movq, {NA, rv}, MR, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x7e, REG}},
{{'\0'}, movq, {vm, vv}, RM, VECTOR, NA, NA, 5, {0xf3, REX, 0x0f, 0x7e, REG}},
{"movzx", movzx, {rr, rm}, RM, DATA_TRANSFER, NA, NA, 4, {REX, 0x0f, 0xb6, REG}},
{"mulpd", mulpd, {NA, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x59, REG}},
{"mul", mul, {r, m}, M, OPERATION, NA, 4, 3, {REX, 0xf7, REG}},
{"mulx", mulx, {rrr, rrm}, RVM, VECTOR_EXT, NA, NA, 3, {VEX(NDD,LZ,XF2,X0F38,W0_W1), 0xf6, REG}},
{"neg", neg, {r, m}, M, OTHER, 1, 3, 3, {REX, 0xf6, REG}},
{"nop", nop, {n, n}, NA, OTHER, NA, NA, 1, {NOP}},
{"nop2", nop, {n, n}, NA, OTHER, NA, NA, 2, {NOP2}},
{"nop3", nop, {n, n}, NA, OTHER, NA, NA, 3, {NOP3}},
{"nop4", nop, {n, n}, NA, OTHER, NA, NA, 4, {NOP4}},
{"nop5", nop, {n, n}, NA, OTHER, NA, NA, 5, {NOP5}},
{"nop6", nop, {n, n}, NA, OTHER, NA, NA, 6, {NOP6}},
{"nop7", nop, {n, n}, NA, OTHER, NA, NA, 7, {NOP7}},
{"nop8", nop, {n, n}, NA, OTHER, NA, NA, 8, {NOP8}},
{"nop9", nop, {n, n}, NA, OTHER, NA, NA, 9, {NOP9}},
{"nop10", nop, {n, n}, NA, OTHER, NA, NA, 10, {NOP10}},
{"nop11", nop, {n, n}, NA, OTHER, NA, NA, 11, {NOP11}},
{"not", not, {r, m}, M, OTHER, 1, 2, 3, {REX, 0xf6, REG}},
{"or", or, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x08, REG}},
{{'\0'}, or, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x0a, REG}},
{{'\0'}, or, {mi, ri}, M, OPERATION, 1, 1, 3, {REX, 0x80, REG}},
{{'\0'}, or, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x0c}},
{"paddb", paddb, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xfc, REG}},
{{'\0'}, paddb, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xfc, REG}},
{"paddd", paddd, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xfe, REG}},
{{'\0'}, paddd, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xfe, REG}},
{"paddq", paddq, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xd4, REG}},
{{'\0'}, paddq, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xd4, REG}},
{"paddw", paddw, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xfd, REG}},
{{'\0'}, paddw, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xfd, REG}},
{"pand", pand, {NA, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xdb, REG}},
{{'\0'}, pand, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xdb, REG}},
{"pandn", pandn, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xdf, REG}},
{{'\0'}, pandn, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xdf, REG}},
{"pmulhrsw", pmulhrsw, {vm, vv}, RM, VECTOR, NA, NA, 6, {0x66, REX, 0x0f, 0x38, 0x0b, REG}},
{{'\0'}, pmulhrsw, {rm, rr}, RM, VECTOR, NA, NA, 5, {REX, 0x0f, 0x38, 0x0b, REG}},
{"pmulhuw", pmulhuw, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xe4, REG}},
{{'\0'}, pmulhuw, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xe4, REG}},
{"pmulhw", pmulhw, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xe5, REG}},
{{'\0'}, pmulhw, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xe5, REG}},
{"pmulld", pmulld, {vm, vv}, RM, VECTOR, NA, NA, 6, {0x66, REX, 0x0f, 0x38, 0x40, REG}},
{"pmuldq", pmuldq, {vm, vv}, RM, VECTOR, NA, NA, 6, {0x66, REX, 0x0f, 0x38, 0x28, REG}},
{"pmullw", pmullw, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xd5, REG}},
{{'\0'}, pmullw, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xd5, REG}},
{"pmuludq", pmuludq, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xf4, REG}},
{{'\0'}, pmuludq, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xf4, REG}},
{"pop", pop, {NA, r }, O, DATA_TRANSFER, NA, NA, 2, {REX, 0x58+rd}},
{"por", por, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xeb, REG}},
{{'\0'}, por, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xeb, REG}},
{"prefetcht0", prefetcht0, {r, m}, M, BYTE_OPD, NA, 1, 4, {REX, 0x0f, 0x18, REG}},
{"prefetcht1", prefetcht1, {r, m}, M, BYTE_OPD, NA, 2, 4, {REX, 0x0f, 0x18, REG}},
{"prefetcht2", prefetcht2, {r, m}, M, BYTE_OPD, NA, 3, 4, {REX, 0x0f, 0x18, REG}},
{"prefetchnta", prefetchnta, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x18, REG}},
{"psrldq", psrldq, {NA, vi}, M, VECTOR, NA, 3, 5, {0x66, REX, 0x0f, 0x73, REG}},
{"psubb", psubb, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xf8, REG}},
{{'\0'}, psubb, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xf8, REG}},
{"psubd", psubd, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xfa, REG}},
{{'\0'}, psubd, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xfa, REG}},
{"psubq", psubq, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xfb, REG}},
{{'\0'}, psubq, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xfb, REG}},
{"psubw", psubw, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xf9, REG}},
{{'\0'}, psubw, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xf9, REG}},
{"pxor", pxor, {vm, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0xef, REG}},
{{'\0'}, pxor, {rm, rr}, RM, VECTOR, NA, NA, 4, {REX, 0x0f, 0xef, REG}},
{"punpcklqdq", punpcklqdq, {NA, vv}, RM, VECTOR, NA, NA, 5, {0x66, REX, 0x0f, 0x6c, REG}},
{"push", push, {NA, r}, O, DATA_TRANSFER, NA, NA, 2, {REX, 0x50+rd}},
{{'\0'}, push, {NA, m}, O, DATA_TRANSFER, NA, NA, 3, {REX, 0xff, 0x30+rd}},
{{'\0'}, push, {n, n}, I, DATA_TRANSFER, NA, NA, 2, {0x6a, ib}},
{{'\0'}, push, {NA, NA}, I, PAD_ALWAYS, NA, NA, 1, {0x68}},
{"rcr", rcr, {mi, ri}, M, SHIFT, 1, 3, 4, {REX, 0xd0, REG, ib}},
{{'\0'}, rcr, {NA, NA}, M, SHIFT, 1, 2, 4, {REX, 0xc1, REG, ib}},
{"rdpmc", rdpmc, {n, n}, NA, OTHER, NA, NA, 2, {0x0f, 0x33}},
{"rdpru", rdpru, {n, n}, NA, OTHER, NA, NA, 3, {0x0f, 0x01, 0xFD}},
{"rdtsc", rdtsc, {n, n}, NA, OTHER, NA, NA, 2, {0x0f, 0x31}},
{"rdtscp", rdtscp, {n, n}, NA, OTHER, NA, NA, 3, {0x0f, 0x01, 0xf9}},
{"ret", ret, {n, n}, NA, CONTROL_FLOW, NA, NA, 1, {0xc3}},
{"ror", ror, {NA, ri}, M, SHIFT, NA, 1, 4, {REX, 0xd1, REG, ib}},
{{'\0'}, ror, {NA, NA}, M, SHIFT, NA, 1, 4, {REX, 0xc1, REG, ib}},
{"rorx", rorx, {rri, rmi}, RM, VECTOR_EXT, NA, NA, 4, {VEX(NNN,LZ,XF2,X0F3A,W0_W1), 0xf0, REG, ib}},
{"sal", sal, {mi, ri}, M, SHIFT, 1, 4, 4, {REX, 0xd0, REG, ib}},
{{'\0'}, sal, {NA, NA}, M, SHIFT, 1, 4, 4, {REX, 0xc0, REG, ib}},
{{'\0'}, sal, {mr, rr}, M, SHIFT, 1, 4, 3, {REX, 0xd2, REG}},
{"sar", sar, {mi, ri}, M, SHIFT, 1, 7, 4, {REX, 0xd0, REG, ib}},
{{'\0'}, sar, {NA, NA}, M, SHIFT, 1, 7, 4, {REX, 0xc0, REG, ib}},
{{'\0'}, sar, {mr, rr}, M, SHIFT, 1, 7, 3, {REX, 0xd2, REG}},
{"sarx", sarx, {rrr, rmr}, RMV, VECTOR_EXT, NA, NA, 3, {VEX(NDS,LZ,XF3,X0F38,W0_W1), 0xf7, REG}},
{"sbb", sbb, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x18, REG}},
{{'\0'}, sbb, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x1a, REG}},
{{'\0'}, sbb, {mi, ri}, M, OPERATION, 1, 3, 3, {REX, 0x80, REG}},
{{'\0'}, sbb, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x1c}},
{"seta", seta, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x97, REG}},
{"setae", setae, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x93, REG}},
{"setb", setb, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x92, REG}},
{"setbe", setbe, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x96, REG}},
{"setc", setc, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x92, REG}},
{"sete", sete, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x94, REG}},
{"setg", setg, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9f, REG}},
{"setge", setge, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9d, REG}},
{"setl", setl, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9c, REG}},
{"setle", setle, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9e, REG}},
{"setna", setna, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x96, REG}},
{"setnae", setnae, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x92, REG}},
{"setnb", setnb, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x93, REG}},
{"setnbe", setnbe, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x97, REG}},
{"setnc", setnc, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x93, REG}},
{"setne", setne, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x95, REG}},
{"setng", setng, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9e, REG}},
{"setnge", setnge, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9c, REG}},
{"setnl", setnl, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9d, REG}},
{"setnle", setnle, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9f, REG}},
{"setno", setno, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x91, REG}},
{"setnp", setnp, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9b, REG}},
{"setns", setns, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x99, REG}},
{"setnz", setnz, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x95, REG}},
{"seto", seto, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x90, REG}},
{"setp", setp, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9a, REG}},
{"setpe", setpe, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9a, REG}},
{"setpo", setpo, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x9b, REG}},
{"sets", sets, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x98, REG}},
{"setz", setz, {r, m}, M, BYTE_OPD, NA, 0, 4, {REX, 0x0f, 0x94, REG}},
{"sfence", sfence, {n, n}, NA, OTHER, NA, NA, 3, {0x0f, 0xae, 0xf8}},
{"shl", shl, {mi, ri}, M, SHIFT, 1, 4, 4, {REX, 0xd0, REG, ib}},
{{'\0'}, shl, {NA, NA}, M, SHIFT, 1, 4, 4, {REX, 0xc0, REG, ib}},
{{'\0'}, shl, {mr, rr}, M, SHIFT, 1, 4, 3, {REX, 0xd2, REG}},
{"shld", shld, {rri, mri}, MR, OTHER, NA, NA, 5, {REX, 0x0f, 0xa4, REG, ib}},
{{'\0'}, shld, {rrr, mrr}, MR, OTHER, NA, NA, 4, {REX, 0x0f, 0xa5, REG}},
{"shlx", shlx, {rrr, rmr}, RMV, VECTOR_EXT, NA, NA, 3, {VEX(NDS,LZ,X66,X0F38,W0_W1), 0xf7, REG}},
{"shr", shr, {mi, ri}, M, SHIFT, 1, 5, 4, {REX, 0xd0, REG, ib}},
{{'\0'}, shr, {NA, NA}, M, SHIFT, 1, 5, 4, {REX, 0xc0, REG, ib}},
{{'\0'}, shr, {mr, rr}, M, SHIFT, 1, 5, 3, {REX, 0xd2, REG}},
{"shrd", shrd, {mri, rri}, MR, OTHER, 2, NA, 4, {REX, 0x0f, 0xa9, REG}},
{"shrx", shrx, {rrr, rmr}, RMV, VECTOR_EXT, NA, NA, 3, {VEX(NDS,LZ,XF2,X0F38,W0_W1), 0xf7, REG}},
{"sub", sub, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x28, REG}},
{{'\0'}, sub, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x2a, REG}},
{{'\0'}, sub, {mi, ri}, M, OPERATION, 1, 5, 3, {REX, 0x80, REG}},
{{'\0'}, sub, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x2c}},
{"test", test, {rr, mr}, MR, PAD_ALWAYS, 1, NA, 3, {REX, 0x84, REG}},
{{'\0'}, test, {mi, ri}, M, PAD_ALWAYS, 1, 0, 3, {REX, 0xf6, REG}},
{{'\0'}, test, {NA, NA}, I, PAD_ALWAYS, 1, NA, 2, {REX, 0xa8}},
{"vaddpd", vaddpd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0x58, REG}},
{"vdivpd", vdivpd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0x5e, REG}},
{"vmovupd", vmovupd, {ym, yy}, RM, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B256,X66,X0F,WIG), 0x10, REG}},
{{'\0'}, vmovupd, {my, NA}, MR, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B256,X66,X0F,WIG), 0x11, REG}},
{{'\0'}, vmovupd, {vm, vv}, RM, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B128,X66,X0F,WIG), 0x10, REG}},
{{'\0'}, vmovupd, {mv, NA}, MR, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B128,X66,X0F,WIG), 0x11, REG}},
{"vmovdqu", vmovdqu, {ym, yy}, RM, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B256,XF3,X0F,WIG), 0x6f, REG}},
{{'\0'}, vmovdqu, {my, NA}, MR, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B256,XF3,X0F,WIG), 0x7f, REG}},
{{'\0'}, vmovdqu, {vm, vv}, RM, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B128,XF3,X0F,WIG), 0x6f, REG}},
{{'\0'}, vmovdqu, {mv, NA}, MR, VECTOR_AVX, NA, NA, 3, {VEX(NNN,B128,XF3,X0F,WIG), 0x7f, REG}},
{"vmulpd", vmulpd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0x59, REG}},
{"vpaddb", vpaddb, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xfc, REG}},
{{'\0'}, vpaddb, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xfc, REG}},
{"vpaddd", vpaddd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xfe, REG}},
{{'\0'}, vpaddd, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xfe, REG}},
{"vpaddq", vpaddq, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xd4, REG}},
{{'\0'}, vpaddq, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xd4, REG}},
{"vpaddw", vpaddw, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xfd, REG}},
{{'\0'}, vpaddw, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xfd, REG}},
{"vpand", vpand, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xdb, REG}},
{{'\0'}, vpand, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xdb, REG}},
{"vpandn", vpandn, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xdf, REG}},
{{'\0'}, vpandn, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xdf, REG}},
{"vpermd", vpermd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F38,W0), 0x36, REG}},
{"vperm2i128", vperm2i128, {yymi,yyyi},RVM, VECTOR_AVX, NA, NA, 4, {VEX(NDS,B256,X66,X0F3A,W0), 0x46, REG, ib}},
{"vperm2f128", vperm2f128, {yymi,yyyi},RVM, VECTOR_AVX, NA, NA, 4, {VEX(NDS,B256,X66,X0F3A,W0), 0x06, REG, ib}},
{"vpmuldq", vpmuldq, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F38,W0), 0x28, REG}},
{{'\0'}, vpmuldq, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F38,W0), 0x28, REG}},
{"vpmulhrsw", vpmulhrsw, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F38,W0), 0x0b, REG}},
{{'\0'}, vpmulhrsw, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F38,W0), 0x0b, REG}},
{"vpmulhuw", vpmulhuw, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xe4, REG}},
{{'\0'}, vpmulhuw, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xe4, REG}},
{"vpmulhw", vpmulhw, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xe5, REG}},
{{'\0'}, vpmulhw, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xe5, REG}},
{"vpmulld", vpmulld, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F38,W0), 0x40, REG}},
{{'\0'}, vpmulld, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F38,W0), 0x40, REG}},
{"vpmullw", vpmullw, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xd5, REG}},
{{'\0'}, vpmullw, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xd5, REG}},
{"vpmuludq", vpmuludq, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xf4, REG}},
{{'\0'}, vpmuludq, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xf4, REG}},
{"vpor", vpor, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xeb, REG}},
{{'\0'}, vpor, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xeb, REG}},
{"vpsubb", vpsubb, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xf8, REG}},
{{'\0'}, vpsubb, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xf8, REG}},
{"vpsubd", vpsubd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xfa, REG}},
{{'\0'}, vpsubd, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xfa, REG}},
{"vpsubq", vpsubq, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xfb, REG}},
{{'\0'}, vpsubq, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xfb, REG}},
{"vpsubw", vpsubw, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xf9, REG}},
{{'\0'}, vpsubw, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xf9, REG}},
{"vpxor", vpxor, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0xef, REG}},
{{'\0'}, vpxor, {vvm, vvv}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B128,X66,X0F,WIG), 0xef, REG}},
{"vsubpd", vsubpd, {yym, yyy}, RVM, VECTOR_AVX, NA, NA, 3, {VEX(NDS,B256,X66,X0F,WIG), 0x5c, REG}},
{"xabort", xabort, {n, n}, I, OTHER, NA, NA, 3, {0xc6, 0xf8, ib}},
{"xbegin", xbegin, {n, n}, NA, OTHER, NA, NA, 2, {0xc7, 0xf8}},
{"xchg", xchg, {rr, rm}, RM, DATA_TRANSFER, 1, NA, 3, {REX, 0x86, REG}},
{{'\0'}, xchg, {NA, NA}, I, DATA_TRANSFER, NA, NA, 2, {REX, 0x90+rd}},
{"xor", xor, {rr, mr}, MR, OPERATION, 1, NA, 3, {REX, 0x30, REG}},
{{'\0'}, xor, {NA, rm}, RM, OPERATION, 1, NA, 3, {REX, 0x32, REG}},
{{'\0'}, xor, {mi, ri}, M, OPERATION, 1, 6, 3, {REX, 0x80, REG}},
{{'\0'}, xor, {NA, NA}, I, OPERATION, 1, NA, 2, {REX, 0x34}},
{"xend", xend, {n, n}, NA, CONTROL_FLOW, NA, NA, 3, {0x0f, 0x01, 0xd5}},
{{'\0'}, NA, {NA, NA}, NA, OTHER, NA, NA, 0, {0}}};
_Atomic(int) instr_table_index[LETTERS_IN_ALPHABET] = {0}; // NOLINT
_Atomic(int) opd_format_table_index[LETTERS_IN_ALPHABET] = {0}; // NOLINT